25 - 29 February 2024
San Jose, California, US
Plenary Event
Tuesday Plenary
27 February 2024 • 8:00 AM - 9:20 AM PST | Convention Center, Ballroom 220A 

This session sponsored by:


8:00 AM - 8:40 AM:
Evolution of advanced lithography and patterning in the system technology co-optimization era of Moore's law

Ann Kelleher, Intel Corp. (United States)

The worldwide demand for computing is undergoing a notable shift, driven by factors like AI/ML, the need for ubiquitous connectivity, and a focus on energy efficiency. In pursuit of the industry's commitment to continuous innovation at Moore’s Law cadence, a system technology co-optimization (STCO) approach has been embraced. Consequently, the distinctions between silicon technology and advanced packaging are blurring. This presentation delves into the evolution of advanced lithography and patterning in the STCO era of Moore’s Law, highlighting the ongoing progress in both silicon and advanced packaging. The importance of sharing ecosystem expertise and ideas across silicon and advanced packaging is underscored for reaping significant benefits. Additionally, with the industry aiming to surpass the $1 trillion revenue mark by the end of the decade, the imperative to innovate on the ongoing journey to environmentally sustainable technologies is emphasized.

Ann Kelleher is the executive vice president and general manager of Technology Development at Intel Corporation. Since 2020, she is responsible for the design, research, development, and deployment of the next-generation silicon, advanced packaging, and test technologies that power Intel’s innovation. She joined Intel in 1996 as a process engineer and has worked in areas spanning from litho, thin films, yield, to managing all of Intel’s Global operations including Fab and Assembly Test factories, supply chain and construction. She did her Ph.D. in electrical engineering from University College Cork in Ireland and her post-doc at IMEC.

 

8:40 AM - 9:20 AM
Lithography technology for memory device patterning

Chan Hwang, Samsung (Korea)

High density memory device has become an inevitable demand of processing capabilities and storage in various applications. The high-density memory devices been mainly developed by lithography, the lateral-scaling technology. In 2010s, DUV multi-patterning technique was introduced as a main contributor of the lateral-scaling, which however recently comes at the cost due to expanding of quadruple patterning and reduction of process margin. As a result, EUV lithography has joined into dominant patterning options for maximizing patterning resolution and reducing cost. This presentation presents our latest patterning solutions extending patterning limit beyond sub 10nm, and outlook of future technologies on memory device patterning such as EUV, High-NA, 3D structure, and bonding overlay.

Chan Hwang joined Samsung Electronics Semiconductor R&D Center in 2002 after completing his Ph.D of Mechanical Design and Production Engineering at Seoul National University where he also received his doctorate (1998) and bachelor (1996) degree. Since 2002, he has developed novel photolithography technologies in the Advanced Photo Technology Division, covering optical resolution enhancement technique, scanner implementation, applications, and overlay control etc. for DUV/EUV process. Since 2019, he has been in charge of Memory Photo Process Development in R&D center. Now, he investigates cost-effective patterning process for both DRAM and Flash devices, providing critical solutions for both R&D center and mass production.