Paper 13093-164
The VERITAS 2.3 readout ASIC for the ATHENA Wide Field Imager
17 June 2024 • 17:30 - 19:00 Japan Standard Time | Room G5, North - 1F
Abstract
VERITAS 2.3 is a further step in the development of the VERITAS (VErsatile Readout based on Integrated
Trapezoidal Analog Shapers) ReadOut Integrated Circuit (ROIC) architecture designed for high-speed, low-noise readout of the DEPFET detectors in the Wide Field Imager on ESA’s ATHENA X-ray satellite. The
chip includes 64 channels, delivering a short processing time of 2.5 μs per readout while targeting a system
noise of 3 e− ENC RMS, enabling nearly Fano-limited spectroscopic performance. While the new chip still uses
previous versions’ proven 0.35 μm CMOS technology node, we have employed new foundry and process options for
better manufacturability and improved reliability. An overview of the design and development of VERITAS 2.3
is presented, along with the first standalone functionality and performance measurements conducted using a
dedicated ASIC test setup.
Presenter
Anna-Katharina Schweingruber
Max-Planck-Institut für extraterrestrische Physik (Germany)