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Proceedings Paper

Simulation of continuously logical base cells (CL BC) with advanced functions for analog-to-digital converters and image processors
Author(s): Vladimir G. Krasilenko; Alexander A. Lazarev; Diana V. Nikitovich
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Paper Abstract

The paper considers results of design and modeling of continuously logical base cells (CL BC) based on current mirrors (CM) with functions of preliminary analogue and subsequent analogue-digital processing for creating sensor multichannel analog-to-digital converters (SMC ADCs) and image processors (IP). For such with vector or matrix parallel inputs-outputs IP and SMC ADCs it is needed active basic photosensitive cells with an extended electronic circuit, which are considered in paper. Such basic cells and ADCs based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of the CL BC and ADC of photocurrents and their various possible implementations and its simulations. We consider CL BC for methods of selection and rank preprocessing and linear array of ADCs with conversion to binary codes and Gray codes. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of simple nodes based on current mirrors extends the range of functions performed by the image processor. Each channel of the structure consists of several digital-analog cells (DC) on 15-35 CMOS. The amount of DC does not exceed the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of ADC with iteration is based on one DC-(G) and SHD, and it has only 35 CMOS transistors. In such ADCs easily parallel code can be realized and also serial-parallel output code. The circuits and simulation results of their design with OrCAD are shown. The supply voltage of the DC is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the transformation time is 20÷30nS at 6-8 bit binary or Gray codes. The general power consumption of the ADC with iteration is only 50÷100μW, if the maximum input current is 4μA. Such simple structure of linear array of ADCs with low power consumption and supply voltage 3.3V, and at the same time with good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 40÷50 MHz, and can be increased up to 10 times) and accuracy characteristics are show. The SMC ADCs based on CL BC and CM opens new prospects for realization of linear and matrix IP and photo-electronic structures with matrix operands, which are necessary for neural networks, digital optoelectronic processors, neural-fuzzy controllers.

Paper Details

Date Published: 6 October 2017
PDF: 14 pages
Proc. SPIE 10438, Emerging Imaging and Sensing Technologies for Security and Defence II, 104380K (6 October 2017); doi: 10.1117/12.2280705
Show Author Affiliations
Vladimir G. Krasilenko, Vinnitsa Social Economy Institute (Ukraine)
Alexander A. Lazarev, Vinnitsa National Technical Univ. (Ukraine)
Diana V. Nikitovich, Vinnitsa Social Economy Institute (Ukraine)

Published in SPIE Proceedings Vol. 10438:
Emerging Imaging and Sensing Technologies for Security and Defence II
Keith L. Lewis; Richard C. Hollins; Gerald S. Buller; Robert A. Lamb, Editor(s)

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