A two stage 14bit pipeline-SAR analog-to-digital converter includes a 5.5bit zero-crossing MDAC and a 9bit asynchronous SAR ADC for image sensor readout circuits built in 0.18um CMOS process is described with low power dissipation as well as small chip area. In this design, we employ comparators instead of high gain and high bandwidth amplifier, which consumes as low as 20mW of power to achieve the sampling rate of 40MSps and 14bit resolution.

Date Published: 13 March 2015
PDF: 7 pages
Proc. SPIE 9403, Image Sensors and Imaging Systems 2015, 94030L (13 March 2015); doi: 10.1117/12.2083307

Published in SPIE Proceedings Vol. 9403:
Image Sensors and Imaging Systems 2015
Ralf Widenhorn; Antoine Dupret, Editor(s)