The semiconductor industry’s progress on EUV lithography was a recurring theme at SPIE Advanced Lithography this year.
In presentations at the weeklong event in San Jose, CA (USA) 26 February through 2 March, representatives from ASML, Intel, KLA-Tencor, JSR Corp, IMEC, Samsung, and other organizations all emphasized the progress being made toward manufacturing computer chips using sub-10nm node lithography.
An invited talk on ASML’s new EUV scanner and three plenary talks at the beginning of the week set the stage for much discussion about when, where, and how — plus the occasional if — the next generation of lithography tools will enable high-volume and high-throughput manufacturing at an EUV wavelength of about 13.5 nm.
A recording of a talk by SPIE member Mark van de Kerkhof of ASML on the company’s NXE:3400B EUV scanner and enabling sub-10-nm-node lithography is one of several presentations that SPIE is making available on the SPIE Newsroom and/or the SPIE Digital Library. The scanner is ASML’s first that can produce 125 wafers/hour, the throughput rate needed in production fabs.
SPIE Fellow Donis Flagello (holding award) received the 2017 SPIE Frits Zernike Award in Microlithography during SPIE Advanced Lithography. At right is Bruce Smith, symposium chair. To Flagello’s left are SPIE CEO Eugene Arthurs and Will Conley, symposium cochair.
Frank Abboud, vice president of the Technology and Manufacturing Group at Intel and general manager of Intel’s mask operations, noted in his plenary talk that photomask technologies must be continuously advanced along with EUV sources and other lithography tools in order for EUV lithography to be adopted.
Since photomasks act as diffractive optical elements in the lithography process, modifying all parameters of impingent light including intensity, direction, phase, and polarization, Abboud said EUV sources are “more disruptive to the mask shop than the wafer fab.
“Almost every module in the mask shop is touched,” including blank preparation, fiducial mark patterning, device patterning, black-border patterning, and metrology/characterization, he said.
Abboud described the Intel Mask Operation approach to adopting EUV lithography through supply chain development, consortia, collaboration, co-development, and internal programs. The results include full-field EUV pellicles demonstrated in 2014 and product reticles shipped in 2016. There also have been continuous improvements on methods, including electron-beam technology, to reduce and/or repair mask defects.
Over time, more of the photomask work is done at internal (captive) mask shops like at Intel, with VLSIresearch predicting mask volume will decrease 10%, but cost will increase 30% over the next few years, primarily driven by the capital spending necessary to shift to EUV. However, Abboud predicted, “The next technology paradigm — EUV — will not be gated by mask.”
Ben Tsai, CTO and executive vice president of corporate alliances at KLA-Tencor, also emphasized the importance of investment in inspection and metrology to identify and resolve essentially all defects in his plenary talk.
Noting that inspection and metrology can involve 1000 process steps for an advanced graphics processing unit (GPU), Tsai noted that if each of those steps was 99.5% perfect, less than 1% of manufactured devices would work.
The third plenary talk, by Nobu Koshiba, president and CEO of JSR Corp., covered the advanced computers and computational power needed for EUV lithography success.
Koshiba noted that new materials and processes are already being developed for the next generation of computing, which must be robust enough to transfer huge amounts of data and be a driver for artificial intelligence, autonomous driving, precision medicine, genomic science, and cognitive computing.
Among the advances in new materials and processes, he cited the case of adding a layer of polymer between resist lines to reduce line collapse and issues associated with cleaning increasingly narrow gaps. New materials, such as SiARC, provide extreme etch resistance and selective deposition of materials can also squeeze maximum resolution lithography and chip density with lower defect contributions.
Nearly 2300 people attended SPIE Advanced Lithography 2017, which included more than 550 technical presentations in seven conferences, 14 courses, and a two-day exhibition with 50 exhibitors from the semiconductor lithography community.
SPIE Advanced Lithography 2018 will be held 25 February to 1 March.
- More highlights from SPIE Advanced Lithography
- Recorded presentations available in the SPIE Newsroom
- Proceedings, including some recorded presentations
As EUV technology strives to reach a level of maturity suitable for high-volume manufacturing, advances in the field will be addressed in different forums throughout the year, including SPIE Photomask Technology, 11-14 September in Monterey, CA (USA), where the International Conference on EUV Lithography joins the symposium as part of the program.
Abstracts for SPIE Photomask Technology + EUV Lithography are due 24 April.
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