Solving etch challenges in EUV patterning

06 March 2023
By Hank Hogan
A slide from Nafees Kabir's talk on Plasma etch challenges and innovations at 2023 Advanced Lithography + Patterning.
A slide from Nafees Kabir's talk on plasma etch challenges and innovations at 2023 SPIE Advanced Lithography + Patterning.

In semiconductor manufacturing, you’ve got to be able to put layers down and take them off. It’s the removal of material in the right spots that plays a key role in patterning. Etch processes are therefore critical to advanced manufacturing.

Three papers at the 2023 SPIE Advanced Lithography + Patterning conference show how the industry is responding to the needs of tomorrow’s semiconductor fabrication.

In the first, Nafees Kabir, an Intel research engineer, discussed what high-NA EUV requires of resist processing. High-NA, or 0.55-NA, EUV can print smaller features, but it has a narrower depth of focus than today’s in-production EUV, which has an NA of 0.33. So, the organic chemically amplified resists that Kabir and co-workers investigated must be thinner on the wafer than today’s resists — 50 percent thinner, in fact. That puts NA EUV resists at 25 or so nanometers thick or even less.

“You are working with very, very tiny thicknesses of resist,” Kabir said.

Etch removes the material not covered by the resist, which is good. But it also removes some of the resist as well, which can be bad if the resist gets so thin it can no longer protect what’s beneath it.

So, the Intel group tested a 25-nm resist’s ability to stand up to etch when patterning lines and spaces that were on a sub-26 nm pitch. Thus, the center from one line to the next was 26 nm or so. They found the resist was up to the task — if some special steps were taken to clean up the edges of the resist line in a process known as descumming.

In the second presentation, Jong Park, a technical manager at DuPont Electronics and Industrial, addressed some of the same issues, but he did so in the context of a new resist DuPont developed. The typical organic resist does a poor job of absorbing EUV photons, Park said. So they have a poor starting point for the lithography process, and improving absorption would enable processing at a lower dose.

DuPont researchers noted that iodine readily absorbs EUV photons and that it could be incorporated into the resist easily. Tests of an iodine enhanced resist showed it had 14 percent better absorption.

A slide from Jong Park’s talk on understanding etch properties of advanced chemically amplified EUV resist at 2023 Advanced Lithography + Patterning

A slide from Jong Park’s talk on understanding etch properties of advanced chemically amplified EUV resist at 2023 SPIE Advanced Lithography + Patterning.

But how would an iodine rich resist do in the etch process?

The DuPont team ran a number of tests, comparing a standard resist against one with medium and another with high iodine content. They looked at the etch rate, as well as surface roughness and defects to spot any cases where the resist broke down during etching.

“Increased iodine content did not affect the etch negatively,” Park said in summing up the group’s work. The new resist offered better lithographic performance, with the resulting features on the wafer being more uniform in their critical dimensions.

The third presentation was by Eric Liu manager of Patterning Process Engineering & MTS (Etch & Integration) at the Tokyo Electron Ltd. Technology Center. He noted that semiconductor manufacturing is at an inflection point, with changes in lithography and transistor architecture presenting hurdles that must be overcome. For that, Tokyo Electron is pushing innovations in lithography and etching.

“We are taking a holistic approach to overcome these challenges,” Liu said in discussing the upcoming inflection point.

A slide from Eric Liu’s talk on innovations in lithography and etching at 2023 SPIE Advanced Lithography + Patterning.

A slide from Eric Liu’s talk on innovations in lithography and etching at 2023 SPIE Advanced Lithography + Patterning.

On the lithography front, the company is working on a metal oxide resist that tests show to be promising in opening up the process window, the allowable variation in process parameters that still give acceptable results. A larger process window could mean, for example, that the dose of EUV photons could be either higher or lower than that allowed by a smaller process window. A larger process window, as a result, typically means a higher yield at either a process step or for the chip as a whole during final testing.

As for etch, company researchers studied the effects of introducing extra steps. They found, Liu reported, that using a plasma curing step during etch improved patterning, as measured by looking at a critical parameter.

“We see about a 30 percent line edge roughness reduction by applying this technique,” Liu said. Lower line edge roughness means that features are closer to their designed shape. As a result, yields may be higher because there is less chance for two lines that should be separated to instead touch.

Taken together, these three talks show that etch obstacles remain. They also illustrate that researchers are making progress in a variety of different ways — good news for advanced semiconductor manufacturing.

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