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William H. Arnold III

Mr. William H  Arnold

Chief Scientist and VP Technology Development Center
ASML, US


8555 S. River Parkway

Tempe AZ 85284
United States

tel: 480 383-4034
fax: 480 383-3985
E-mail: bill.arnold@asml.com
Web: http://www.asml.com

Area of Expertise

Silicon processes for integrated circuit memories and microprocessors

Biography

Mr. William H Arnold has been Chief Scientist of ASML, the world's leading manufacturer of microlithographic exposure tools, since 1998. Before that he worked for Advanced Micro Devices 18 years in various roles developing silicon processes for integrated circuit memories and microprocessors. Mr. Arnold is the 2013 President of SPIE.

Lecture Title(s)

Progress in Extreme Ultraviolet Lithography for IC Manufacturing
Optical lithography has been the key manufacturing technology for integrated-circuit production, enabling a million-fold reduction in average transistor length over 50 years. The development of projection scanners, step and repeat tools, and now, step and scan systems at higher numerical apertures and shorter wavelengths have led to today's main lithographic production tool: the 193nm immersion scanner. With 20nm half-pitch fabrication, at half the effective resolution limit, it is necessary to use multiple patterning, either through pattern splitting and multiple exposures, or through a self-aligned spacer process. This leads to one of two consequences: on the one hand, to a significant increase in the number of mask levels, process cost, and manufacturing complexity; and, on the other hand, to significant layout restrictions which require closer collaboration between semiconductor design and manufacturing for optimal imaging results and high yield. Even so, for lithography systems to achieve these small resolutions, there are other requirements: a sharp increase in process overlay ( to achieve nanometer-specific positioning of the projected image on the silicon wafer); and Critical Dimension Uniformity (CDU) ( to specify the nanometer consistency of the projected image). Computational lithography and high-speed diffraction-based metrology are needed to meet these challenges. To relax the complexity of the double-patterning process and layout restrictions, EUV lithography has been developed to support 1x-nm logic and memory fabrication, and has been demonstrated to meet imaging and overlay requirements. The major challenge remaining is productivity!

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