This PDF file contains the front matter associated with SPIE Proceedings Volume 11855, including the Title Page, Copyright information, and Table of Contents.

SMILE is a free and open-source software for the analysis of SEM images of lines and spaces patterns. We developed SMILE, in particular, to provide reliable metrology for images of high-resolution photoresist patterns obtained with EUV lithography. Our motivation is also to improve the consistency of the reported performance parameters, e.g., line-width roughness (LWR) and critical dimension (CD), in the nanolithography and EUVL communities. In its original version, SMILE offered the possibility to measure the CD of the lines and their unbiased LWR. Since its release, the software user interface and core functionalities have been substantially upgraded. In particular, SMILE is now capable of reporting unbiased LWR and LER, performing primary statistical analyses of metrics evaluated over multiple images, and analyzing SEM images of contact hole or pillar arrays. In this paper, we will discuss the new functionalities of SMILE and the algorithms used to detect the contact holes and their parameters.

In this paper, we show the characteristics of particle contamination induced defect footprints and explain the basic principles of their formation during ebeam exposure. To verify these principles, we carried out full 3D Monte Carlo Simulations of electrons impinging on the mask stack (modelled as PMMA, Cr, and SiO₂), covered by a defect layer and compared the simulated contour with SEM images of real defect footprints. The relevant physical property is the deposited energy inside the PMMA layer. First, we verified in our simulations that the deposited energy is indeed antiproportional to the beam energy. In a second step we simulated scattering trajectories of electrons to quantify the nontrivial dependence of deposited energy on the size and thickness of defects as well as defect composition. We also considered shotnoise statistics due to the limited number of electrons in ebeam pattern generation accompanied by gaussian smoothing of the deposited energy representing subsequent processing and demonstrate that considerably increased energy deposition to an ebeam-active resist can occur in direct vicinity of a scattering defect when scattering widens the beam opening angle leading to longer trajectories inside the resist. The pattern generator is variable-shaped electron beam (VSB) with 50 keV energy operated in the high-volume photomask manufacturing facility at AMTC Dresden, the Monte Carlo simulation software is virtualSEM from GenISys GmbH.

In this paper we introduce a method of combining the use of the KLA FlashScan® reticle blank defect inspection system and the KLA LMS IPRO reticle pattern registration metrology system for high-precision mask defect inspection and registration. We investigated EUV mask blanks at various production stages and confirmed the reliable measurement of defect coordinates, which propagate through the multilayer stack towards the surface as well as after the absorber deposition process. During the inspection, in addition to the categorization among various types and sizes of blank defects, unique alignment marks were also placed on the mask. These alignment marks allowed us to use a defined coordinate system, enabling reliable and accurate registration of the defect location even on blank substrates. If the mask shop requires EUV defect coordinates in their own internal coordinate system, matching between the mask shop and blank coordinate systems is achieved by measuring both alignment mark pairs and applying the appropriate coordinate transformation. The combined use of inspection and metrology systems proved to be a cost-effective solution for the development of a defect mitigation strategy with automatic workflow for EUV mask shops and mask blank suppliers.

In semiconductor industry, CD-SEMs (critical dimension scanning electron microscopes) are key enablers for metrology and process control. Additional applications that exploit the potential of CD-SEM equipment have being developed – such as contour extraction algorithms, in order to continue to address the increasing metrology requirements of the semiconductor industry. An important example of the utilization of image information is the industry’s use of full contour extraction for various applications, such as MPC (mask process correction) modeling, OPC (optical proximity correction) modeling, and advanced measurement solutions, especially for newer technologies such as ILT (Inverse Lithography Technology), where the characteristics of the 2D curvilinear patterns are such that standard measurement solutions are no longer an option. As mask errors become more and more critical, providing good measurements is critical for calibrating MPC models, estimating etch bias over complex features, providing CD uniformity analysis, among other. More complex patterns also lead to less robust measurements in traditional CD-SEMs requiring more refined algorithms and statistics control to achieve a good level of certainty. Tool drift can lead to a lack of focus during the image acquisition and induce a blur problem in the image, affecting the quality of the signal to be analyzed, and consequently misleading the measurements. These measurements can induce false statistics and lead to bad decisions in a fab environment. Another important factor for considering over SEM images is the quality of the signal on the pattern edges. This characteristic may have a significant impact over the measurement results, also leading to errors in the production flow. For example, using wrong measurements for addressing etching recipes or for generating MPC models may induce errors in the mask fabrication process, reducing its overall quality. Therefore, being capable of identifying blur on SEM images as well as edge quality variation is an important tool for mask manufacturers to prevent from using erroneous measurements for the decisions required during the entire fabrication flow. In this work, the impact of blur on CD-SEM measurements is evaluated. Also, the impact of the blur over the detection of pattern’s edges is demonstrated over experimental data, coming from three different mask production flows, with different etch signatures and acquisition conditions. The proposed approach enables removing untrustworthy measurements from a calibration or a verification set.

With the transition of EUV lithography to high volume manufacturing, EUV mask metrology has become a critical requirement. At PSI, we are developing RESCAN, a lensless actinic microscope dedicated to EUV mask inspection. RESCAN is based on coherent diffraction imaging (CDI), a method that reconstructs the complex image of the sample through its diffraction spectrum measured with a CCD detector. While this approach can overcome the cons and limitations of traditional optical imaging systems, in CDI, the quality of the recorded diffraction data is crucial for the reliable reconstruction of a high-resolution image. Ultimately, the signal-to-noise ratio of the recorded diffraction data depends on several parameters, such as the reflectance of the sample, the quantum efficiency of the detector, its full well capacity, and the intensity of the illumination. This paper investigates the optimal photon flux for RESCAN and analyzes the relation between the image quality and the EUV illumination intensity for a CDI-based imaging tool dedicated to EUV mask inspection and review.

The Digital Scanner (DS) being developed by Nikon is an optical maskless exposure tool with DUV light source and a micromirror-type spatial light modulator (SLM). The SLM forms a pixelated image; although each micromirror operates in a binary mode, the DS is capable to control pattern edges with subpixel resolution. This is because the pixel size on the wafer plane is smaller than the optical resolution, and therefore multiple pixels can contribute to each point in a projected image. We report simulation results of subpixel edge placement controllability of the DS. Actual exposure results on our experimental tool are also presented.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field/shot-by-field/shot deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay, defectivity and throughput. Advanced memories, such as DRAM and phase change memory are challenging, because the roadmap for these devices calls for continued scaling, eventually reaching half pitches of 14nm and beyond. Scaling also impacts the overlay budget. For DRAM, as an example, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1nm - 2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). This makes a direct printing process, such as NIL an attractive solution. In previous papers, overlay has been addressed by applying methods that are unique to NIL. In 2018, Hiura et al. reported a mix and match overlay (MMO) of 3.4 nm and a single machine overlay (SMO) across the wafer was 2.5nm using an FPA-1200 NZ2C four station cluster tool. These results were achieved by combining a magnification actuator system with a High Order Distortion Correction (HODC) system, thereby enabling correction of high order distortion terms up to K30. The HODC system utilizes a digital micro mirror array to correct distortion on a field-by-field basis. Further improvements to the system have been achieved by extending the range of the HODC system by applying a diamond like carbon film to the wafer chuck in order to reduce friction. Other process variables that are unique to NIL and that can be considered as process tunable variables include imprint force and tip/tilt of the imprint head relative to the wafer substrate during exposure. These variables can be used to modulate and control the overlay errors near the imprint field edges and provide good overlay control. An additional method to improve overlay is Drop Pattern Compensation (DPC). DPC is used to create a resist drop pattern designed to remove non-flatness originating either from the wafer/wafer chuck or pattern topography, so as to minimize mask bending. Finally, it is also possible to correct distortion signatures on wafer by fabricating a “refined” mask which takes into account the distortion signature. The purpose of this paper is to describe the application of the improvements discussed above to realize a mix and match overlay of less than 3nm.

A sampling inspection using non-patterned wafer and photomask has been dedicated to classical inspection technology for monitoring trend of particle variation at mass production. Total cost of sampling inspection method decreases the overall equipment effectiveness in mass production because equipment usage time and raw material cost. Nevertheless, customer mass production yield requirements for high-grade photomask and extreme ultraviolet photomask by sampling inspection method will be difficult to satisfy. To overcome sampling inspection's low reliability, this paper intended to describe an application of real-time monitoring for mass production equipment and verification of evaluated case by case. Optimization of real-time monitoring setup requires that sensor's install location with a considered mean free path in vacuum chamber, avoid to particle and bubble in chemical tube line and filter, and digital image process comparing method for nozzle height and parts location. An emergence of many by-products in a vacuum chamber, chemical tube line, and chemical filter is an unexpected danger. Application of real-time monitoring contributes to observing particles that in vacuum chamber using plasma, in tube line using chemical and chemical filters, sensing of mechanical drift and twist are also applicable with real-time detection technology using high-resolution cameras. As mentioned above, saved real-time big data can use proactive control to improve yield loss and cost of ownership. The specific suggestion about using real-time monitoring method is as follows 1. Detected increase rapidly trend of particle. Stop a process and start a particle removing recipe. 2. Observed particle rising. Stop process and start a cure recipe, and change other best path. 3. Sensed abnormal action. Stop process and do preventive maintenance after all substrate out. Both real-time monitoring data and yield data can analyze correlations that improve to become low cost of ownership by figuring out a root cause and drop in quality. A photomask industry is small compare to semiconductor industries, less than 1 percent by number of tools and production capacity. A photomask industry hard to make a big data due to little seed or small volume data. This paper shows how to make big data using real-time monitoring technology and how to defend a yield loss by unexpected situation at photomask tools.

Comprehensive disposition of reticle defects is critical for process and yield control. Misjudging a real defect on mask may not only reduce its lithography process window but also kill thousands of wafers causing unbearable economic loss. With the development of OPC and ILT technology, manual judgement of reticle defects has become more challenging. The situation is even worse in advanced logic fab, especially for foundry, where pattern complexity and diversity vary from worldwide fabless upstream firms. Working with KLA, USCXM adopted and reported ADC (Automated Defect Classification) and DPM (Defect Progressing Monitor) solutions to avoid defect misclassification and to alarm defects degrading [1]. These solutions run smoothly and shorten the cycle time in daily routine production. However, both functions cannot well predict the defect printability on wafer when there are questionable mask defects. Usually, the problematic mask has to be sent back to mask shop, where an AIMSTM tool evaluates printing risk, leading to a very time-consuming verification cycle. Thus, a cutting-edge technology called LPR (Lithography Printability Review) has been fully qualified and applied in a logic foundry for the first time. Using the optical mask inspection images, with LPR, the aerial image CD error can be accurately modeled thereby eliminating possibility of any related yield loss, while also dramatically shortening the cycle time for verifying such defects. In this paper, we introduce a series of strict qualification processes for LPR adoption. The qualification flow involves both PDM (Programmed Defect Mask) and production mask with respective purpose. The PDM verification covers various defect types while the production mask provides abundant pattern geometry. The LPR vs AIMSTM simulation efficiency is over 90% without missing one killer defect. Furthermore, LPR operates as part of an integrated solution with ADC and DPM. Typical production cases are also presented in this paper to demonstrate its invaluable contribution to avoiding yield loss. The RA (Reticle Analyzer) product including ADC, DPM and LPR, is the only mature solution, and is now deployed in full volume mask manufacturing production, driving intelligent automation with zero misoperation, shortened cycle time, and increased fab productivity.

TN5nm HVM where EUVL was implemented on started in the middle of 2020, but EUV mask pattern inspection is still not ready in terms of fully satisfying customers' requirements. There are three tool candidates; optical, actinic, and e-beam inspection. The E-beam tools have high resolution and sensitivity, but have a low throughput. To better address market requirements, NuFlare has optimized its multi e-beam optics to inspect EUV masks, and apply D2DB method into the e-beam tool to achieve the throughput target. We describe the latest results of verification about main technologies to achieve throughput required for EUV mask inspection.

The two standard reticle defect inspection methods are die-to-die and die-to-database. The die-to-die inspection method compares images from the two dice on the same reticle to identify any defect. However, the die-to-database inspection method compares images from the reticle with the design data (CAD). The previous year, we built an SEM-based VSB writer classification system for die-to-die inspection that used state-of-the-art deep learning models to identify errors such as shape, position, and dose [1]. Using the deep neural networks and DL-based SEM digital twins [2], we showed better accuracy than the average human expert in classifying SEM-based defects. However, a limitation remained that the DL model wasn’t aware of chrome and glass regions, just from the input SEM. This information is helpful to make better decisions in classifying some typical errors achieving higher accuracy. In the current paper, we improve the accuracy of the existing classifier by enhancing the underlying deep learning model and supplementing it with the recognition of chrome and glass (exposed and unexposed) regions further. We make it possible with yet another DL-based SEM2CAD digital twin to automatically identify exposed/unexposed areas from the SEM and augment manual input by the expert to it. We feed this new information into the SEM classifier that currently takes a reference and error SEM image for more accurate results. In addition, we also built an SEM-based defect classification system for the die-to-database inspection to categorize various types of VSB mask writer defects, which requires defect SEM images and the reference CAD. Using several deep neural network models and digital twins, in this paper, we provide a production-grade system for the VSB writer’s SEM-based defect classification that works for both die-to-die and die-to-database inspection methods.

The mask CD mean-to-target (MTT) has been widely adopted as one of the key metrics for the mask quality control. As more aggressive optical proximity correction (OPC) is applied to push the resolution limit, traditional CDSEM measurement-based metrology is not sufficient to characterize mask CD MTT, especially for complicated 2D patterns. In this paper, we present the method of using SEM image contours for the characterization of mask CD MTT. The full flow includes contour extraction from mask SEM images, contour-to-contour alignment, contour averaging and edge placement error (EPE) measurement of mask image contour against the target. The OPC Verify engine is employed to give fast EPE check at closely packed sampling sites along the target. We apply this method to evaluate mask CD MTT for the hotspot patterns from two masks. The generated mask CD MTT distribution histograms and color maps demonstrate a good correlation with the wafer defect counts.

As mass production of advanced semiconductors using EUV lithography has begun, there was a high demand for various EUV actinic tools by mask shops, blank makers, and material suppliers. For example, EUV microscope would need for EUV mask defect review, EUV phase measurement tool would need for EUV PSM, and EUV transmittance, reflectance measurement tool would require EUV pellicle. Moreover, EUV test exposure tool is also required to develop EUV resist materials and process equipment. These are currently being developed as stand-alone tools but it is not easy to introduce all the individual tools due to the high cost of ownership, large fab space and low utilization at the beginning stage. In order to solve these difficulties of the industry, we have developed an equipment that can implement multiple solutions within the same system. Depending on the user's specific purpose, the various functions can be freely combined in a LEGO style with cost effective way to maximize equipment utilization and reduce the fab space. In this paper, we will discuss how this concept is realized for EUV mask and EUV material industry.

Alternatives to Ta-based absorbers are being considered for next generation lithography nodes to reduce 3D mask effects and to improve image modulation through phase interference. Low complex refractive index (n – ik) materials can provide phase shifting behavior at thicknesses less than those needed for conventional absorbers, essentially acting as attenuated phase shift mask (attPSM) films. Identifying attPSM absorber thickness and consequent phase requires determining optimum phase shift mask reflectance. Imaging with absorbers at high reflectance show better imaging performance. The absorber thickness is determined where the interference effects lead to high absorber reflectivity. Low refractive index (n) materials are therefore desired as candidate attPSM absorbers. Low – n material combinations identified using Wiener bounds and Effective media approximation (EMA) modelling are optimized for NILS and MEEF using absorber reflectivity on line-space and contact-holes patterns. Absorber candidates at optimum thickness for contact holes are compared with conventional Ta-based absorber using reflected nearfield intensity imaging.

ASML’s extreme ultraviolet (EUV) lithography machines have found widescale adoption in 5 and 3 nm logic nodes and leading-edge DRAM nodes. The tool operates by generating 13.5nm light from a tin plasma source, which is then directed through multiple optics and reflected off the EUV photomask and down to the wafer surface. In the EUV tool, tin and other contaminants are generated, and because no protective pellicle is used in EUV photo-lithography, any contaminate on the EUV photomask will become a defect on the wafer. EUV photomasks therefore need frequent cleaning compared to a traditional photolithography process, which would employ a protective pellicle. Herein, we report on the development of an EUV photomask cleaning solution that was designed to remove Sn, SnO2, and other contaminates from a mask surface without damaging the mask’s tantalum absorber and ruthenium capping layers. Our mask cleaning solution extends photomask lifetime and can improve operational performance and quality control.

The global photomask business faces both substantial opportunities and challenges in the coming decade. The semiconductor business is forecasted to grow at 9.9% CAGR from 2020 - 20301 which will drive growth in the photomask market. Coincident with this predicted growth, the photomask industry is facing significant equipment obsolescence issues that will require many of the legacy tools that support <=28nm technology to be renewed or retired and replaced in this timeframe. This presentation will review the challenges that these trends present to the photomask and semiconductor market. We will review the lithography system growth estimates from our previously published paper and extend that analysis to all photomask equipment. The business implications of this environment are critical to both the semiconductor and photomask supply chain.

This is a management overview of our experience in how to apply deep learning for semiconductor manufacturing projects. Deep learning is a transformative software technique, largely enabled by "useful waste" that is now possible with Peta-FLOPS level computing available with GPUs. DL has achieved many "firsts" that tens of years of effort by the best computer scientists could not achieve before. But production deployment of DL projects in semiconductor manufacturing including mask manufacturing has been difficult to attain. There has been a number of successes reported at this conference and elsewhere, but a common theme in deep learning papers in our field is the lack of availability of a large amount of data. Deep learning needs lots of data to train with because it is a pattern matching technique. It needs to see enough patterns to recognize all the situations a production mask might contain. In addition, deep learning programmers improve the network by adding data to the training data set to disambiguate where the network is confused. it is essential to be able to add any kind of data at will quickly to improve the success rate of a deep learning network. In semiconductor manufacturing, real data is hard to come by because of confidentiality requirements and also because of the expense of generating masks and wafers. A key ingredient to the general formula for deep learning success in semiconductor manufacturing is to use digital twins to generate data at will. It is time consuming, resource intensive, and expensive to set up. But it is necessary to create a deep learning capability that can be deployed in production. We will conclude with an overview of the other necessary conditions for deep learning success.

Semiconductor manufacturing equipment must maintain high productivity and provide high-yield processing and Canon has developing high-reliability exposure tools that have demonstrated high-uptime and performance stability in production. As global emergency epidemic restrictions limit the travel of expert engineers, customer service becomes more challenging and alternative methods of support are being developed to help customers meet their production roadmaps. To help control performance, lithography tools have sophisticated logging systems that can monitor every movement in the tool and we studied a novel Artificial Intelligence system that utilizes big logging data to help improve exposure tool uptime, productivity and performance related to yield. One goal of our study is to minimize exposure tool downtime by monitoring and reacting to tool status. For this purpose we are applying machine learning to develop abnormality detection or prediction models with automated recovery procedures for each abnormality. We will report on Auto-Fault-Tree-Analysis (FTA) models being constructed to evaluate large volumes of design and trouble information to help minimize downtime. Another study goal is to improve lithography tool performance by monitoring and reacting to factors including overlay accuracy and CD uniformity that can strongly affect device yield. Outputs of this analysis include simulation and optimization of equipment performance, and virtual metrology. This paper reports on the system we are developing to help increase the uptime, productivity and imaging performance of Canon semiconductor lithography tools. The system is designed to monitor the operating state of lithography tools and apply automated recovery and optimization actions identified through machine learning.

With the VLSI technology shrinking to 7nm and beyond, the Redundant Local Loop (RLL), also known as via pillar, becomes a promising candidate of redundant via insertion due to its compatibility with the unidirectional layout style. Existing RLL insertion approaches only leverage rule-based heuristics for manufacturing constraints, which can no longer obtain a large enough Process Window (PW) in advanced technology nodes. It is imperative to develop new techniques to optimize lithography process window while inserting RLL to achieve a good yield. In this paper, we propose a machine learning-based litho-aware RLL insertion framework. Conventional lithography simulation requires tremendous computational resources to evaluate the lithography quality accurately, which is not feasible for process window exploration. We formulate the lithography simulation as a regression task and develop a customized Conventional Neural Network (CNN) architecture to predict the Depth of Focus (DOF), a standard metric for evaluating process window. We propose a complete ow for litho-aware RLL insertion based on the CNN model for process window evaluation. The commercial lithography simulator evaluates the effectiveness of the proposed framework. Experimental results demonstrate that our lithography model can predict the DOF with high accuracy and generalize well on unseen patterns while achieving orders of magnitude speedup compared to conventional lithography simulation. Our litho-aware RLL insertion framework can effectively improve the lithography process window with comparable runtime and insertion rate compared to the state-of-the-art method.

Prediction intervals which describe the reliability of the predictive performance of machine learning models are important to guide decision making and to improve trust in deep learning and other forms of machine learning and artificial intelligence. Conformal prediction is a relatively recent, increasingly popular, rigorously proven and simple methodology to address this need for both classification and regression problems, and it does not use distributional assumptions like Gaussianity or the Bayesian framework; one new variant combines it with another technique to generate prediction intervals known as quantile regression. We will illustrate the strengths and limitations of different conformal prediction procedures for a regression problem involving line edge roughness (LER) estimation; LER affects semiconductor device performance and the yield of the manufacturing process. Low-dose images from the scanning electron microscope (SEM) are often used for roughness measurements because of relatively small acquisition times and resist shrinkage, but such images are corrupted by noise, blur, edge effects and other instrument errors. We consider prediction intervals for the deep convolutional neural network EDGENet, which was trained on a large dataset of simulated SEM images and directly estimates the edge positions from a SEM rough line image containing an unknown level of Poisson noise.

Toward logic 3nm and beyond, mask 3D effect and stochastic failure are main issues in EUV lithography. Alternative absorber material is required to mitigate those issues. EUV attenuated phase shift type absorber with low n value enables to achieve higher NILS due to phase cancellation effect. And much better imaging performance can be expected. We developed candidate attenuated phase shift type absorbers and evaluated these blank and mask properties. In this paper, we will report on those blank and mask properties for the candidate phase shift type absorbers.

Extreme ultraviolet lithography (EUVL) is a main lithographic technology for cutting-edge node. Also, ArF lithography will continue to be used in conjunction with EUVL for advanced node production. Critical ArF imaging layers require photomasks with tight resolution and "rigid CD and Positional accuracy". Those specifications are tightening due to the narrow process window. The etching process for phase-shifter has to precisely controlled to achieve the targets. . Various pattern density in PSM (Phase-Shifter Mask) shows phase angle variation due to the digging of the Quartz substrate(QZ). In the high transmittance PSM, the error has larger impact on the lithography due to strong phase shift effects. To prevent phase shift error from the target phase angle, QZ etching stop film is considered. It is possible to obtain a high etching selectivity compared with QZ and to apply an aggressive dry etching condition. In order to control in-plane phase angle distribution due to QZ etching during PSM etching, we proposed a novel high transmission etching stop film for ArF lasers.

As semiconductor technology became more integrated, the numerical aperture (NA) of extreme ultraviolet (EUV) exposure technology has increased from 0.33 to 0.55 to realize finer patterning. High NA EUVL aims to enable 8 nm half pitch resolution. As the NA increases and a smaller linewidth needs to be implemented, the mask 3D effects on patterning will become more severe. For mass production of EUV, it is essential to find an optimal absorber structure to alleviate serious problems such as mask 3D effects and shadowing effects. Among the various factors constituting the EUV photomask, phase shift and reflectance of the absorber are the most important factors that determine the image quality. Through computational simulation, the optimal structure was selected in consideration of phase shift and reflectance, and imaging performance and process latitude were calculated.

In this work, we present using curvature-based pre-bias to reduce the number of iterations required to reach convergence in curvilinear mask correction. The pre-bias is generated with a simple curvature, which extracts the input contour curvature. Although the curvature-aware model is simple, the created pre-bias is close to the converged MPC correction output. Therefore, fewer iterations with the full model are needed to reach convergence. In the meantime, since the curvature model is simple and does not require high compute resources, the total runtime of curvilinear MPC can be reduced.

Photomask technology has advanced substantially with the introduction of Multi Beam Mask Writers (MBMW), which achieve acceptable mask write times even with very complex mask patterns. In addition, Inverse Lithography Technology (ILT) and similar techniques generating complex curvilinear mask shapes, have been shown to improve wafer lithography process window significantly. Both of those factors and the increasing power of computing resources increase the use of such mask shapes for DUV and EUV lithography. However, when processing complex curvilinear mask shapes in the mask data preparation flow, file size and data processing time, for example in Mask Process Correction (MPC), become a bottleneck[4]. In order to reduce the impact of curvilinear mask shapes on overall data preparation time, this work introduces a Curvature Based Fracturing (CBF) method, feasible for reducing file size and data processing time. CBF fragments curvilinear shapes based on their curvature. This method generates short segments along the shape edges where curvature is large and longer segments where curvature is small. Fragmenting curvilinear shapes this way is important for MPC to work well and achieve small Edge-Placement-Errors (EPE) even at high curvature regions. In addition, the method only generates small fragments where they are required for good MPC convergence but relaxes segment length at low curvature areas. That way, in many cases the result is a reduction in fragment count per shape and therefore a reduction in MPC runtime. The reduced fragment count also translates directly into smaller file sizes. In order to optimize the entire mask data preparation flow, CBF is applied during curvilinear OPC or ILT, so that all following data processing steps, in particular MPC, can benefit from an optimized fragmentation.

The patterning requirements of next generation lithographic processes and the desire to keep manufacturing costs down have pushed the lithographers to explore the advantages of the curvilinear masks. Multiple studies backed by the experimental results have demonstrated the lithographic advantage of the curvilinear (CL) photomasks over the rectilinear (RL) approximations by showing improved MEEF, depth of focus (DoF) and common DoF (CDoF) for variety of patterns on the same mask, ILS and, as a result, process window (PW) of the CL masks over its close RL siblings [1,2]. Manufacturability of the CL masks has been limited due to the architecture of the Variable Shaped Beam (VSB) writers, which made it prohibitive from both mask data preparation (MDP) and mask writing perspective. The availability of Multi Beam Mask Writers (MBMW) has removed these roadblocks and brought introduction of the curvilinear masks much closer to reality. The development of novel approaches for MDP and Mask Proximity Correction (MPC) as it is demonstrated by Bork et al in [3] brought further advances in availability of the CL masks for high volume manufacturing (HVM). Traditionally the Inverse Lithography Technology (ILT) has offered the most potential to achieve significant lithographic advantage over RL masks but has suffered from very long data preparation runtimes which presented an additional hurdle for broad deployment in manufacturing. While various speed up options such as machine learning-based acceleration, and GPU processing [4,5] are being explored, the full chip ILT run time still represents significant challenge in the HVM world. This paper will concentrate on two OPC approaches that allow CL mask generation without run time penalties associated with full chip ILT processing. The first is based on a hybrid methodology that allows for generation of the CL mask shapes by using fast ILT-based algorithms for SRAF generation while the main features are controlled to allow for full chip processing within the reasonable time. The second approach is more appropriate for the memory applications where patterns are highly repetitive. Due to high level of repetition, it is acceptable to use full ILT correction carried over a small area of the chip and to utilize pattern matching (PM) methodologies to propagate both SRAFs and OPC-corrected features from unique to non-unique pattern placements. Such a methodology allows for the full ILT advantages in the highly critical memory array areas.

It is known that Inverse Lithography Technology (ILT) is the key to enable the semiconductor industry to move forward beyond 3nm node driven by design density and process window improvements. The test patterns used for recipe development play a critical role in achieving optimized ILT masks in terms of mask-friendliness, OPC convergence or multi-structure common focus range. The traditional way of test pattern selection is usually a clip-level manual search by considering of design rules, which inevitably may cause lack of critical design representations. In this paper, we introduce Mentor Graphics’ Calibre SONR, a Machine Learning (ML) method to implement design layouts clustering and automatic pattern selections for ILT recipe tuning on a full-chip level. It is shown that SONR enables comprehensive coverage of the layout complicity and hence improves the robustness in the real full chip run. In addition, it improves productivity for recipe tuning without suffering any loss in the wafer performance by simulation in terms of EPE convergence, PVBand and common DOF.

Curvilinear masks are coming. With multi-beam mask writers in production, leading edge mask shops now are able to write curvilinear masks in the same mask write times as any Manhattan masks [1, 2]. As Samsung and Luminescent showed long ago [3], curvilinear mask shapes produce the best wafer process windows. For 193i masks, curvilinear SRAFs have been demonstrated in reasonable time even with the traditional variable-shaped beam (VSB) writers with good wafer results. [4] It is widely anticipated [5] by the luminaries of the industry that curvilinear ILT shapes either are already or will be used at least for hotspots in some leading-edge layers before 2023 for both 193i and EUV masks. ILT solutions have previously focused on Manhattanizing the output to make it suitable for VSB writing, instead of using curvilinear or at least piecewise linear polygons to be specified for the desired mask shapes. With multi-beam mask writing being widely available for the leading-edge nodes, manufacturing curvilinear ILT shapes is now possible. But what about the rest of the mask making infrastructure? This paper introduces the session on curvilinear masks by surveying the constraints and considerations around introducing curvilinear masks to mask manufacturing. The other papers of the session will address the data volume and computational complexity issues with contour geometry in polygon-based processing of data. We take note of pixel-based manipulation of data being constant in run-time performance regardless of shape, whereas manipulation of contour geometry scales in run time based on vertex or edge count. This paper also reiterates that curvilinear MRC can be significantly less complex [6]. Other aspects of the mask infrastructure including metrology, inspection and repair will be discussed. The paper concludes with a brief discussion about curvilinear wafer targets, or curvilinear designs [7]. It suggests that allowing certain curvilinear targets can make designs more manufacturable and more resilient to manufacturing variation on the wafer, while decreasing power consumption, increasing clock speeds, and making designs smaller.

As the semiconductor manufacturing industry moves towards advanced nodes with increasingly complex designs, users may experience an enormous increase in runtimes of mask data processing steps. This is true for Mask Process Correction (MPC)/Mask Data Preparation (MDP or fracture). Conventionally, in a high-volume production flow, the steps execute sequentially; a subsequent step waits for the preceding step to complete. In cases where the entire design does not need to be processed for the next step to begin, users may pipeline the steps to reduce total turn-around time. For example, if MPC and fracture are executed on a design, fracture commences only once MPC is complete on the entire design. An integrated, pipelined flow subsumes the runtimes associated with downstream fracture processing to the maximum possible capability of the computing resources. The integration is achieved by using a task-based pipeline that produces and consumes data without intermediate file exchange. It allows for in-memory processing which eliminates intermediate disk I/O operations, thereby making room for optimizations. This paper presents a comprehensive study of an integrated Curvilinear MPC (CLMPC) + IMS Multibeam Fracture (MBW) flow and demonstrates the runtime benefit with minimal impact on accuracy and file size over a conventional sequential flow [1,2]. We explore and demonstrate the runtime advantage from pipelining on a set of representative curvilinear/rectilinear designs by comparing sequential vs. pipelined execution of curvilinear MPC (CLMPC) and curvilinear fracture. A set of 11 designs are investigated to illustrate a substantial reduction in runtime while maintaining high-quality results.

The multi-beam mask writer MBM-2000 is released for the 3 nm technology node. It is designed to expose EUV blanks and leading edge photomasks at high throughput with beamlets of total current 1.6 uA. The curve data format supported by MBF 2.0 enables full-mask writing of curvilinear patterns by reducing data volume and computation cost of rasterizing. To maximize the performance of multi-beam writing, MBM-2000 is equipped with pixel level dose correction (PLDC) which improves pattern fidelity and patterning resolution. In this paper, we have reported and discussed the writing results of MBM-2000.

In this paper, we will report the modeling of behaviors of low-energy secondary electrons (LSEs) in a charge effect correction system (CEC), which compensates image placement errors predicted by writing layout data, on mask blanks with and without a charge dissipation layer (CDL). For the demand of low line edge roughness and high critical dimension uniformity, the more dose-sensitivity of resist is lowered, the more a contribution of LSE is made in charge effect, because the number of primary electrons generating LSEs also increases. In such a situation of advanced lithography, we have tackled challenges of CEC system in terms of blanks with and without CDL. On blanks without CDL, CEC needs to predict the complicated charge distribution including that of LSE which is affected by electromagnetic field of optical system and already-existing resist surface charge. On blanks with CDL, CEC needs to predict LSE charge diffusing on the resist surface. In order to address these challenges, NuFlare Technology (NFT) has developed models of CEC on blanks with and without CDL. In order to verify these models, we evaluated the surface charge effect in the writing on blanks with resist of 100 μC/cm² dose-sensitivity on electron beam mask writer EBM-9000/9500. Furthermore, as another solution besides CEC and CDL, NFT has developed a charge effect reduction (CER) system which prevents LSEs from re-entering into the resist surface. We have verified CER by comparing the experimental results between EBM9500 and EBM9500PLUS, which is the NFT’s latest variable-shaped beam with CER system.

It is possible to plan mass production by multiple patterning technology of 193 immersion scanner at 7nm technology node. Source mask optimization (SMO) is essential for critical layers, which is a long-running job. It is practicable to explore the methodology to shorten the iterative process of SMO. The different initial sources for SMO of freeform source have little impact on runtime, final source shape and process window (PW) because the algorithm tries to avoid getting stuck in a local optimal solution. However, the number of patterns involved in SMO has obvious positive correlation with runtime. Our paper put forward a novel acceleration workflow for reducing the number of candidates in SMO to reduce the total runtime, and get qualified overlapped PW and improve optimization efficiency. The proposed methodology is demonstrated on leading logic technology node. The results show the feasibility to apply the method for runtime decrease and performance improvement.

Model-based Mask Process Correction (MPC) is an indispensable data processing step for producing masks for advanced wafer production nodes. Typically, calibration of an MPC model may require several thousands SEM measurements. However, due to metrology tool-time constraints, there is an increasing requirement to minimize the number of measurements for building an MPC model, without impacting the model quality significantly. This work presents the development of a down-sampling approach using a combination of sensitivity analysis and clustering to reduce a larger set of diverse measurement locations to a smaller subset according to the metrology budget of photomask engineers.

The demand for semiconductors has outstripped WW capacity over the past year as consumer products become smarter & more connected. A significant portion of this demand requires feature rich technologies based on legacy technology nodes, which is driving the industry to explore novel approaches to supporting semiconductor wafers & mask needs. In this talk we will explore the megatrends driving the current Renaissance of Computing, and provide a roadmap for the innovation and investment needed from throughout the global semiconductor ecosystem to support the insatiable thirst for computing outside of just the single-nm technologies.

The semiconductor industry is enjoying the “Semiconductor super cycle” catalyzed by the pandemic. In addition, the variety of semiconductor chips are increasing driven by electronification of everything resulting the demand for laser based mask writers are increasing due to lower exposure cost per mask. However, many laser mask writers in operation today are getting old. As a response to the growing demand Mycronic introduced SLX series, a new generation cost-efficient laser mask writer and the superiority of the system is demonstrated by sharing recent evaluation data with two different laser sources.

The semiconductor industry's migration to EUV for the leading-edge nodes provides significant advantages and poses new challenges for the mask writers. The mask quality requirements for the leading-edge process technology call for ILT (Inverse Lithography Technology) and curvilinear patterns to improve the attainable resolution on wafers and extend the process windows. While single-beam writers cannot handle writing arbitrary curvilinear patterns without throughput penalty, multi-beam mask writers (MBMW) can easily print such patterns without degrading their throughput5,6. However, the transition to the curvilinear mask ILT significantly increases the layout complexity, posing a challenge for data transfer and storage systems as the file sizes increase substantially1. Traditionally, multi-beam-writers have been using a mask data input format derived from OASIS P44, namely OASIS.MBW 1.0/1.2, leading to multi-terabyte layouts. We present OASIS.MBW 2.1 as an efficient data format for curvilinear ILT masks. OASIS.MBW 2.1 enables a dramatic reduction in file size and vertex-density and preserves the qualities of OASIS.MBW 1.1/1.2 as well as quick and easy adaptability for the end-users. This is achieved by allowing the use of the OASIS P39 POLYGON RECORD in addition to the other OASIS.MBW 1.x properties, creating a hybrid format between OASIS P39 and P44 that provides a minimal file size comparable to OASIS P39 for pre- and post-fracture data operations at the fabs. Consequently, OASIS.MBW 2.1 provides the optimal combination of minimized file size and minimized required CPU time, thus enabling fast processing as well as a fast transfer for all applications.

In this paper, we present a simulation analysis of the impact of reticle pattern roughness and its impact on future mask design. To that end, we examine the role of reticle roughness on EPE, ILS, and the resulting process window for a series of 2D N3 and N2 features. The nominal masks studied were the result of four different flavors of OPC: Manhattan and freeform, with and without SRAFs, with the stated goal of uncovering how reticle roughness may impact the choice of reticle design and fabrication. Fourteen different patterns were simulated for each OPC mask design, with 105 -106 features for each pattern. The selected patterns comprise a range of CDs from 20 to 60 nm, at pitches in the range of 36 to 135 nm. Reticle variability was injected using a Monte Carlo approach, in which the injected roughness is parameterized by correlation length and amplitude derived empirically from a mask available to us. Carrying out simulations in this way allows us to measure variability distributions and their low-probability impacts at approximately a 5-sigma level. Our preliminary results suggest that both SRAFs and freeform mask design, particularly in concert, offer improved robustness to reticle variability.

As EUV is adopted by more companies, the insertion strategy and timing begin to drive new mask requirements. Traditional lithography extensions employed for DUV may now appear with EUV, from ILT to PSM to aggressive use of pellicles. Looking beyond was has been successful with EUV HVM and towards what we anticipate the requirements will be for the future, this panel will provide a suppliers perspective on where they believe the mask infrastructure stands to support low-k1 imaging for 33NA today and the initial path to support 55NA tomorrow.