This PDF file contains the front matter associated with SPIE Proceedings Volume 11325, including the Title Page, Copyright information, Table of Contents, Author and Conference Committee lists

As scaling becomes more challenging, new approaches to transistor design, new materials, and new devices are all being explored. Advanced transistor designs such as vertically stacked nanowire and nanosheet FETs (NW/NS FETs) provide a pathway to sub-10 nm devices. Ferroelectric High κ enables extension of FinFET and NW/NS FETs as well as providing a potential dielectric for memristive devices, including RRAM and ferroelectric tunnel junctions. NW/NS FETs provide a significant challenge for both processing and process control due to the geometries associated with their 3D structure. Increasing computational power will ultimately require more than scaling, however. Neuromorphic (brain like) computing and non-Von Neumann computing architectures are now being explored as alternative options for increasing computation capability. To develop efficient neuromorphic and non-Von Neumann hardware, new devices and materials integration strategies are required. This paper provides an overview of advanced NW/NS transistors and new memristor devices and materials and their characterization and metrology.

Galileo Galilei once quoted: “Measure what is measurable, and make measurable what is not so”. In silicon manufacturing R&D phase, it often happens that engineers would like to access some parameter values that are not easy, even impossible to measure. When looking at a CDSEM image, the parameters of interest seem easy to extract but in practice getting access to them in a robust and reliable way is not always simple. Developing a contour-based metrology tool coupling robust contour extraction with a comprehensive contour metrology environment could help to bridge this gap. In previous works, it has been shown that SEM images contain significant amounts of information that can be extracted and analyzed using efficient contour extraction and analysis toolboxes [1, 2]. Also, the concept of implementing remote contour-based metrology has been introduced. The present work continues to unveil what can be achieved with such solutions. For that, the example of implant layers’ process assumption will be explored. During this process step, counter doping problems can occur for example when the distance between layers deviates from nominal. Therefore, it is crucial for design rule control to measure some critical dimensions such as minimum distance between layers, corner rounding, slope, etc. However, given the characteristics of the different structures in the images, which may come from different layers and/or processes steps, the measurements are not straightforward to extract with standard CDSEM metrology algorithms. Moreover, recipes are complex to setup, measurements by themselves are not very stable, and usually an indirect determination of the key figure is performed. In this paper, we will show that multilayer contour-based metrology, mixing image contour and GDS layout, allows to overcome the previously mentioned difficulties, as well as to generate measurements that are not possible to be performed by using standard algorithms.

In leading edge patterning processes, overlay is now entangled with CD including OPC residuals and stochastics. This combined effect is a serious challenge for continued shrink and can be characterized with an Edge Placement Error (EPE) budget containing multi-domain components: global and local CD, local placement errors, overlay errors, etch biases and OPC. EPE defines process capability and ultimately relates to device yield. Understanding the EPE budget leads to efficient ways to monitor process capability and optimize it using EPE based process control applications. We examine a critical EPE use case on a leading edge DRAM node. We start by constructing and verifying the EPE Budget via densely sampled on-product in-device local, global CD and Overlay metrology after the etch process step. EPE budget contributors are ranked according to their impact to overall EPE performance and later with simulated EPE performance improvements per component. A cost/benefit analysis is shown to help choose the most HVM-friendly solutions.

In this paper we present a powerful virtual metrology system to aid in-fab product lot level dispositioning and yield learning. CD and overlay measurement data of different layers are modeled across the wafers and mapped to dense dose, focus, and overlay grids. These are input processing conditions for design-specific computational lithography to predict on full-wafer, full-chip inter-layer overlap area and critical edge-to-edge distances, which are thereafter used to predict electrical failure. The system is composed of an off-line inter-layer hotspot database and an on-line real time dispositioning module. It supports complex multi-patterning stacks with or without self-aligned processes. Example runs have been conducted for 14 nm node metal and via layers, using both FEM-like and typical nominal production wafer data, and the results are as expected from lithographical point of view. Comparing with traditional wafer dispositioning based on static overlay spec and CD spec, our system outputs wafer map stacked with failed dies locations, worst case hotspots contours, root cause analysis, list of worst hotspots and worst dies for inspection, and help litho engineer make an educated decision on wafer dispositioning. This will help fab optimize CD – Overlay process window, improve yield ramp, reduce wafer rework rate, and hence reduce cost, and shorten turn-around-time. The system’s computation is fast and inline real time wafer dispositioning aided by computational lithography is made possible by the system.

Optical overlay metrology has been used for years as the baseline for overlay control, measuring an optical target in the scribe line with optimized design to best match the on-product overlay. However, matching the optical target overlay measurements to the real on-product overlay becomes a serious challenge for most advanced technology nodes and forces the industry to develop different or complementary solutions. To identify and better quantify the different, well-known overlay accuracy detractors, in this work we have used optical and state-of-the-art electron beam technologies (eBeam) to measure on-product and on-optical target overlay errors of a wafer processed at imec using 5 nm technology node design rules and intentionally introduced overlay skews of +10 and -10 nm in x and y axis. The overlay errors as measured by the SEM eBeam system, equipped with elluminator™ technology which enables fast see through measurements of overlay which has been compared with (X-sectional) STEM-HAADF reference overlay metrology data. The on-product and optical target SEM overlay measurements show very similar wafer maps, in line with the applied overlay errors during the lithography exposure step. eBeam and TEM data show excellent correlation for the on-product overlay errors and the eBeam data also reveal a significant bias of ~ 6 nm between on-product and on-target overlay errors. From these results it can be concluded that manufacturing of advanced devices which require accurate OPO control, will need new metrology strategies that combine eBeam and optical or, eventually, use only eBeam technologies to guarantee effective overlay control with sufficient accuracy.

We present a different approach to laser-assisted atom probe tomography, where instead of using a near-UV laser for inducing a thermal transient, we use an extreme-ultraviolet coherent light source to trigger field ion emission at the tip's apex. The use of extreme-ultraviolet photons in atom probe tomography opens the potential for an athermalfield ionization pathway.

In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher, peripheral circuits may account for more than 50% of the overall chip area. On the contrast, the Xtacking^TM technology arranges array and logic parts on two different wafers, and connects the memory arrays to the logic circuit by metal VIAs (Vertical Interconnect Accesses) to achieve unprecedented high storage density as well as DRAM level I/O speed. As a consequence, it becomes increasingly significant to monitor metal VIAs depth before wafer bonding process as to ensure reliability of array-logic connections. Currently, AFM (Atom Force Microscopy) is the main stream method of VIA depth monitoring. Apparently, AFM wins the battle of precision, however the low throughput limited its usage in mass production. In order to accomplish the requirement of VLSI production, a WLI (White Light Interferometry) metrology is revisited and a novel neural network assisted method was developed to monitor VIA depth. Basically, there are two major limitations that keep WLI tools from wider use, transparent film impact and diffraction limitation. In this work, realization of neural network is illustrated and inline dishing measurement is achieved with high accuracy and precision.

In order to extract ever more performance from semiconductor devices on the same device area, the semiconductor industry is moving towards device structures with increasingly complex material combinations and 3D geometries. To ensure cost effective fabrication of next generation devices, metrology solutions are needed that tackle the specific challenges that come from these developments such as 3 dimensional imaging of structures and imaging of deeply buried structures under arbitrary, complex layers. Compared to existing metrology solutions for high end manufacturing, ultrasonic inspection techniques have advantages: they are unaffected by optically opaque layers, the acoustic wavelength (60nm @ 100GHz in SiO2) can be smaller than optical wavelengths and the measurement depth can be larger. However, traditional acoustic microscopy tops out at a few GHz due to manufacturing tolerances and the required liquid couplant. We propose to combine very high frequency ultrasound with scanning probe microscopy. By locating the transducer above the cantilever tip, it guides sound into the sample with a dry tip-sample contact. This allows for very high acoustic frequencies and a resolution of O(wavelength).

Semiconductor reliability in applications such as automotive is getting increased attention as design rules shrink to include 1Xnm, semiconductor content per vehicle continues to grow, applications become more critical and reliability requirements tighten. Current automotive requirements stipulate less than one defective part per million (DPPM). Approaches to address reliability include improving design, manufacturing and test. Process control in manufacturing is critical for reliability and includes continuous improvement for reducing process tool defectivity, excursion monitoring of process tools and product lines, golden or best performing tool methods [1], measurement system analysis (MSA) methods and screening. Inline defectivity is known to have an impact on both yield and reliability [2], and defects can impact reliability in one of two ways. Killer defects located in areas that are untested can result in so called Zero- Kilometer failures. In other cases, the same types of defects that cause yield loss can also cause latent reliability failures – the difference being size, location and density. Latent reliability defects become activated after test and can include defect types such as partial bridges, partial opens, and embedded particles. Current reliability engineering relies on outlier detection rules like parametric part average testing (P-PAT) [3], or geographic part average testing (G-PAT), both of which are derived from end-of-line screening data, which is based solely on electrical test data [4]. Inline Part Average Testing (I-PAT™) is enabled by multi-channel high-speed LED scanning inspection technology and offers an opportunity to apply fab data to reliability engineering. Defect inspection results are analyzed with machine learning (ML) to weigh the defectivity and create a die-level defectivity metric allowing the statistical identification of die which are a high reliability risk [5, 6]. Two case studies are described. The first case is a feasibility study based on historical fab defectivity data and includes a sample of ~250,000 die, with eight inline defect inspections per wafer, including four front end of line (FEOL) and four back end of line (BEOL), on a high sensitivity broadband inspection system [7, 8]. Each defect is assigned a weight based on its impact to various “ground truth” indicators. The combined impact of all defects in a given die stacked across all inspections is aggregated into a die-level metric. Plotting the die-level I-PAT metrics for all the die as a Pareto chart allows outliers to be identified using accepted statistical methods [9]. I-PAT metrics can then be correlated to electrical wafer sort (EWS) yield or fallout rate, specific wafer-sort bins, EWS parametric test performance and post burn-in electrical test. Of key importance is that wafer test was not used to train the I-PAT model, and therefore this method is an independent validation of latent reliability. The second case study focuses on production screening feasibility with multi-channel high-speed LED scanning, and addresses overkill, or the over inking of potentially good die based on inline defectivity, which is a critical challenge that must be overcome for production implementation [10]. Using inspection enabled by high speed LED scanning technology, die screening is a critical component of a comprehensive automotive Zero Defect program. Applications include early detection of fab excursions, feedback for continuous improvement of inline defectivity, feedforward to optimize electrical test methods and screening of die containing possible latent reliability defects. The I-PAT methodology can be used to enhance standard end-of-line outlier detection rules such as P-PAT [3], which is based solely on parametric testing.

In order to successfully develop and manufacture semiconductor chips, in-line inspection is extremely important. Optical and e-beam inspection are the two major defect inspection approaches used for semiconductor manufacturing. As critical dimensions continue to shrink with each new technology, killer defects are becoming smaller and smaller, reducing the effectiveness of optical inspection, which is resolution limited. A growing number of defect types are just not detectable with optical inspection. A partial solution is to adjust inspection parameters to run “hot”, but then the few defects of interest that are captured are buried in large numbers of nuisance defects. E-beam inspection (EBI), in addition to it’s unique role of detecting buried defects using voltage contrast (VC), is able to detect these smaller defects, but suffers from throughput constraints. This is because of EBI’s substantially smaller pixel size, which takes much longer to tile across the wafer surface, and a lower sampling frequency, because electrons aren’t as prevalent as photons. In R&D, this is not as much of a limitation, with EBI commonly deployed as a metric for many physical defects beyond optical inspection resolution as well as lithography related use cases such as process window qualification (PWQ) and EUV print check. However, EBI’s adoption during yield ramp and high volume manufacturing (HVM) is limited by these throughput constraints. To address this issue, HMI is developing multi-beam inspection (MBI) systems [1,2]. This latest paper covers three new topics. First, new milestones were achieved in the last year, including simultaneous operation of all beams and defect detection while in this mode, will be reviewed. Second, the importance of minimizing cross-talk between beamlets for MBI and the cross-talk performance of our latest tool is discussed. Finally, simulations of the anticipated throughput gains achievable for a range of physical and voltage contrast inspections for the current system are presented. These throughput gains vary widely and are useful in prioritizing certain inspections over others for practical use, as well as understanding the limiting factors for laggard inspections. Potentially some of these factors can be alleviated. Going forward, the plan is to continue to aggressively increase the number of beamlets while simultaneously further improving the resolution. Overall the HMI MBI program is on track with tool shipments to select customers in the very near future.

It has long been observed that certain pattern-failure phenomena manifest in an apparent random manner on wafer. Thus for a design pattern featuring multiple identical repeats in identical surrounding environments, some locations will at certain processing conditions result in failure, whereas identical patterns in direct proximity might not exhibit failure. Two examples of such are sub-resolution assist features (SRAF) printing and aspect-ratio dependent pattern collapse. SRAFs are of course designed to not print on the wafer, but it is observed that when SRAFs of a certain size or proximity to the main feature, at a specific dose and focus condition, are first observed to print on wafer, they do so in a random manner. The clearest demonstration of this is for a simple grating pattern with long running simple 1D lines interspersed with uniformly sized SRAF on the mask. Depending upon the resist system polarity, it is common to see splotches of partially printed SRAF dimples in the photoresist, or residual scum of photoresist appearing randomly along the length of the SRAM location. This behavior can be ascribed to the cumulative stochastic effects of exposure, PEB, and develop. A more complex phenomenon is pattern-collapse, which has been thoroughly researched and shown to be related to non-uniform capillary forces acting upon the newly developed photoresist pattern as well as the profile and bottom CD of those patterns. The result can again be an apparent randomness to the toppling of patterns which are nominally identical, especially when layout and process conditions are right at the onset of failure observation. Early experimental work in characterizing these two phenomena were often based on simple SEM image analysis, and demonstrated perhaps parts per thousand sensitivity. More sophisticated optical imaging techniques such as E-beam inspection can achieve perhaps parts per million sensitivity. With the advent of EUV lithography, there has been increased attention on stochastic effects, owing to the relatively few number of photons involved in the exposure of a single pattern. The result has been improved experimental methodologies for characterizing stochastic phenomena such as micropinching or micro-bridging, as well as improved simulation of these random behaviors. For 7 nm and below, the required sensitivity to protect yield is less than parts per billion. In this work, we report on the use of stochastic models to quantify the prediction of SRAF printing and pattern-collapse through the process window. Simple grating patterns with variable sized single SRAFs are used for characterization of the failure rate expressed in terms of percent of total SRAF mask layout area in the design block. For pattern collapse simulation, an array of photoresist posts are utilized, and as a proxy for pattern collapse, we use bottom CD area calculated from the randomized simulated contour. We use a range of different stochastic models to represent variable degrees of stochastic contribution and show the impact on main feature line edge roughness (LER) as well as pattern failure. Examples are shown for both EUV and 193i cases, and it is highlighted that stochastic failure is not relegated solely to EUV.

Appropriate solutions for post-lithographic defect management and process tool control are fundamental to ensure better chip quality and yield maintenance through the reduction of wafers at risk. The increasing demand in terms of wafer production capacity and sensitivity requirements from the automotive, MEMS and Internet of Things markets is leading advanced legacy semiconductor fabs to challenge their conventional after-develop-inspection (ADI) paradigm. In this work, we present a high throughput photolithography step monitoring scheme, developed by STMicroelectronics and KLA, employing an 8 Series patterned wafer defect inspection system for wafer frontside inspection and review. Namely, we demonstrate the capacity to capture die level defects together with full wafer excursions with a significant level of sensitivity, as well as a beneficial impact on yield improvement and lithography cell control. Moreover, we propose fast and reliable methods for monitoring the pattern shift and mask check, enabling increased wafer sampling and faster rework decisions. Lastly, we show well-engineered on-tool classification solutions at inspection runtime for each defect detected, allowing for improved control with high purity and fully automatic wafer disposition. Besides inline monitoring, we also show the capacity to check process tool performance, to detect lithography excursions faster and more effectively and have a better understanding of defectivity root causes. Moreover, to ensure complete control over the full lithography process, we show after-cleaning-inspection capabilities alongside conventional ADI. In this work, we present the beneficial aspects of the adopted strategy in terms of capacity improvement and critical defect detection in the production line.

At sub10nm nodes of Backend of Line (BEOL) using Extreme Ultraviolet Lithography (EUVL), the requirements of the process window of patterning are extremely tight for parameters such as Critical Dimension (CD) and Overlay which are traditionally managed for the semiconductor process. In addition to these parameters, because the latest BEOL pattern consists of a variety of space patterns, Edge Placement Error (EPE) of the tip feature of space pattern is the most critical to secure the contact between metal layer and contact or via layer. Because tip EPE is assumed to be affected by multiple factors such as pattern layout, the accuracy of Optical Proximity Correction (OPC), mask pattern, scanner tool conditions, and etching process conditions etc., the characterization of the patterning process and the establishing analysis method to find the root cause of EPE is of utmost importance before starting a high-volume manufacturing. However, general CDSEM metrology is only utilized to collect the limited number of data from several features which are predicted by simulation or searched by optical inspection tool. This implies the possibility of further process optimization is still covered inside of various 2D feature in BEOL. In this paper, we apply Die to Database(D2DB) EPE and show the necessity of massive data-based methodology to identify local process variability of 2D feature using e-beam metrology.

An auto e-beam tilt technology was used to measure bottom critical dimensions (CD) of High-Aspect Ratio (HAR) contact holes. Results show that traditional Scanning Electron Microscope (SEM) is not capable of catching bottom information, such as bending structures. A new method with hardware and software has been developed to first find the best angle to detect bottom electron signals with high acceleration voltage and then synthesize with multi-angle electron signals. By using this method, accurate bottom CD as well as the angle and direction of bended hole can be measured automatically. It is very effective for inline metrology of HAR 3D structure in semiconductor wafer processing.

We demonstrate the application of 3D tomography by FIB-SEM to analyze channel holes in 3D-NAND. We automatically analyze the 3D channel profiles for size, shape, and placement from the reconstructed full 3D volume. As the data contains thousands of holes, and each hole is sampled with a resolution of a few nanometer in 3D, this method provides a vast amount of data. We analyze individual holes as well as a full population of holes, from a solid statistical basis. Such information is beneficial in monitoring and controlling the etch process of the HAR channel holes in 3DNAND fabrication.

We applied deep learning techniques to improve the accuracy of 3D-profiling for high aspect ratio (HAR) holes. As deep learning requires big data for training, we developed a method for generating a large amount of BSE line-profiles by a numerical calculation in which the aperture angle and the aberration effects of the electron beam are considered. We then utilized these numerically calculated datasets to train the deep learning model to learn the mapping from the BSE line-profiles to the target cross-sectional profiles of the HAR holes. Two different one-dimensional neural network architectures: convolutional neural network (CNN) and multi-scale convolutional neural network (MS-CNN) were trained, and different loss functions were investigated to optimize the networks. The test results show that the MS-CNN model with a defined loss function of weighted mean square error (WMSE) provided higher accuracy than the others. The mean absolute percentage error (MAPE) distribution was narrow and the typical MAPE was 4% over 2810 items of test data. This model enables us to predict the cross-section of the HAR holes with different sidewall profiles more accurately than our previously proposed exponential model. These results demonstrate the effectiveness of the learning approach for improving the accuracy of 3D-profiling of the HAR features.

Tilted channel holes affect final yield significantly in High Aspect Ratio (HAR) 3D NAND memory wafer processing. An in-line measurement method is developed to use machine learning that utilizes the spectra from optical metrology to map Tilt-X and Tilt-Y. Reliable reference is provided by high voltage SEM. Results show that the correlation of optical and HV e-Beam measurements has R² more than 0.92. In addition, measurement throughput is improved tremendously by 40% from e-Beam to optical metrology. Combined with other optical metrology on the same platform (thickness, and Optical CD), this method is much efficient for in-line tilt measurement after channel hole etch process.

Background: Understanding line-edge and linewidth roughness in semiconductor patterning requires accurate, unbiased measurements where noise in the scanning electron microscope (SEM) image does not impact the measured roughness. This in turn requires edge detection algorithms with minimum sensitivity to SEM noise since unbiased roughness measurement does not allow the use of image filtering. Aim: There is a need to characterize and evaluate the noise sensitivity of edge detection algorithms used in SEM metrology. Approach: The noise floor of the roughness power spectral density will be used as a metric of noise sensitivity to compare three edge detection algorithms (derivative, threshold, and Fractilia Inverse Linescan Model (FILM)) using three sets of images (low-noise, mid-noise, and higher-noise cases). Results: The derivative edge detection algorithm performed poorly even on low-noise images. The threshold algorithm worked well only on the low-noise images. For all levels of noise in the images, the FILM algorithm performed well, and better than the threshold and derivative methods. Conclusions: An approach to unbiased roughness measurement that requires measurement of the noise floor without the use of image filtering requires an edge detection algorithm with inherently low noise sensitivity. The testing approach used here, comparing the noise floor level for different algorithms applied to the same images, is an effective way to evaluate the inherent noise sensitivity of edge detection algorithms.

Line edge roughness (LER) measurement of a nanoscale line pattern is a metrology challenge in the inspection of semiconductor devices. Conventional scanning electron microscopy (SEM), a classical LER measurement technique, is a top-view (2D) metrology and incapable of accurately measuring 3D structures. For LER measurements, SEM measurement generates a single line edge profile for the 3D sidewall roughness, although the line edge profile differs at each height in the 3D sidewall. In this study, we used atomic force microscopy (AFM) with the tip-tilting technique to measure the 3D sidewall roughness, as an LER reference metrology. An identical location of a line pattern measured by SEM and AFM was compared to evaluate the SEM’s performance. The line edge profile from the AFM measurement exhibited lower noise than that from SEM. The measured line edge profiles were analyzed using the power spectral density (PSD), height-height correlation function (HHCF), and autocorrelation function. The results demonstrate that the standard deviation (σ) and correlation length (ξ) are overestimated while the roughness exponent (α) is underestimated by SEM, considering the AFM results as reference values.

The different typical noise components observed in SEMs are important aspects to image quality and thus performance, yet models for adding realistic noise to model-generated images is an area where improvement of SEM simulation is important for addressing critical IC industry applications. Understanding how realistic factors affect the achieved noise distribution is important to achieve realistic noise characteristic fidelity in simulated images with respect to experimental images. Achieving realistic noise is important to enable simulations to help address many industry issues, such as minimizing line edge roughness measurement uncertainty. In this work, JMONSEL will be used to simulate various test structures with many repeats to observe how the noise distribution changes spatially, which will allow us to understand the noise dependencies on material and local geometry, which should give insight into the possible need for more detailed attention to how noise is applied to analytically-generated images.

EUV resist characterizations for line and space patterning as a function of dose and illumination conditions for varying pitches down to 28 nm are discussed. The unintentional resist line top loss (LTL) after development has been monitored and analyzed for all experimental conditions. Furthermore, line top roughness (LTR) is introduced, which is a 3 stochastic metric characterizing in-plane roughness related to the top of the resist lines. The main characterization technique employed for this study is atomic force microscopy (AFM) with novel probing algorithms as well as novel tips with diameters down to 5 nm and aspect ratios of 10:1. Additionally, results acquired by critical dimension scanning electron microscopy and optical critical dimension scatterometry are presented. It was found that the unintentional LTL is resist- and pitch-dependent and can be higher than 9 nm at 16 nm half-pitch but does not correlate with line break defect density results. However, LTR measurements of small area scans at dense line/space pitches may be used to draw conclusions about line break defect densities and hence yield. The resist specific metrics, LTR and LTL, allow for fast and early-on evaluation of new chemical formulations and help to forecast pitch- and dose-dependent performance. Furthermore, the results can be used to improve resist model accuracy for optical proximity correction calculations.

We propose a methodology for the mathematical and quantitative characterization of the deviation of rough line/space patterns from their ideal smooth shape to identify defects related to line mass and shape. The methodology is applied in real AFM images of line/space patterns while a modelling framework is elaborated for the generation of rough line/space patterns with controlled top and sidewall roughness and size variations. We also explore the consequences of the proposed methodology in the metrology of LER and its relation to 3D patterns.

With the ever increasing demand for higher transistor density and improved functionality, the nanostructures on modern semiconductor chips become more and more complex and their modeling requires a multitude of parameters. As a result, the performance of scatterometry as state-of-the-art optical inspection tool is limited by insufficient sensitivities towards certain parameters and high cross-correlations between them. In order to improve the model-based reconstruction, it is essential to generate as many uncorrelated datasets as possible. In this paper, we propose to combine conventional Fourier scatterometry with Mueller polarimetry and white-light interferometry to measure both angle- and wavelength-resolved Mueller matrices. This approach takes advantage simultaneously of the most relevant information channels of the light field: intensity, wavelength, phase, propagation angle, and polarization. We validate the performance improvement in case of multi-parameter problems by means of a comprehensive simulation study. In general, both the measurement uncertainties and the cross-correlations are reduced in comparison to other scatterometric configurations. Furthermore, our approach facilitatesthe reconstruction of target asymmetries, such as asymmetric sidewall angles, or the analysis of isolated line gratings at low technology nodes. Aiming at an experimental validation as well, we finally show results from first proof-of-principle measurements performed during the ongoing setup implementation.

The three-dimensional architectures for field effect transistors (FETs) with vertical stacking of Gate-all-Around Nanowires provide a pathway to increased device density and superior electrical performance. However, the transition from research into manufacturing will only be successful if their feature shape, critical dimensions, and associated electrical performance are repeatable across the integrated circuit, across the wafer, and among multiple wafers. Patterning process control for these structures will require significant advances in metrology. Two techniques that are potential candidates for this purpose are Mueller Matrix Spectroscopic Ellipsometry based Scatterometry (MMSEscatterometry) and Critical Dimension Small Angle X-Ray Scattering (CDSAXS). In this work, we highlight the characterization of the Nanowire Test Structures fabricated from patterned Si/Si_xGe_1-x/Si/Si_xGe1-x/Si/Si_xGe_1-x/Si structures using CDSAXS. Preliminary experimental data shows sensitivity to the selective etching of subsurface SixGe1- x. CDSAXS diffraction data provides information in reciprocal space about line shape and periodicity as well as the amount of subsurface etching. Side lobes in the Intensity vs. Q_z (structure height) data are observed around Qz positions of around 0.15 nm^-1 and 0.5 nm^-1 and are at the same positions in the measured and the simulated data for different amounts of Si_xGe_1-x etch in the Nanowire Test Structures. This demonstrates its ability for successful measurement of the critical dimensions and 3D profile of the Nanowire Test Structures, which can then be extended to monitor several key process steps for Nanowire/Nanosheet FET fabrication.

In this contribution nanoscale gratings are characterized by means of broadband EUV spectroscopy with wavelengths from 10 nm to 15 nm. The study focuses on the specifics of this spectral range that can be beneficial for metrology applications in lithography. Experimental investigations are carried out on fused silica nanoscale line gratings in a stand-alone laboratory-based setup. A corresponding sensitivity study is carried out analyzing the influence of grating parameter variations on EUV reflectance curves. Subsequently, experimental uncertainties are propagated to accuracies of grating parameter extraction. Using rigorous simulations in combination with machine learning, limitations of the technique are discussed regarding industrially relevant gratings. Extending the method through analysis of higher diffraction orders is evaluated.

The native self-alignment of area-selective deposition (ASD) processes makes this technology a promising solution for precise pattern positioning in the EUV era. The key challenge for any ASD process is its defectivity associated with the deposition on the growth-inhibiting surface. Therefore, the ability to qualify an ASD process using the appropriate set of in-line metrology tools is crucial for up-scaling of the technology. In this work, we present a new concept of area-selective ALD TiO2 growth and use it as an example to show the potential of in-line OCD and XPS tools for evaluation of ASD processes. The proposed novel process is based on selective growth of TiO2 on top of SiO2/SiN in the presence of plasma halogenated amorphous carbon (a-C:H) acting as a growth-inhibiting layer. The exposure of a-C:H to CF4 or Cl2 plasma results in formation of a thin halogen-rich film suppressing nucleation of TiO2, while the latter is minimally affected on the plasma treated SiNx or SiO2 layers. The selectivity was assessed on both blanket films and 45 nm half-pitch a-C:H line patterns. The analysis of blanket a-C:H substrates showed that the plasma chlorination provides a substantially more efficient growth inhibition as compared to the fluorination. However, the ability of the CF4-plasma to etch the topmost surface of the a-C:H makes it more favorable for application on a-C:H patterns, surface of which is typically contaminated with residues from hard-mask or from the patterning plasma. Therefore, the pre-cleaning of the a-C:H line pattern surface with CF4-plasma is required to restore the growth blocking efficiency of the chlorinated a-C:H.

Line-edge roughness (LER) is often measured from top-down critical dimension scanning electron microscope (CD-SEM) images. The true three-dimensional roughness profile of the sidewall is typically ignored in such analyses.

We study the response of a CD-SEM to sidewall roughness (SWR) by simulation. We generate random rough lines and spaces, where the SWR is modelled by a known power spectral density. We then obtain corresponding CD-SEM images using a Monte Carlo electron scattering simulator.

We find the measured LER from these images, and compare it to the known input roughness. We find that, for isolated lines, the SEM measures the outermost extrusion of the rough sidewall. The result is that the measured LER is up to a factor 2 less than the true on-wafer roughness. The effect can be accurately modelled by making a top-down projection of the rough edge. Our model for isolated lines works fairly well for a dense grating of lines and spaces, as long as the trench width exceeds the line height.

In recent years semiconductor manufacturers have increasingly employed deep through-silicon via (TSV) at the front end of line (FEOL) process steps, combined with using an increased number of multilevel, three-dimensional (3D) layers with different material stack at the back end of line (BEOL) process steps. This increased usage results in enhanced requirements for 3D feature characterization during the process development steps, as well as with monitoring and failure analysis during production.

Traditionally, deep TSV features during the FEOL are analyzed by cleaving (breaking) the wafers and observing the cross section. At the BEOL, focused ion beam (FIB) cross section and etch back or chemical mechanical polishing (CMP) of layer-by-layer are used to characterize the 3D multilevel layers. Both methods result in a slow turnaround time (TAT), but most importantly, cross section analysis only gives two-dimensional (2D) information about 3D multilevel structure and can miss abnormalities. Etch back or CMP has relatively low quality, accuracy, and repeatability and results in full wafer scrap.

Inline Xe plasma FIB (PFIB) has become an important tool for 3D feature characterization and failure analysis in the chip manufacturing production line. Layer-by-layer excavation (also known as delayering) of a specific site provides enhanced metrology and reconstruction of complete 3D features. Thus, manufacturers can identify process abnormalities of the complete structure. Moreover, inline delayering, combined with cross sectioning of specific sites, enhances the TAT. The wafer can return to production for further analysis, and manufacturers can study the effects on different steps.

When manufacturing a semiconductor device having a three-dimensional structure, grasping the positional relationship between the upper and lower structures is important. Our “Dig & See” technology using GFIS-SIM enables such a device to be processed and its lower layers observed by quickly switching ion beams. With this technology, the digging of only the narrow areas of interest expedites delayering. Moreover, the structure of the lower layer can be exposed by top-down delayering and observed without using another tool. Unlike with other methods, the position of the lower layer can be determined with reference to the upper layer position.

As development of stacked Nanosheet Gate All-Around (GAA) transistor continues as the candidate technology for future nodes, several key process points remain difficult to characterize effectively. With the GAA device strategy, it is critical to have an inline solution that can provide a readout of physical dimensions that have an impact on the threshold voltage (VT) and yield. Metrology challenges for obtaining these metrics arise from increasingly dense arrays coupled with both high aspect ratios, high numbers of correlated parameters, and increasingly complex 3D geometries. Large area metrology structures can be used for 3D parameters’ process monitoring through techniques such as scatterometry and xray diffraction (XRD) which deliver averaged results over that area, but variation impacting specific devices cannot currently be understood without destructive cross-section. Prior work to characterize the dimensions of these GAA devices has primarily featured optical metrology, X-ray metrology, and critical-dimension scanning electron microscopy (CDSEM), but these techniques have their own challenges at the critical process points. Atomic force microscopy (AFM) had not been utilized due to the aspect ratios and small trench widths which were inaccessible to conventional techniques. However, due to recent advances in scanning and novel probe technologies, AFM is well-suited now to solve these local, three-dimensional challenges. Through this study, we demonstrate AFM characterization of a key process point in the GAA process flow for multiple structures with varying channel lengths, after epitaxial (epi) growth along the Si sidewall. The AFM scan results are compared to CDSEM images for top-down corroboration of topography and to other reference metrology for height correlation. The impact of measured variations in epi height to device performance is also reviewed.

Node to node design rule are shrinking to enable better performance envelope in storage, computing power and electrical usage. A major part of every technology development is verification of the actual device overlay for thick stacks. Today the IC manufactures utilize TEM, Fib and other methods to understand the impact of overlay for thick stacks. These methods, which are considered as a “ground truth” of the fab, can give very good resolution of the features shape characteristics, material contrast, metrology and defectivity. That said, some are destructive and have long time to results. Another approach for thick stack is to use eBeam high kV landing with elluminator technology, this enables fast see through measurements of overlay, yet this approach has also limitation where layer stack thickness exceeds see through imaging capability while chipmakers still require seeing the bottom layer to measure the overlay. In this paper, we propose a flow of accurate in-line runtime delayer method flowed by an eBeam elluminator technology for overlay verification as an extension of current eBeam measurement capabilities. This flow can be complimentary for different applications space where there’s imaging limitation of the eBeam. The excellent local delayer control enables shorter time to root cause, process and design verification metrology (as a “golden ruler”) in runtime fab. The work is based on IMEC frontend wafer at source drain Implant process steps after Hard Mask Etch. Looking at device features we explore the accuracy of new flow in sampling fins, dummy gate and Hard mask openings for implant process steps. Reference eBeam metrology will verify the accuracy of the delayer metrology.

Dual beam focused ion beam/scanning electron microscopy (FIB/SEM) is a key characterization technique for rapid process development of electronic devices with complex geometry such as magnetic read/write heads in hard disk drives (HDD). Despite the destructive nature of FIB/SEM, it is still used as an in-line metrology technique supporting high volume manufacturing (HVM) process control. To overcome the throughput limitation of this technique and minimize the impact on product shipment time, it is a common practice to have a fleet of FIB/SEM tools in line. Hence, controlling the total measurement uncertainty (TMU) for the reference metrology fleet is essential. However, the existing TMU evaluation methods are mainly developed for non-destructive or less-destructive metrology techniques, which allows measurement repetition. [1], [2]

Scatterometry is an optical metrology technique designed for analyzing the changes of light intensity in a device. This technique is widely used for the wafer metrology of nanostructured surfaces in the semiconductor industry. There are two scatterometric approaches: angle-resolved and spectroscopic scatterometer.^{1, 2} Angle-resolved scatterometry involves single-wavelength readings at various angles, and measure both zeroth-order and first order diffractions. Spectroscopic systems work at a fixed angle of incidence but in broadband wavelengths range in the visible or UV, and measure only the zeroth-order diffraction. In contrast to angle-resolved and spectroscopic scatterometries, the proposed extreme ultraviolet (EUV) scatterometer is designed to measure the intensity of non-zero-order diffractions at a fixed incident angle and at multiple laser-like wavelengths. The short wavelengths of EUV, which give rise of several diffraction orders of scattering from nanoscale grating features. The well-separated higher-order diffraction beams are more informative than the zero-order diffraction beam, coupled with a very efficient rigorous coupled-wave analysis (RCWA), can achieve a detailed reconstruction of the profile of nanoscale periodic gratings. In this paper, however, describes the use of yet two more methods for breaking correlations and increasing sensitivity—include the use of non-zeroth order (m = + 1 and m = −1) diffracted light and polychromatic wavelengths of high harmonic generation (HHG). For many structures, this flexibility significantly increases parameter sensitivity and reduces parameter correlation.

Beyond the 5nm technology node, interconnect scaling has an impact on metal material selection: usage of copper may hit a limit with respect to resistance and reliability performance [1]. Thickness of barrier and liner (required for copper) cannot be reduced further, meaning that trench width reduction will have a negative effect on the relative copper volume. Grain boundary scattering increases as well, which in turn further increases resistivity and resistance. One of the best alternatives is Ruthenium (Ru), but dual-damascene processing is difficult with Ru (requires improvements in Ru filling of narrow high aspect ratio trenches and in Ru CMP selectivity and defects). So, a Back End of Line (BEOL) material change may require a move to a semi-damascene integration with direct Ruthenium metal etch [2]. This shift from a well-known dual-damascene flow, based on metal CMP, to a semi-damascene flow, based on metal etch integration, will require a new set of metrology capabilities, which are studied in this paper. In the current study, Scatterometry is widely used in all semi-damascene process steps to monitor both dimensional and material properties. Important measured parameters include thickness, full profile details, grain size, and roughness of metal lines—all parameters that are required for feedback and in-line process control. We will describe how these parameters can be monitored using a single Scatterometry metrology system. The semi-damascene process development described in this paper exploits EUV lithography at a critical dimension (CD) of 16 nm and 32 nm pitch and includes the optimization of the following process steps: 1. Metal deposition techniques: ALD and PVD, with a wide range of metal thickness. 2. Anneal , affecting grain size. 3. Etch process , for optimal metal line profile and roughness. The Scatterometry results were evaluated and verified by reference techniques such as CDSEM, and HAADF-STEM. The goal of the process optimization was Ru resistivity and resistance. In-line Scatterometry was shown to accurately predict the resistance of the Ru lines — parameter that is measured at the end of the processing, and is affected by all processes, including deposition, annealing, and etch. Prediction was carried out by a machine learning algorithm, based on an E-test, combining the contribution of all three process steps into a single output, at the post-etch measurement phase.

As the lithographically manufactured nanostructures are shrinking in size, conventional techniques, such as microscopies (SEM, AFM) reach their resolution limits. We have developed a high-performance Grazing Incidence SAXS simulation tool to reconstruct the in-depth profile highly ordered material such as line gratings [1, 2]. Here, we will present the latest development and applications of the technique using x-rays to characterize line gratings and contact holes. Specifically, we will show how the CD-GISAXS approach has been extended to extract the in-depth profile dispersion of the lines, leading to a quantification of the line edge roughness. Finally, by introducing a recent study which harnessed the chemical sensitivity provided by soft x-ray scattering to extract latent image profiles from resists [3], we highlight new applications for this technique with high potential.

Recent studies for profile reconstructions of nanostructures produced with self-aligned quadruple patterning (SAQP) indicate the limits for solving the inverse problem with a rigorous simulation. Using Monte Carlo methods for the theoretical investigation of the observed pitchwalk behaviour is not feasible due to the high computational cost of simulating GISAXS measurements by solving Maxwell’s equations with an FEM approach for each proposed structural model. We will show that a surrogate model based on a polynomial chaos expansion is a versatile tool to reduce the computational effort significantly. The expansion provides not only a surrogate for the forward model, but also Sobol indices for a global sensitivity analysis. This enables the study of the sensitivities in GISAXS in detail.

Accurate, optics-based measurement of feature sizes at deep sub-wavelength dimensions has been conventionally challenged by improved manufacturing, including smaller linewidths, denser layouts, and greater materials complexity at near-atomic scales. Electromagnetic modeling is relied upon heavily for forward maps used to solve the inverse problem of optical measurements for parametric estimation. Machine learning (ML) approaches are continually under consideration, either as a means to bypass direct comparison to simulation or as a method to augment nonlinear regression. In this work, ML approaches are investigated using a well-characterized experimental data set and its simulation library that assumes a 2-D geometry. The benefits and limitations of ML for optical critical dimension (OCD) metrology are illustrated by comparing a straightforward library lookup method and two ML approaches, a data-driven surrogate model for nonlinear regression using radial basis functions (RBF) and multiple-output Gaussian process regression (GPR) that indirectly applies the simulated intensity data. Both RBF and GPR generally improve accuracy over the conventional method with as few as 32 training points. However, as measurement noise is decreased the uncertainties from RBF and GPR differ greatly as the GPR posterior estimate of the variance appears to overestimate parametric uncertainties. Both accuracy and uncertainty must be addressed in OCD while balancing simulation versus ML computational requirements.

CD measurements of advanced 3D-NAND Staircase process require development of new approaches in CD metrology [1]. The current CD SEM Contact Analysis used for 3D-NAND assumes that process control could be provided through a set of geometric parameters defining the contact shape (i.e. parameters of contact shape elliptic fit such as equivalent contact top diameter (Top CD), equivalent contact bottom diameter (Bottom CD), ellipticity, minor, major axis). The limitation of this approach for process control of complex structures was considered, and a new approach based on Grey Level Analysis of contact features in SEM images was proposed. However, this analysis is not enough for controlling the complicated 3D-NAND Staircase formation process steps, as contact holes with same geometric parameters but different depths cannot be separated by traditional CD SEM metrology measurement procedure (Figures 1 and 2). Thus, traditional CD SEM approach needs revisiting in order to work in situations where process control requires analysis of sophisticated Grey Level uniformity distribution. We propose a novel approach combining traditional metrology with machine learning methods. The essence of this new approach is to combine Grey Level attributes and traditional CD measured geometric parameters of the feature, obtained by traditional CD metrology flow, in a classification scheme (Figures 2 and 3). The proposed approach was qualified at Micron site demonstrating ~98% purity classification results.
The proposed approach is generic and can be extended to a large variety of process control applications. Enhancing regular metrology flow with the capability to classify Etch process quality eliminates the need for the expensive and destructive cross-sectional SEM analysis. Furthermore, this method has a clear advantage during the early R&D phase of process development as it increases the usefulness of the in-line metrology tool while the process is still immature and unstable.

Machine learning (ML) techniques have been successfully deployed to resolve optical metrology challenges in semiconductor industry during recent years. With more advanced computing technology and algorithms, the ML system can be improved further to address High Volume Manufacturing (HVM) requirements. In this work, an advanced ML eco-system was implemented based on big data architecture to generate fast and user-friendly ML predictive models for metrology purposes. Application work and results completed by using this ML eco-system have revealed its capability to quickly refine solutions to predict both external reference data and to improve the throughput of conventional Optical Critical Dimension (OCD) metrology. The time-to-solution has been significantly improved and human operational time has also been greatly reduced. Results were shown for both front end and back end of line measurement applications, demonstrating good correlations and small errors in comparison with either external reference or conventional OCD results. The incremental retraining from this ML eco-system improved the correlation to external references, and multiple retrained models were analyzed to understand retraining effects and corresponding requirements. Quality Metric (QM) was also shown to have relevance in monitoring recipe performance. It has successfully demonstrated that with this advanced ML eco-system, streamlined ML models can be readily updated for high sensitivity and process development applications in HVM scenarios.

A methodology of obtaining the local critical dimension uniformity of contact hole arrays by using optical scatterometry in conjunction with machine learning algorithms is presented and discussed. Staggered contact hole arrays at 44 nm pitch were created by EUV lithography using three different positive-tone chemically amplified resists. To introduce local critical dimension uniformity variations different exposure conditions for dose and focus were used. Optical scatterometry spectra were acquired post development as well as post etch into a SiN layer. Reference data for the machine learning algorithm were collected by critical dimension scanning electron microscopy (CDSEM). The machine learning algorithm was then trained using the optical spectra and the corresponding calculated LCDU values from CDSEM image analyses. It was found that LCDU and CD can be accurately measured with the proposed methodology both post lithography and post etch. Additionally, since the collection of optical spectra post development is non-destructive, same area measurements are possible to single out etch improvements. This optical metrology technique can be readily implemented inline and significantly improves the throughput compared to currently used electron beam measurements.

In multi patterning processes, overlay is now entangled with CD including OPC and stochastics. This combined effect is a serious challenge for continued shrink and is driving down the allowed overlay margin to an unprecedented level. We need to do everything to improve overlay where accurate measurement and control of wafer deformation is extremely important. This requires accuracy in overlay metrology that decouples target asymmetry from wafer deformation. Multiwavelength diffraction-based overlay (DBO) is positioned for providing such accuracy while maintaining the required measurement speed. At the same time, with the increase of process complexity in advanced nodes, several new types of target asymmetries are introduced. Some of such asymmetries vary even within the target / grating area (intra-grating) and some are so severe that it impacts the center of gravity shift of the overlay target.

As the industry moves from node to node, lithographers have been pushed to use complex models to correct overlay errors and drive down model residuals. High order models are now used in combination with Correction per Exposure capabilities for critical layers on immersion scanners ^[1]. Mean overlay intrafield signatures are linked to the reticles (current and reference) and illuminations used, therefore the intrafield High Order Process Correction (iHOPC) model should be as stable as possible in terms of correction parameters. However, iHOPC data shows that the overlay parameters can drift over time and a Run to Run can follow these slow drifts. IHOPC R2R integration in production overlay correction flow is discussed in this paper: How corrections are generated from overlay measurement? What metrics are used to secure the model application? What results on production lots can be achieved? Then, a focus is made on the model variability. To operate properly, the R2R needs a high frequency variability as low as possible. Some factors like scanner lens aberration correction, metrology tool matching, measurement layouts, have been found to have an impact on lot-to-lot variability. These effects will be investigated in this paper to provide a conclusion on the usage of an iHOPC R2R for mean overlay intrafield signatures.

Reducing the overlay error between stacked layers is key to enabling higher pattern density and thus moving towards high performance and more cost effective devices. However, as for specific applications like macrochips with photonic interconnects and high-resolution image sensor flat panels with advance polarizers, customers require product field sizes that are larger than the maximum field size available on scanners. Those large fields are obtained by stitching together multiple standard fields. The overlay performances between two adjacent dies are as aggressive as what is usually required between two stacked layers. For this application, the well-established polynomial overlay model is not suitable as the displacement is measured relatively and the metrology sampling in the field is such that some high order nonlinear (K) terms cannot be modeled independently. Furthermore, a perfect grid is needed in mix and match production. The intrafield correction capability of the exposure tool is not the same for each process steps. For example, no intrinsic K13 can be printed for a mix and match process flow that includes an Extreme Ultra-Violet (EUV) litho step. In addition, some KrF scanners with fewer lens manipulators cannot correct for K9. Measuring the stitching and correcting it at the first layer will prevent printing K terms that are not correctable later in the process. In this paper, the need to characterize and control single-layer overlay among different pattern placement mechanisms intrinsic to the scanner was studied: optical aberrations, field-to-field position, mask placement and registration. An ASML set-up BP-XY-V3 reticle was used to generate a large experimental dataset to validate stitching models supported by Overlay Optimizer (OVO). Overlay measurements were done Resist-in-Resist using new YieldStar (YS) interlaced stitching Diffraction Based Overlay (μDBO) targets that were designed and validated. This paper will present on product metrology results of a scatterometry-based platform showing production results with focus not only on precision and on accuracy, but also assessing target performance and target-to-target delta without process influence. A high order stitching model was developed and verified on a Multi-Product Reticle for a large device application. Trench width control at the field intersection was studied then optimized with proximity correction to ensure a perfect field-to-field junction.

Atomic Force Microscopy (AFM) is a proven technique applied in research environments, most commonly in materials science and biological research. More recently, requirements in semiconductor manufacturing advocate that probe microscopy has potential to assist with the new metrology techniques associated with device scaling and the corresponding increase in 3D structures. In this paper a novel form of AFM called the Rapid Probe Microscope (RPM) will be demonstrated operating at high data acquisition rates; with images collected in seconds, combined with the ability to characterise individual 3D structures with sub nanometre accuracy. The capability of the RPM will be illustrated by measuring a suite of 2D EUV posts of 26nm dimension in staggered topology with 40nm minimum pitch. These structures were developed as part of IMEC’s EUV lithography patterning development program. The high throughput of the RPM enables the collection of multiple site and multiple pitch data, from a focused exposure matrix. Automated batch processing tools have been developed to enable the effective analysis of the high volume of data produced. The data can then be extensively interrogated to fully understand how the structure of the posts is related to the lithography process. In addition to a statistical analysis of the entire pillar population, the analysis tools can isolate and measure each individual pillar, providing the ability to compare the height and shape on an isolated pillar by pillar bases.

On Product Overlay (OPO) is a critical budget for advanced lithography. LithoInSight (LIS), an ASML application product, has proven to improve the ability of advanced process control (APC) for overlay with accurate fingerprint estimation and optimized scanner correction. It is now often used as Process of Record (PoR) for performing chuck/lot based run-to-run (R2R) control in a High Volume Manufacturing (HVM) environment. In order to further improve the on-product performance given the ever-tightening overlay spec. in advanced nodes, the question of how to reduce wafer-to-wafer process-induced variation has been asked frequently. Studies have shown that the wafer-to-wafer overlay variation is driven by certain critical process contexts. Aiming to bring a solution to the HVM phase, the ASML and Micron Data Science teams developed a Wafer Level Grouping Control (WLGC) methodology to perform overlay control given the process context information. This methodology has been implemented in one of the Micron production fabs, and demonstrated both reduced wafer-to-wafer (W2W) overlay variation and improved device yield on a yield-critical layer for a product from Micron 1z DRAM node.

On product overlay (OPO) challenges are quickly becoming yield limiters for the latest technology nodes, requiring new and innovative metrology solutions. In this paper we will cover current and future overlay trends in logic and memory device processing. We will review new lithography overlay challenges and node-after-node trends in the OPO error budget for advanced logic, DRAM, and 3D NAND devices. The central question of this paper is whether optical overlay metrology can keep up with challenges that include accuracy, intra-field variability, target-to-device offset, and others. After surveying the two dominant technologies in optical overlay metrology (IBO and SCOL^®), we will outline innovative solutions that will help to address metrology challenges for the new device nodes.

As a follow-up to last year’s “What is prevalent CD-SEM's role in EUV era?” [1], here we report our ongoing progress on total metrology solutions for the sub-10-nm extreme ultraviolet (EUV) lithography process. We discuss two technical approaches that have emerged following our previous work. First, similar to conventional minimization processes, we focus on improvements in the top metrology task, down-to-ångström-order tool matching, namely, “atomic matching”, which is a crucially important feature in all in-line metrology tools in the EUV era. Second, we examine a comprehensive solution that enables EUV-characterized featured process monitoring with greater accuracy, higher speed, and smarter metrology.

This study explores SEM induced shrink on EUV resist at different SEM scanning conditions from traditional to low landing energies. Measurement results of different targets, constant space of 28 nm and different pitches, across FEM wafer demonstrate both charging and resist shrink impact on measurement sensitivity and uncertainty. AFM measurements, SEM vs fresh locations are performed to quantify 3D morphology changes of the EUV pattern.

Process monitoring of extreme ultraviolet (EUV) photoresist requires critical dimension analysis and careful control of extracted parameters like line edge roughness (LER) and line width roughness (LWR). Automated SEM metrology typically provides estimates for these parameters, including critical dimensions and “shape, ” but at the cost of SEM exposure modifying the shape and size of the material systems. A method for acquiring and analyzing dense line structures using TEM tomography is proposed. Automation of the process from in-fab photoresist encapsulation through dual-beam lamella preparation to tomography acquisition is described, followed by a discussion of novel methods for volumetric reconstruction with metrology. Measurement capabilities are compared to CDSEM and AFM. Novel three-dimensional constructs illustrating process and property relationships in the lithography module are provided.

In order to meet the tightened lithography performance requirement for EUV systems, a good on-product focus control with accurate metrology is essential. In this manuscript we report on a novel metrology solution for the EUV on-product focus measurement using YieldStar. The new metrology has been qualified on the Logic product wafers and when combined with the advanced techniques and algorithm shows a performance that is accurate and precise enough to meet EUV requirements. Furthermore, the new methodology provides the opportunity for on-product focus monitoring and control through different scanner interfaces. Here we present a case in which the Imaging Optimizer using the EUV metrology data shows an improvement of over 20% on the focus uniformity.

Shrinking design rule coupled with complex device geometries and introduction of new materials in the manufacturing of today’s semiconductor devices generate inherent device weak points which in turn give rise to mechanisms that result in yield impacting defects. The development and introduction of finFET has helped considerably in the quest to further shrink design rule. However, the design and complex manufacturing process involved in producing these high performance finFET devices bring with it a whole new class of defects that have considerable impact on device performance and yield. Some of these defects are buried beneath the wafer surface and are very difficult to detect. They are often missed by optical inspection, only to cause fails at final testing. Failure analysis (FA) then becomes the only means by which they are uncovered. FA is a destructive methodology and its benefits are realized only after the fact. Unlike FA, e-Beam inspection is non-destructive. e-Beam uses electron optics and has a unique ability to detect buried defects electrically by voltage contrast (VC) between a defective structure and its reference. As process window gets tighter and tighter process margin becomes difficult to predict. In this work, e-Beam inspection and overlay data is used to identify process weakness regions on wafer to predict fails and help optimize process and improve yield.

Advanced nodes require tighter and tighter overlay control to secure products yield. Market like automotive one are even more demanding on “overlay reliability” till the extreme edge of wafers. High order models including Correction per Exposure capabilities are now introduced on the most critical immersion layers to put extra correction on the edge of wafers scanner fields. To ensure a correction model able to bring back these fields under overlay specification, the understanding of key process/equipment parameters to be put under control is needed. In this paper, choices done in term of overlay and Run to Run model will be discussed. On tools aspects, scanner table clean frequency impact and etch chambers variability will be addressed. In addition, etch recipe can modulate this etch chamber effect. The paper will conclude on the compromise to face in order to better correct and control overlay at the Edge of Wafer with the current Litho/Etch tools capabilities and R2R model strategy, at an acceptable cost (tool efficiency) and effort (rework, R2R complexity, …)

On-product overlay (OPO) challenges are quickly becoming yield limiters for the latest IC technology nodes, requiring new and innovative solutions to meet the technology demands. One of the primary means for reducing OPO error is the measurement of the grid (on target) at after-develop inspection (ADI) correctly and accurately. To reduce the optical error in the measurement, signals from both high voltage scanning electron microscope (HV-SEM) technology and imaging based overlay (IBO) measurements at ADI can be leveraged. Using key performance indicators (KPIs) and information produced by multiple optical measurement conditions, it is possible to optimize SEM sampling across the wafer and to capture all relevant target deformations. The objective is to improve the accuracy of optical measurements by efficiently combining information from HV-SEM and optical metrology systems. This paper will demonstrate that the information extracted from electron-based metrology and IBO measurements can be used for direct measurement of target deformations, which feeds into advanced optical target diagnostics and utilized for de-correlation between asymmetries and overlay (OVL).

A standalone alignment technology was developed as a fundamental solution to improve on-product overlay (OPO). It enables high performance alignment measurements, and delivers state-of-the-art feed forward corrections to exposure scanner. Dense alignment sampling and high-order field distortion correction is effective for scanner fingerprint matching and for heat related field distortions. A modeling and sampling optimization software is a powerful tool for dense sampling and high-order overlay correction with minimal throughput loss. We performed an overlay experiment using the standalone alignment technology coupled with a modeling and sampling optimization software, which demonstrates on-product overlay improvement potential for next generation manufacturing accuracy and productivity challenges.

In recent technology node manufacturing processes, on-product overlay (OPO) is becoming increasingly more important. In previous generations, the optimization of the total measurement uncertainty (TMU) itself was sufficient. However, with the use of modern technologies, target asymmetry-related measurement inaccuracy became a significant source of error, requiring new methods of control. This paper presents a machine learning (ML) based algorithm that reduces inaccuracy in misregistration measurements of the after-develop inspection (ADI) optical overlay (OVL). The algorithm relies on numerous features that were extracted from the OVL tool camera images, accuracy metrics derived from OVL computation, and other metadata. It is trained to estimate OVL measurement inaccuracy and produce corrected OVL per site. The ground truth of the ML model can include either internal or external OVL values. In the former case, the model is trained using wafer modeling errors (a.k.a. residuals), implying that these are a good indicator of target inaccuracy, which is a commonly used assumption. In the latter case, the model is trained using external overlay as the reference. If an accurate external reference overlay measurement exists, this option can be the most accurate. In both cases, the algorithm produces corrected OVL values. This study shows that for both ground truth options, the suggested method reduces inaccuracy and wafer modeling residuals in ADI optical OVL metrology measurements. The results were obtained by experimenting on production wafers from DRAM critical layers at SK Hynix. All the measurements were taken using an imaging-based overlay (IBO) technique and were validated by scanning electron microscope (SEM) measurements of the same wafers.

This paper reports line width roughness (LWR) measurement with edge averaging method (EAM) for different measurement length (L). The issues of LWR measurement are that raw LWR measurement data contains non-negligible image noise components and depends on L. EAM is an analysis method that creates several artificial images from 4D information (x axis, y axis, pixel color and frames) of scanning electron microscopy (SEM) and detects pattern’s edges. EAM is needed only 4 one-frame’s images. Power spectral density (PSD), auto-correlation function (ACF) and height-height correlation function (HHCF) using EAM edge data were studied. As the second topic, the relationship among CD variation, LWR and PSD curves are described. The balance of CD variation and LWR depends on L. For example, when L is shortened, LWR at low frequency component changes to CD variation. To clarify L is important to compare various LWR measurement results. Therefore, we propose “𝐿𝑊𝑅^x_r ” (x is “Biased”, “Unbiased” or “Noise”) to express LWR.

The market transition from 2D to 3D-NAND in recent years requires strict focus control and monitoring solutions. ASML’s μDBF targets (micro Diffraction Based Focus) enable on-product focus measurement which can be used to optimize scanner correction. Additionally, dense computational focus maps can be generated by combining μDBF measurements with scanner metrology such as non-correctable leveling error. This paper discusses the focus variability observed on memory layers through on product focus monitoring. This work will show how exposure at best focus can be performed for immersion lithography in the case of strong focus fingerprints. Focus monitoring data from μDBF and computational focus metrology will be used to generate and apply corrections on two 3D-NAND layers.

In this work a novel machine learning algorithm is used to calculate the after etch overlay of the memory holes in a 3DNAND device based on OCD metrology by YieldStar S1375. It is shown that the method can distinguish the overlay signals from the process induced signals in the acquired pupil image and therefore, enables for an overlay metrology approach which is highly robust to process variations. This metrology data is used to characterize and correct the process induced intra-die stress and the DUV scanner application fingerprint.

Self-aligned quadruple patterning (SAQP) has quickly become the most viable multi-patterning scheme adopted for manufacturing critical layers in logic and memory devices below the 10nm (N10) technology node. Occurrence of pitch walk is a very common phenomenon in post SAQP layers. If not properly managed, the absolute value and variability of pitch walk could result in either parametric yield degradation or catastrophic fin-loss defects. These issues result from the interaction with subsequent processes, such as keeps and cuts, which are used to define and isolate fin groups for building the transistors. Previous studies have shown that a combined lithography and etch methodology would help reduce the pitch walk impact [1]. In this article, we will show advanced control for SAQP pitch walk using a combined scheme of lithography, deposition and etch actuators, in a front end 5nm logic process. By the implementation of a rigorous pitch walk prediction model that is calibrated and validated with wafer data, we then expand the model coverage to include an edge placement error component. This accounts for the contribution of overlay from subsequent layers to predict patterning defect probability at the final stage of device structure formation. With this approach, we can identify the optimal process control loop that minimizes pitch walk effects while maximizes the process margin for subsequent layers for this integration scheme.

The method to perform Optical Proximity Correction (OPC) model calibration with contour-based input data from both small field of view (SFoV) and large field of view (LFoV) e-beam inspection is presented. For advanced OPC models - such as Neural Network Assisted Models (NNAM) [1], pattern sampling is a critical topic, where pattern feature vectors utilized in model training, such as image parameter space (IPS) is critical to ensure accurate model prediction [2-5]. In order to improve the design space coverage, thousands of gauges with unique feature vector combinations might be brought into OPC model calibration to improve pattern coverage. The time and cost in conventional Critical Dimension Scanning Electron Microscope (CD-SEM) metrology to measure this large amount of CD gauges is costly. Hence, an OPC modeling solution with contourbased input has been introduced [6]. Built on this methodology, a single inspection image and SEM contour can include a large amount of information along polygon edges in complex logic circuit layouts. Namely, a better feature vector coverage could be expected [7]. Furthermore, much less metrology time is needed to collect the OPC modeling data comparing to conventional CD measurements. It is also shown that by utilizing large field 2D contours, which are difficult to characterize by CD measurements, in model calibration the model prediction of 2D features is improved. Finally, the model error rms of conventional SFoV modeling and LFoV contour modeling between SEM contours and simulation results are compared.

Electron beam (EB) metrology of Ge channel gate-all-around (GAA) FET (field effect transistor) was investigated. Ge-GAA FET is one of the promising candidates for high performance pMOS device of future node. Ge is superior to Si in hole mobility which can be enhanced further by applying compressive channel strain in GAA structure with SiGe strain relaxed buffer (SRB). Coincide with this advantage, channel buckling could happen more easily. Thus, a monitoring method of channel buckling is required. Chemical instability of Ge is another issue in fabrication process. It is suspected that EB irradiation during SEM inspection could cause the deterioration of device performance. On this background, following two evaluations were performed. The first one is quantitative evaluation of channel buckling. It is found that the channel buckling can be quantified with a proposed buckling index. The second one is assessment of the EB-induced damage on the electrical properties. The results showed that EB irradiation on Ge channels does not affect the device performance when the device is annealed adequately. In conclusion, EB metrology is effective for the evaluation of channel buckling and applicable to Ge channels without deterioration of the device performance.

In the semiconductor manufacturing industry, Automatic Defect Classification (ADC) plays an important role in maintaining high wafer inspection quality and reducing yield loss. ADC performance has benefitted from using machine learning (ML) algorithms; however, performance is negatively affected by the data imbalance and limited amounts of training data. Synthetic Minority Oversampling Technique (SMOTE) is an oversampling technique to adjust the skewed class distribution of a dataset so that the bias of the majority class is reduced. This paper shows that applying SMOTE achieved higher accuracy and purity on two imbalanced datasets, consisting of scanning electron microscopy (SEM) images collected with ASML-HMI eP™ and eScan^® series inspection tools. The ML models are also less sensitive to the selection of hyperparameters when SMOTE is applied. We also show that better classification results can be obtained with less training samples with SMOTE; we conducted an experiment where a ML model trained on only 25% of samples with SMOTE achieved a higher ADC accuracy and purity performance compared to the same ML model trained on all samples but without SMOTE. In another experiment using a highly imbalanced SEM dataset with very few counts of the defect-of- interest (DOI), the combination of SMOTE and random undersampling of the majority class improves the accuracy by up to 5x while maintaining the same level of purity.

Continuous reduction in pattern size, the primary path of advancement for the semiconductor industry, has greatly increased resolution and throughput demands for defect inspection and metrology, where Electronic-beam (E-beam) wafer inspection equipment has been commonly used for both purposes. High resolution is specifically needed in order to inspect or measure these smaller patterns and is accomplished by either decreasing pixel size or increasing frame averages. Both of these adjustments come with a big penalty of throughput, which is an extremely important metric as large areas of the wafer must be inspected in a reasonable time to meet semiconductor development, yield ramp and high volume manufacturing process control requirements. A slow inspection means more inspection tools are required and lots are delayed by the longer process time. In order to regain throughput, it is common to try to back off on the frame averages, but this often results in low quality images with noise, blurring effects, and distortions. The end result is less defect sensitivity for inspections, lower CD measurement accuracy and precision for metrology. Image quality enhancement (IQE) algorithms can compensate for this and thereby play a significant role in achieving higher throughput while keeping sufficient sensitivity. In recent years, deep learning methods have demonstrated superior performance to traditional algorithms for IQE. However, these methods often require clean ground truth data for supervised training purposes, which is extremely difficult and expensive to achieve. For example, ground truth images with lower noise levels can be obtained by averaging hundreds of frames at the same location, but, in addition to taking a very long time, can cause permanent physical damage to the wafer due to the E-beam wafer imaging process, and unexpected artifacts or shadowing effects. In order to alleviate these issues, we propose an unsupervised machine learning- based image quality enhancement framework (uMLIQE) using deep learning methods, which does not require clean target images for the training process. In fact, only one or a few images are required since the required information can be extracted by segmenting the available image. The performance of this system was compared both via simulation and experimentally to a comprehensive list of alternate IQE approaches. The wafer we used for data collection was generated with standard semiconductor processing representative of CMOS processing across the industry. The unsupervised approach is clearly superior to all alternatives both qualitatively and quantitatively. Our proposed unsupervised deep learning IQE framework for SEM images has proven superior for throughput enhancement for high resolution E-beam wafer imaging.

With continuous scaling and increased design and process complexity, there is an increasing need for semiconductor manufacturing process control. This need calls for not only advanced methods and more capable tools, but also additional intra-wafer and across-lot sampling in order to capture process variations and/or changes in process signatures. In this paper we will demonstrate high speed full wafer metrology use cases from the KLA CIRCL™ platform. The CIRCL platform is typically used for very high throughput inline macro defect inspection. Here we demonstrate that this tool can also be used for certain types of metrology applications. In this paper, we will investigate metrology opportunities with full wafer coverage for critical process parameters on two test vehicles: (1) a 32nm pitch regular line-and-space defect vehicle patterned with single exposure EUV and (2) an iN7 BEOL integration test vehicle, also patterned with single exposure EUV.

Utilizing a unique high NA optical system, a new methodology to measure device overlay accurately has been developed with a key differentiation. Historically, optical techniques to measure features below the image resolution require supporting measurement techniques to be used as a reference to anchor the optical measurement. This novel selfreference methodology enables accurate and robust optical metrology for device features after etch eliminating the need for external reference measurements such as Decap, x-sections or high landing energy SEMs. In this paper, we discuss how a high NA Optical Metrology system enables measurements on small area device replica targets, which enables the ability to create a reference target for device measurements. The methodology utilizes this reference target to enable accurate direct on device overlay measurements without the need for an external reference. Furthermore, the technique is expanded to improve the robustness of the measurement and monitor live in production the health of the recipe, ensuring accuracy overtime. This ultimately leads to a method to extend the recipes in real-time based on the health KPIs. The improved accurate and robust device overlay measurements have proven to improve the overlay performance compared to other techniques. This, combined with the speed of optical systems, enables unconstrained dense measurements directly on device structures after etch, allowing for improved overlay control.

The accurate and precise contour extraction on SEM image is important to measure overlay, improve OPC model, inspect tiny hot-spot, and so on. In 2019, we reported about the measurement repeatability of edge placement error (EPE) with Die-to-Database (D2DB) algorithm. In this study, we apply machine learning for the contour extraction to improve the measurement throughput with high accuracy and precision of EPE on 2D pattern. The pattern contour on SEM image can be extracted by processing gray-level profile data across the measurement line. Generally, in order to extract the precise contour, the direction of the profile should be perpendicular to the pattern contour. Although the direction used to be determined by the design pattern, it can’t be accurate enough to extract the contour exactly since the shape between the design pattern and the actual pattern are different. We propose the method that determines the direction of the profile acquisition using the contour taken by machine learning, which is more similar to the actual pattern contour than the design pattern contour. The accuracy and the precision of EPE measurement using the contour extracted by our method has been improved in actual SEM images captured repeatedly.

Overlay control for recording head manufacturing is becoming increasingly challenging as design geometry specifications tighten in the transition to advanced Heated Assisted Magnetic Recording (HAMR) devices. As overlay control requirements for critical patterning layers tighten below 5nm, the need for accurate and robust overlay metrology is key to enabling the patterning roadmap and improving yields. This work focuses on improving Imaged Based Overlay (IBO) metrology to ensure accurate overlay measurements for critical lithography steps in the recording head fabrication process. Selection of the optimal settings for color filter and Numeric Aperture (NA) parameters can have a significant impact on overlay measurement accuracy and Total Measurement Uncertainty (TMU) when setting up a new overlay metrology recipe^1-2. These overlay metrology recipe parameters can be selected to minimize the influence of process induced overlay target imperfections on the measured overlay ³. This paper reports our revised workflow for selecting IBO measurement conditions and evaluating pre-existing recipes for robustness. We utilize metrics such as the overlay model residuals, Tool Induced Shift (TIS), and Qmerit error in identifying recipes requiring improvement. The new “Train Log” feature available on KLA’s Archer™ IBO metrology tool platform can be used to compare the through focus contrast precision of different illumination conditions at the time of recipe creation. In this study, we show that an optimization workflow that utilizes the “Train Log” collection of the contrast precision metric and imageless recipes in selecting color filter and numeric aperture settings can significantly improve the overlay measurement repeatability and tool to tool matching.

Tool induced shift (TIS) is a measurement error attributed to tool asymmetry issues and is commonly used to measure the accuracy of metrology tools. Overlay (OVL) measurement inaccuracy is commonly caused by lens aberration, lens alignment, illumination alignment and asymmetries on the measured target. TIS impacts total measurement uncertainty (TMU) and tool-to-tool matching, and TIS variation across wafer can account for inaccuracy, if not fully corrected, as it depends on the incoming process condition. In addition, both lot-to-lot and wafer-to-wafer process variation are influenced by TIS in terms of overlay performance, which also includes metrology tool-to-tool efficiency in terms of throughput. In the past, TIS correction was only done using a small sampling, resulting in additional error in the measurement which was not corrected. Hence, a new methodology is explored to improve overlay measurement accuracy by Modeled-TIS (M-TIS). This paper discusses a new approach of harnessing Machine Learning (ML) algorithms to predict TIS correction on imaging-based overlay (IBO) measurements at the after-develop inspection (ADI) step. KLA’s ML algorithm is trained to detect TIS error contributors to overlay measurements by training a model to find the required TIS correction for one wafer. This information, along with additional accuracy metrics, is then used to predict the TIS for other wafers, without having to actually measure the wafers. In this paper, we present the results of a case study focusing on DRAM and 3D NAND production lots.

As the semiconductor industry rapidly approaches the 3nm lithography node, on product overlay (OPO) requirements have become tighter and as a result, residuals magnitude requirements have become even more challenging. Metrology performance enhancements are required to meet these demands. Color Per Layer (CPL) is a unique imaging overlay metrology approach that enables the measurement of each layer with individually-optimized wavelength and focus position. CPL allows the user to custom-define the most suitable conditions per layer, thereby ensuring optimal performance. Imaging-based overlay (IBO) utilizes CPL in order to overcome inaccuracies due to interactions between bottom and top layers. These layers are fundamentally different in that the top grating is usually the photoresist layer, but the bottom grating can be any process layer. Therefore, optimizing the conditions for each layer will maximize measurement accuracy. KLA’s Archer™ 700 metrology tool addresses these metrology challenges by putting CPL to use, where the Wave Tuner (WT) allows the user to select a specific wavelength. This paper presents this novel CPL approach and discusses its reduction in OPO and contrast, and reviews use cases from DRAM and 3D NAND. We will present the results from these case studies, focusing on SK Hynix DRAM production wafers.

In the drive toward sub-10-nm semiconductor devices, manufacturers have been developing advanced lithography technologies such as extreme ultraviolet lithography and multiple patterning. However, these technologies can cause unexpected defects, and a high-speed inspection is thus required to cover the entire surface of a wafer. A Die-to-Database (D2DB) inspection is commonly known as a high-speed inspection. The D2DB inspection compares an inspection image with a design layout, so it does not require a reference image for comparing with the inspection image, unlike a die-to-die inspection, thereby achieving a high-speed inspection. However, conventional D2DB inspections suffer from erroneous detection because the manufacturing processes deform the circuit pattern from the design layout, and such deformations will be detected as defects. To resolve this issue, we propose a deep-learning-based D2DB inspection that can distinguish a defect deformation from a normal deformation by learning the luminosity distribution in normal images. Our inspection detects outliers of the learned luminosity distribution as defects. Because our inspection requires only normal images, we can train the model without defect images, which are difficult to obtain with enough variety. In this way, our inspection can detect unseen defects. Through experiments, we show that our inspection can detect only the defect region on an inspection image.

Critical dimension analysis of cross-section image with delicate accuracy has become important demand for semiconductor manufacturing. In traditional analytic method, manual measurements always accompany large deviation and lower measured efficiency. Therefore, a robust and reliable analysis method is most essential objective to obtain accurate dimensions from PFA results. In this work, we demonstrate an intelligent image analysis method which is combined Mask Region based Convolution Neural Networks (Mask r-CNN) and image processing technique. Compared with manual measurement, intelligent image analysis method can achieve significant improvement on measured results in reproducibility, repeatability, and efficiency. This intelligent image analysis will provide novel applications in CD measurement, wafer defect analysis, and focus-exposure process window judgment.

The Rapid Probe Microscope (RPM), exists as an integrated solution for photomask repair, with its application extended to include wafer metrology in 2016 [1]. The RPM can acquire non-destructive, high resolution, sub-nm detail in all 3 dimensions, overcoming some of the limitations of conventional AFM. In addition, it is flexible and can be configured to run either in air or in vacuum. The RPM includes the innovative use of an interferometric detection system to simultaneously measure both the height and the deflection of the cantilever, while the probe is controlled through photo thermal actuation. This combination delivers an accurate, very fast, direct measurement of the height of the probe and the corresponding structure of the sample surface. The X,Y probe scanner movement is also monitored by an interferometer. This guarantees both the linearity and XY position of the probe tip, delivering a corresponding sub-nm metrology of the wafer structure.

In the latest 3D NAND devices there is a larger focus on measurement accuracy control, coupled with more traditional minimization of Total Measurement Uncertainty (TMU). Measurement inaccuracy consumes an increasingly significant part of the overlay (OVL) budget, requiring control and optimization.

In this paper we will show the improvement in imaging OVL measurement accuracy using wave tuning (WT) capability combined with advanced algorithms to address 3D NAND process challenges. In addition to new OVL target designs that take advantage of WT capability, we also demonstrate improvement in OVL model residuals through optimization of measurement bandwidth, focus position and number of grab frames. Improvements in precision and tool-to-tool matching are also realized through both optimization of the region of interest (ROI) and splitting measurement areas using a dual-recipe technique.

In microelectronic device manufacturing, photosensitive organic insulators (POIs) are widely used during passivation steps to protect and preserve the chips from damage due to subsequent processes and from the external environment. To ensure high performance and to maintain chip quality, a well-controlled POI lithography process and corresponding defectivity monitoring are needed. In this work, we present an automated method developed by STMicroelectronics and KLA for POI defectivity and process control employing a KLA 8 Series inspection system with illumination in the visible range. The highly sensitive macro inspection tool with dedicated analysis approaches and solutions successfully enabled the detection of the principal defects of interest, the identification of defectivity root causes through automatic classification and review, and the evaluation of the layer thickness and uniformity through reflected intensity heatmaps. For several months, this protocol has been applied to the production environment, proving to be effective in detecting even small deviations from the standard process. Here, we present some promising results obtained with this strategy, highlighting the benefits in terms of rework reduction and improved equipment management.

Metrology requirements at advanced nodes are not only tightening on specifications but also broadening in terms of flexibility needed to cover variety of product stacks. Metrology targets need to be process compatible and at the same time these targets should also be readable by the metrology system. In some cases, process conditions require a target pitch that is large compared to the wavelength used by the metrology system. Examples of these situations include for instance topography transfer or stacks with thick resist (for e.g. 3D-NAND). Traditionally overlay is extracted from the asymmetry in the positive and negative first diffraction order generated from μDBO targets. However, when the pitch is large, the targets generate multiple higher diffraction orders. Current state-of-the-art diffraction based overlay systems do not take into account the effect of these higher diffraction orders and typically only select the first diffraction order. This is done by reducing the pitch of the target, tuning the wavelength or by changing the angle of incidence of the illumination light. To address wavelength over pitch flexibility an advanced algorithm was introduced on a new metrology system in the fab, providing full flexibility in the selection of measurement wavelength and pitch. To obey the specifications on accuracy and throughput, we will present a new metrology system that is, compared to its predecessor, about 2x faster and able to measure more accurately because of the ability to measure multiple wavelengths within the same time frame.

The paper represents a comparison of simulated light scattering of the near and far fields of subwavelength grating at various wavelengths. By quantifying and comparing the scattered near and far fields of multiple grating parameters to the nominal parameter based scattered field, the sensitivity to the change of grating parameters is determined. The wavelength influence on the near field is analyzed by applying a plane wave at certain angle of incidence and the far field diffraction patterns are simulated by applying coherent focused light (conical incidence). The paper analyses how each wavelength affects the sensitivity to the change of the height and the sidewall angle of a subwavelength grating.

One of the challenges of surface characterization at the nano-scale is that analytical tools which are capable of topological nano-scale analysis have limited capabilities for molecular characterization. Here we present a study on molecular characterization of positive tone photo-resist films with varying exposure dose. The technique is based on secondary ion mass spectrometry, SIMS, with gold nanoparticles (e.g. Au⁴⁺₄₀₀). In the methodology a sequence of individual gold nanoparticles is used to stochastically bombard the photoresist films, where each impact results in the emission of ions from a region 10-20 nm in diameter. The technique has several unique features which enable molecular characterization at the nano-scale. Firstly, the use of individual massive clusters impacts which sample nano-volumes, and from these nano-volumes multiple molecular ions can be ejected simultaneously. Secondly, the acquisition of the mass spectra from each projectile impact allows co-ejected ions to be collected in the same mass spectrum. These two features allow for tests on the nano-scale homogeneity of molecules. This is of particular interest for photoresist films, where nano-scale inhomogeneity may result in poor quality films. In this study we examined bulk photoresist films with varying dose post development, in order to probe physical aggregation and chemical transformation on the partially exposed resist pattern side wall and surface. We found that the cation and anion of the photoacid generator were not removed equally during development, and we found that the quencher is not completely removed by the developer.

For today’s advanced processes, in order to achieve higher optical lithography resolution, some of the layers require extreme dipole illumination conditions. One example is the modern DRAM process, where numerous critical layers are patterned with extreme dipole scanner illumination. Conventional (both imaging-based and diffraction-based) overlay marks on such layers typically use horizontal or vertical lines that suffer from insufficient accuracy in overlay device tracking. The new Diagonal AIM (DAIM™) overlay mark mimics the actual device through the usage of tilted structures. Significant improvement in device overlay tracking was demonstrated using the DAIM overlay mark.

On product overlay (OPO) shrink is a key enabler to achieve high yield in integrated circuit manufacturing. One of the key factors to enable accurate measurement on grid (target) is the use of optimized overlay (OVL) mark design to achieve low OPO. The OVL mark design enables accurate and robust OVL metrology and improves measurability and basic performance requirements such as total measurement uncertainty (TMU). In this paper, we demonstrate the methodology of mark design for different devices based on simulations, measurements and verification. We compare OVL performance of AIM® targets and grating-over-grating imaging targets utilizing the Moiré effect. Methodologies described in this work utilize robust AIM (rAIM™) targets, target design from the MTD AcuRate™ simulation-based OVL metrology target design tool, and the Archer™ OVL metrology system.

In order to achieve better resolution and improve lithography process window, device manufacturers are looking into or adopting high transmission attenuated phase shift mask (HTM). The critical dimension uniformity (CDU) of the device pattern can be quite a bit better with high transmission mask as compared to conventional attenuated phase shift mask, which makes it an attractive choice for advanced memory devices. However, it poses challenges on metrology targets such as alignment marks or micro diffraction-based overlay (uDBO) marks, which has different dimensions as device patterns as required by the metrology sensors. The challenges include printability, detectability, accuracy, process compatibility and defectively on the same device layer. In this paper we demonstrate solutions to address these challenges and thereby improve metrology for advanced memory devices with HTM. Without sacrificing mark contrast on wafer, the wafer quality of alignment mark is improved up to 10 times with respect to array like alignment marks and the stack sensitivity of uDBO mark can also increase more than 7 times as array like marks. Through a holistic target approach involving target design, target OPC, and recipe setup, we are able to achieve accurate metrology for optimal on-product overlay and device yield.

During wafer exposure, the scanner overlays product structures from the layer being exposed onto underlying layers, with a limited error margin. Alignment is the process of measuring pre-defined marks that have been exposed on previous layers and using these measurements to determine what adjustments to make during exposure. Current alignment marks are still quite big compared to overlay targets and fill quite some reticle-area. Therefore, there is a drive towards narrower and smaller alignment marks in order to free up scribe-lane space. Further, during design of narrower and/or smaller alignment marks, not only the width or length needs to be taken into account, but also the process loading effect and scribe-lane dummy following rules.

Maximizing product-area is an important driver for many DRAM customers. One way is by reducing scribe-lane space. Currently most customers are using 60um to 90 um wide scribe-lanes. However, developments are ongoing to further reduce this to 40um -50um. The current narrowest standard ASML alignment marks are 40 um wide and there is a growing demand for narrower and even smaller marks. Experiment tool groups configure selection with ASML SMASH senor and it brings more possibility in scribe-lane design and alignment size topic.

Tests with narrow alignment marks were done on an ASML XT1460K scanner with SMASH3.1 sensor. Both narrow DPCM (coarse align) and narrow NSSM marks (coarse and fine align) were tested and the impact on accuracy, repro and overlay was investigated. The width of the DPCM marks was reduced from 160um to 150um and 140um. The width of the NSSM (AA11 and AH53) marks was reduced from 40um to 30um and 28um.

This paper will explain the tests done in detail and will present the results of using narrow marks on alignment mark repro, mark KPIs (WQ, MCC, etc.) and overlay performance. These results will be compared to those of the standard marks. Also results from further alignment mark recipe optimization will be presented.

In this paper we introduce a new metrology technique for measuring wafer geometry on silicon wafers. Wave Front Phase Imaging (WFPI) has high lateral resolution and is sensitive enough to measure roughness on a silicon wafer by simply acquiring a single image snapshot of the entire wafer. WFPI is achieved by measuring the reflected light intensity from monochromatic uncoherent light at two different planes along the optical path with the same field of view. We show that the lateral resolution in the current system is 24μm though it can be pushed to less than 5μm by simply adding more pixels to the image sensor. Also, we show that the amplitude resolution limit is 0.3nm. A 2-inch wafer was measured while laying on a flat sample holder and the roughness was revealed by applying a double Gaussian high pass filter to the global topography data. The same 2-inch wafer was also placed on a simulated robotic handler arm, and we show that even if gravity was causing extra bow on the wafer, the same roughness was still being revealed at the same resolution after a high pass filter was applied to the global wafer geometry data.

In advanced DRAM semiconductor manufacturing, there is a need to reduce the overlay fingerprints. Reducing on device fingerprints with very high spatial frequency remains one of the bottlenecks to achieve sub-2nm on device overlay. After-etch device overlay measurements using the YieldStar in-device metrology (IDM)[1] allow for previously unassessed and uncontrolled fingerprints to be corrected employing higher-order overlay corrections. This is because this technology allows dramatically increased overlay metrology sampling at affordable throughputs. This paper reports considerations for enabling dense after-etch overlay based corrections in a high volume manufacturing environment. Results will be shown on a front end critical layer of SK hynix that has been sampled with IDM with high density wafer sampling, over dozens of lots spanning several weeks.

In the 14nm FinFET(Fin-shaped Field-Effect Transistor) node, SADP(Self-Aligned Double Patterning) technology has been introduced to produce Fin because of the exposure limit of 193nm DUV immersion lithography. As is known to all, pitch walking issue appears when the technology comes to SADP, so how to accurately measure pitch walking is particularly important. In this paper, we use CD-SEM(Critical Dimension Scanning Electron Microscope) to measure the CD(Critical Dimension) of Fin pitch inline, and evaluate different parameter settings or machine type to improve the accuracy of the measurement results. For sub-nanometer accuracy of line width measurement, TEM(Transmission Electron Microscope) image is used to calibrate the line width measurements as a kind of reference metrology.

Accurate segmentation of 3D-NAND memory cells and the interfaces of different materials within is the basis of reliable metrology for 3D-NAND memory fabrication. We are proposing a machine learning assisted fast marching level sets method (FMLS) to efficiently delineate material interfaces within 3D-NAND cells. This method works with single or multiple seed initialization that evolves and propagates towards object boundaries independent of topological merger and splitting. Images containing thousands of NAND cells can be processed within a few seconds using this method, making this a very convenient tool for inline metrology during fabrication. With an appropriate preprocessing, FMLS can be used to segment nonconvex structures, such as fins and gates, too.

Optical encoding technology is one of the most popular technologies with nano-meter degree accuracy in precise displacement metrology field. Basically, two optical gratings overlap in the encoder, resulting in Moiré fringes. An optical sensor records the Moiré fringes signal. When one of the optical gratings moves, the Moiré fringes will vary. The phase of the Moiré fringes is extracted from the signal, and the displacement is obtained from the phase. The fabrication always becomes more difficult and the cost is higher when the measurement accuracy becomes higher for such optical encoder. We have developed a simple, novel encoder with only one optical grating and an optical imaging system. The Moiré fringe curve is obtained when the optical grating overlaps with two complementary digital gratings which are virtually constructed with a CCD or CMOS sensor in a camera. In this technique, the Moiré fringe curve is not a strict sine wave, leading to some difficulty to accurately extract the phase value. This paper compares the performance of four phase extraction algorithms, i.e., Fourier transform, polynomial fitting, Hilbert transform and wavelet transform. The experimental results show that both the measurement accuracy and repeatability of the four algorithms are within 30 nm after calibration. The overall accuracy of the wavelet transform is the best with minimum error of only 5 nm. The processing speed of FFT is the fastest, reaching sub millisecond level.