This PDF file contains the front matter associated with SPIE Proceedings Volume 10589, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and Conference Committee listing.

This paper discusses the process challenges and limitations for 3D NAND processes, focusing on vertical 3D architectures. The effect of deep memory hole etches on die cost is calculated, with die cost showing a minimum at a given number of layers because of aspect-ratio dependent etch effects. Techniques to mitigate these etch effects are summarized, as are other etch issues, such as bowing and twisting. Metal replacement gate processes and their challenges are also described. Lastly, future directions of vertical 3D NAND technologies are explored.

A pattern transfer study was conducted to monitor the evolution of roughness in sub-10 nm half-pitch lines generated by the directed self-assembly (DSA) of a high-chi, silicon-containing block copolymer, poly(4-trimethylsilylstyrene)-block-poly(4-methoxystyrene). Unbiased roughness measurements were used to characterize the roughness of the structures before and after pattern transfer into silicon nitride. Parameters of the reactive ion etch process used as a dry development were systematically modified to minimize undesired line walking created by the DSA pre-pattern and to determine their impacts on roughness. The results of this study indicate that an optimized dry development can mitigate the effects of pre-pattern inhomogeneity, and that both dry development and pattern transfer steps effect the roughness of the final structures.

Multi-layer patterning schemes involve the use of Silicon containing Anti-Reflective Coating (SiARC) films for their anti-reflective properties. Patterning transfer completion requires complete and selective removal of SiARC which is very difficult due to its high silicon content (>40%). Typically, SiARC removal is accomplished through a non-selective etch during the pattern transfer process using fluorine containing plasmas, or an ex-situ wet etch process using hydrofluoric acid is employed to remove the residual SiARC, post pattern transfer. Using a non-selective etch may result in profile distortion or wiggling, due to distortion of the underlying organic layer. The drawbacks of using wet etch process for SiARC removal are increased overall processing time and the need for additional equipment. Many applications may involve patterning of active structures in a poly-Si layer with an underlying oxide stopping layer. In such applications, SiARC removal selective to oxide using a wet process may prove futile. Removing SiARC selectively to SiO₂ using a dry etch process is also challenging, due to similarity in the nature of chemical bonds (Si – O) in the two materials.

In this work, we present highly selective etching of SiARC, in a plasma driven by a surface wave radial line slot antenna. The first step in the process involves an in-situ modification of the SiARC layer in O2 plasma followed by selective etching in a NF₃/H₂ plasma. Surface treatment in O₂ plasma resulted in enhanced etching of the SiARC layer. For the right processing conditions, in-situ NF₃/H₂ dry etch process demonstrated selectivity values greater than 15:1 with respect to SiO₂. The etching chemistry, however, was sensitive to NF₃:H₂ gas ratio. For dilute NF₃ in H₂, no SiARC etching was observed. Presumably, this is due to the deposition of ammonium fluorosilicate layer that occurs for dilute NF₃/H₂ plasmas. Additionally, challenges involved in selective SiARC removal (selective to SiO2, organic and Si layers) post pattern transfer, in a multi-layer structure will be discussed.

Interest in atomic layer etching (ALE) has surged recently because it offers several advantages over continuous or quasicontinuous plasma etching. These benefits include (1) independent control of ion energy, ion flux, and radical flux, (2) flux-independent etch rate that mitigates the iso-dense loading effects, and (3) ability to control the etch rate with atomic or nanoscale precision. In addition to these benefits, we demonstrate an area-selective etching for maskless lithography as a new frontier of ALE. In this paper, area-selective etching refers to the confinement of etching into the specific areas of the substrate. The concept of area-selective etching originated during our studies on quasi-ALE of silicon nitride which consists of sequential exposure of silicon nitride to hydrogen and fluorinated plasma. The findings of our studies reported in this paper suggest that it may be possible to confine the etching into specific areas of silicon nitride without using any mask by replacing conventional hydrogen plasma with a localized source of hydrogen ions.

Year after year, the semiconductor industry overcomes a tremendous amount of technical challenges to satisfy Moore’s law. Through innovative device architectures, smart design, new integration and patterning concepts, better tools and new materials, the industry has successfully reached the 7nm technology node. Both design and patterning options are identified and the high volume manufacturing readiness is expected end of 2018. Today, the industry is preparing for the 5nm technology node (N5) while research centers start identifying and exploring the different patterning options for the 3nm technology node. The former targets a Metal 2 Pitch (M2P) of 32nm and a Contacted Poly Pitch (CPP) of 42nm while the latter aims for a M2P of 24nm and a CPP of 32nm. At such tight metal pitches and in view of the continuous progress in EUV tool performance, a single print EUV lithography is considered as a potential patterning option for N5 to pattern critical Back-End-Of-Line (BEOL) layers such as block, via and unidirectional metal lines. However, without the emergence of improved EUV photoresist (PR) platform that meets requirements for resolution, line edge roughness and sensitivity, we can expect a very limited available PR budget for pattern transfer (between 12nm and 30nm), an increase of defects such as bridging or line interruptions and finally a degradation of the sidewall roughness. These will contribute to the total CD variation and consume an important part of the overall Edge Placement Error (EPE) budget. Hence, actual patterning methods used to smooth and transfer down the PR pattern must be significantly improved and new solutions must be explored to enable the emergence of advanced technologies. In this work, we explore different post-lithography methods to overcome challenges related to EUV-based patterning at tight pitches. Both chemically amplified PR and metal-based PR are considered and the performance of the different approaches are evaluated step-by-step using top down SEM imaging, cross-section SEM and 3D-AFM. Finally, we complete the study showing Power Spectral Density (PSD) analysis that help to understand how the roughness is distributed in the frequency domain for the different studied methods.

In this work, we present our recent achievements on the integration and transfer etching of a novel silicon-containing high-χ block copolymer for lines/spaces applications. Developed carbo-silane BCPs are synthesized under industrial conditions and present periodicities as low as 14 nm. A full directed self-assembly by graphoepitaxy process is shown using standard photolithography stacks and all processes are performed on 300 mm wafer compatible tools. Specific plasma processes are developed to isolate perpendicular lamellae and sub-12 nm features are finally transferred into silicon substrates. The quality of the final BCP hard mask (CDU, LWR, LER) are also investigated. Finally, thanks to the development of dedicated neutral layers and top-coats allowing perpendicular orientations, it was possible to investigate plasma etching experiments on full-sheets at 7 nm resolution, opening the way to the integration of these polymers in chemoepitaxy stacks.

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region.

In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements.

Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

While the semiconductor industry is almost ready for high-volume manufacturing of the 7 nm technology node, research centers are defining and troubleshooting the patterning options for the 5 nm technology node (N5) and below. The target dimension for imec’s N5 BEOL applications is 20-24 nm Metal Pitch (MP), which requires Self-Aligned multiple (Double/Quadruple/Octuple) Patterning approaches (SAxP) in combination with EUV or immersion lithography at 193 nm. There are numerous technical challenges to enable gratings at the hard mask level such as good uniformity across wafer, low line edge/width roughness (LER/LWR), large process window, and all of this at low cost. An even greater challenge is to transfer these gratings into the dielectric material at such critical dimensions, where increased line edge roughness, line wiggling and even pattern collapse can be expected for materials with small mechanical stability such as highly porous low-k dielectrics. In this work we first compare three different patterning options for 12 nm half-pitch gratings at the hard mask level: EUV-based SADP and 193i-based SAQP and SAOP. This comparison will be based on process window, line edge/width roughness and cost. Next, the transfer of 12 nm line/space gratings in the dielectric material is discussed and presented. The LER of the dielectric lines is investigated as a function of the dielectric material, the trench depth, and the stress in the sacrificial hard mask. Finally, we elaborate on the different options to enable scaling down from 24 nm MP to 16 nm MP, and demonstrate 8 nm line/space gratings with 193i-based SAOP.

This paper discusses the approach and solution adopted by GLOBALFOUNDRIES, a high volume manufacturing (HVM) foundry, for dry-etch related edge-signature surface particle defects issue facing the sub-nm node in the gate-etch sector. It is one of the highest die killers for the company in the 14-nm node. We have used different approaches to attack and rectify the edge signature surface particle defect. Several process-related & hardware changes have been successively implemented to achieve defect reduction improvement by 63%. Each systematic process and/or hardware approach has its own unique downstream issues and they have been dealt in a route-cause-effect technique to address the issue.

Thermal atomic layer etching (ALE) is a thin film removal technique based on sequential, self-limiting surface reactions. ALE is the reverse of atomic layer deposition (ALD). This talk will discuss new thermal ALE procedures that have been developed recently for the thermal ALE of metal oxides, metal nitrides and elemental metals. Thermal ALE provides for atomic layer controlled and isotropic etching. Al2O3 ALE will be demonstrated using sequential fluorination and ligand-exchange reactions using HF and Al(CH3)3 as the reactants. TiN ALE will be presented using sequential reactions based on oxidation and fluorination to a volatile fluoride using O3 and HF as the reactants. W ALE will be illustrated using sequential oxidation, conversion to a different metal oxide and fluorination to a volatile fluoride. W ALE employs O3, BCl3 and HF as the reactants. Thermal ALE will be useful for the atomic layer processing required for advanced semiconductor manufacturing.

A two-dimensional, cellular automata model for atomic layer etching (ALE) is presented and used to predict the etch rate and the evolution of the roughness of various surfaces as a function of the efficiencies or probabilities of the adsorption and removal steps in the ALE process. The atoms of the material to be etched are initially placed in a two-dimensional array several layers thick. The etch follows the two step process of ALE. First, the initial reaction step (e.g., Cl reacting with Si) is assumed to occur at 100% efficiency activating the exposed, surface atoms; that is, all exposed atoms react with the etching gas. The second reaction step (e.g., Ar ion bombardment or sputtering) occurs with efficiencies that are assumed to vary depending on the exposure of the surface atoms relative to their neighbors and on the strength of bombardment. For sufficiently high bombardment or sputtering, atoms below the activated surface atoms can also be removed, which gives etch rates greater than one layer per ALE cycle. The bounds on the efficiencies of the second removal step are extracted from experimental measurements and fully detailed molecular dynamics simulations from the literature. A trade-off is observed between etch rate and surface roughness as the Ar ion bombardment is increased.

A selective, rapid thermal-cyclic atomic-level etching (ALE) of tungsten is developed. The first step of this process is exposing the surface of tungsten with hydrofluorocarbon plasma at −22°C to form a tungsten fluoride-based surface modified layer on the tungsten surface. The second step is rapid thermal annealing with infrared (IR) irradiation to remove the surface modified layer. Tungsten 4f peaks and a fluorine 1s peak, which were assigned to tungsten fluoride, were observed by in-situ x-ray photoelectron spectroscopy immediately after plasma exposure. The peaks that originated from tungsten fluoride disappeared after the samples were annealed. Cyclic etching tests were carried out by repeating plasma exposure and IR irradiation with a 300-mm ALE tool. Films of tungsten, TiN, and SiO₂ were used as sample materials. The amount of etched tungsten increased as the number of cycle repetitions increased. The etched amount per cycle for tungsten was 0.8 nm. In comparison, etching of TiN and SiO₂ was not detected. Conformal etching profiles of patterned samples after 60 cycles were obtained. Furthermore, the etched amount per cycle showed saturation behavior with regard to plasma exposure time. Selective, rapid thermal cyclic ALE of tungsten was thus successfully demonstrated.

Predicting the etch and deposition profiles created using plasma processes is challenging due to the complexity of plasma discharges and plasma-surface interactions. Volume-averaged global models allow for efficient prediction of important processing parameters and provide a means to quickly determine the effect of a variety of process inputs on the plasma discharge. However, global models are limited based on simplifying assumptions to describe the chemical reaction network. Here a database of 128 reactions is compiled and their corresponding rate constants collected from 24 sources for an Ar/CF₄ plasma using the platform RODEo (Recipe Optimization for Deposition and Etching). Six different reaction sets were tested which employed anywhere from 12 to all 128 reactions to evaluate the impact of the reaction database on particle species densities and electron temperature. Because many the reactions used in our database had conflicting rate constants as reported in literature, we also present a method to deal with those uncertainties when constructing the model which includes weighting each reaction rate and filtering outliers. By analyzing the link between a reaction’s rate constant and its impact on the predicted plasma densities and electron temperatures, we determine the conditions at which a reaction is deemed necessary to the plasma model. The results of this study provide a foundation for determining which minimal set of reactions must be included in the reaction set of the plasma model.

The thin nature of EUV (Extreme Ultraviolet) resist has posed significant challenges for etch processes. In particular, EUV patterning combined with conventional etch approaches suffers from loss of pattern fidelity in the form of line breaks. A typical conventional etch approach prevents the etch process from having sufficient resist margin to control the trench CD (Critical Dimension), minimize the LWR (Line Width Roughness), LER (Line Edge Roughness) and reduce the T2T (Tip-to-Tip). Pre-etch deposition increases the resist budget by adding additional material to the resist layer, thus enabling the etch process to explore a wider set of process parameters to achieve better pattern fidelity. Preliminary tests with pre-etch deposition resulted in blocked isolated trenches. In order to mitigate these effects, a cyclic deposition and etch technique is proposed. With optimization of deposition and etch cycle time as well as total number of cycles, it is possible to open the underlying layers with a beneficial over etch and simultaneously keep the isolated trenches open. This study compares the impact of no pre-etch deposition, one time deposition and cyclic deposition/etch techniques on 4 aspects: resist budget, isolated trench open, LWR/LER and T2T.

We report a sub-30nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology (SAB) targeting the back end of line (BEOL) metal line patterning applications for logic nodes beyond 5nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193nm immersion SADP targeting a 40nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, Spin on carbon, spin on glass). The multi-color integration approach is successfully demonstrated and provides a valuable method to address overlay concerns and more generally edge placement error (EPE) as a whole for advanced process nodes. Unbiased LER/LWR analysis comparison between EUV SADP and 193nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open and dielectric etch compared to 193nm immersion SADP, the final process performance is matched in terms of LWR (1.08nm 3 sigma unbiased) and is only 6% higher than 193nm immersion SADP for average unbiased LER. Using EUV SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged, and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges.

The semiconductor industry has been pushing the limits of scalability by combining 193nm immersion lithography with multi-patterning techniques for several years. Those integrations have been declined in a wide variety of options to lower their cost but retain their inherent variability and process complexity. EUV lithography offers a much desired path that allows for direct print of line and space at 36nm pitch and below and effectively addresses issues like cycle time, intra-level overlay and mask count costs associated with multi-patterning. However it also brings its own sets of challenges. One of the major barrier to high volume manufacturing implementation has been hitting the 250W power exposure required for adequate throughput [1]. Enabling patterning using a lower dose resist could help move us closer to the HVM throughput targets assuming required performance for roughness and pattern transfer can be met.

As plasma etching is known to reduce line edge roughness on 193nm lithography printed features [2], we investigate in this paper the level of roughness that can be achieved on EUV photoresist exposed at a lower dose through etch process optimization into a typical back end of line film stack. We will study 16nm lines printed at 32 and 34nm pitch. MOX and CAR photoresist performance will be compared. We will review step by step etch chemistry development to reach adequate selectivity and roughness reduction to successfully pattern the target layer.

The need for forming gratings (for example used in VR headsets) in materials such as SiO₂ has seen a recent surge in the use of Ion beam etching techniques. However, when using an argon-only beam, the selectivity is limited as it is a physical process.

Typically, gases such as CHF₃, SF₆, O₂ and Cl₂ can be added to argon in order to increase selectivity; depending on where the gas is injected, the process is known as Reactive Ion Beam Etching (RIBE) or Chemically Assisted Ion Beam Etching (CAIBE). The substrate holder can rotate in order to provide an axisymmetric etch rate profile. It can also be tilted over a range of angles to the beam direction. This enables control over the sidewall profile as well as radial uniformity optimisation. Ion beam directionality in conjunction with variable incident beam angle via platen angle setting enables profile control and feature shaping during nanopatterning. These hardware features unique to the Ion Beam etching methods can be used to create angled etch features. The CAIBE technique is also well suited to laser diode facet etch (for optoelectronic devices); these typically use III-V materials like InP.

Here, we report on materials such as SiO₂ etched without rotation and at a fixed platen angle allowing the formation of gratings and InP etched at a fixed angle with rotation allowing the formation of nanopillars and laser facets.

No single lithography technology can create <24nm pitch patterns in a single pass except for direct-write e-beam which is too slow and expensive for HVM. Various complex multi-patterning process flows can be compared by Cost Per Wafer Pass (CPWP), a term defined as the cost-of-ownership (CoO) with all yield losses set to zero in high volume manufacturing (HVM). CPWP modeling allows for the evaluation of alternate 1D and 2D patterning paths, including EUV LE2, EUV SADP, ArFi LE4, ArFi SAQP + EUV cut-mask, and ArFi SADP + DSA + ArFi block-mask. Similar CPWP for ArFi- and EUV-based flows favor the latter due to reduced yield losses and manufacturing times.

Directed self-assembly (DSA) of block copolymers (BCPs) is one of the most promising patterning technologies for future lithography nodes. However, one of the biggest challenges to DSA is the pattern transfer by plasma etching from BCP to hardmask (HM) because the etch selectivity between BCP and neutral brush layer underneath is usually not high enough to enable robust pattern transfer. This paper will explore the plasma etch conditions of both BCPs and neutral brush layers that may improve selectivity and allow a more robust pattern transfer of DSA patterns into the hardmask layer. The plasma etching parameters that are under investigation include the selection of oxidative or reductive etch chemistries, as well as plasma gas pressure, power, and gas mixture fractions. Investigation into the relationship between BCP/neutral brush layer materials with varying chemical compositions and the plasma etching conditions will be highlighted. The culmination of this work will demonstrate important etch parameters that allow BCPs and neutral brush layers to be etched into the underlying hardmask layer with a large process window.

In integrated circuit and memory devices, size shrinkage has been the most effective method to reduce production cost and enable the steady increment of the number of transistors per unit area over the past few decades. In order to reduce the die size and feature size, it is necessary to minimize pattern formation in the advance node development. In the node of sub-10nm, extreme ultra violet lithography (EUV) and multi-patterning solutions based on 193nm immersionlithography are the two most common options to achieve the size requirement. In such small features of line and space pattern, line width roughness (LWR) and line edge roughness (LER) contribute significant amount of process variation that impacts both physical and electrical performances.

In this paper, we focus on optimizing the line roughness performance by using wafer stress engineering on 30nm pitch line and space pattern. This pattern is generated by a self-aligned quadruple patterning (SAQP) technique for the potential application of fin formation. Our investigation starts by comparing film materials and stress levels in various processing steps and material selection on SAQP integration scheme. From the cross-matrix comparison, we are able to determine the best stack of film selection and stress combination in order to achieve the lowest line roughness performance while obtaining pattern validity after fin etch. This stack is also used to study the step-by-step line roughness performance from SAQP to fin etch. Finally, we will show a successful patterning of 30nm pitch line and space pattern SAQP scheme with 1nm line roughness performance.

Directed self-assembly (DSA) of block copolymers (BCP) is a promising alternative technology to overcome the limits of patterning for the semiconductor industry. DSA exploits the self-assembling property of BCPs for nano-scale manufacturing and to repair defects in patterns created during photolithography. After self-assembly of BCPs, to transfer the created pattern to the underlying substrate, selective etching of PMMA (poly (methyl methacrylate)) to PS (polystyrene) is required. However, the etch process to transfer the self-assemble “fingerprint” DSA patterns to the underlying layer is still a challenge. Using combined experimental and modelling studies increases understanding of plasma interaction with BCP materials during the etch process and supports the development of selective process that form well-defined patterns. In this paper, a simple model based on a generic surface model has been developed and an investigation to understand the etch behavior of PS-b-PMMA for Ar, and Ar/O2 plasma chemistries has been conducted. The implemented model is calibrated for etch rates and etch profiles with literature data to extract parameters and conduct simulations. In order to understand the effect of the plasma on the block copolymers, first the etch model was calibrated for polystyrene (PS) and poly (methyl methacrylate) (PMMA) homopolymers. After calibration of the model with the homopolymers etch rate, a full Monte-Carlo simulation was conducted and simulation results are compared with the critical-dimension (CD) and selectivity of etch profile measurement. In addition, etch simulations for lamellae pattern have been demonstrated, using the implemented model.

The aim of this paper is to investigate the role of etch transfer in two challenges of LER metrology raised by recent evolutions in lithography: the effects of SEM noise and the cross-line and edge correlations.

The first comes from the ongoing scaling down of linewidths, which dictates SEM imaging with less scanning frames to reduce specimen damage and hence with more noise. During the last decade, it has been shown that image noise can be an important budget of the measured LER while systematically affects and alter the PSD curve of LER at high frequencies. A recent method for unbiased LER measurement is based on the systematic Fourier or correlation analysis to decompose the effects of noise from true LER (Fourier-Correlation filtering method). The success of the method depends on the PSD and HHCF curve. Previous experimental and model works have revealed that etch transfer affects the PSD of LER reducing its high frequency values. In this work, we estimate the noise contribution to the biased LER through PSD flat floor at high frequencies and relate it with the differences between the PSDs of lithography and etched LER. Based on this comparison, we propose an improvement of the PSD/HHCF-based method for noise-free LER measurement to include the missed high frequency real LER.

The second issue is related with the increased density of lithographic patterns and the special characteristics of DSA and MP lithography patterns exhibits. In a previous work, we presented an enlarged LER characterization methodology for such patterns, which includes updated versions of the old metrics along with new metrics defined and developed to capture cross-edge and cross-line correlations. The fundamental concept has been the Line Center Roughness (LCR), the edge c-factor and the line c-factor correlation function and length quantifying the line fluctuations and the extent of cross-edge and cross-line correlations. In this work, we focus on the role of etch steps on cross-edge and line correlation metrics in SAQP data. We find that the spacer etch steps reduce edge correlations while etch steps with pattern transfer increase these. Furthermore, the density doubling and quadrupling increase edge correlations as well as cross-line correlations.