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Design-Process-Technology Co-optimization for Manufacturability IX
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Volume Details

Volume Number: 9427
Date Published: 21 April 2015

Table of Contents
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Front Matter: Volume 9427
Author(s): Proceedings of SPIE
The daunting complexity of scaling to 7NM without EUV: pushing DTCO to the extreme
Author(s): Lars Liebmann; Albert Chu; Paul Gutwin
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High coverage of litho hotspot detection by weak pattern scoring
Author(s): Jinho Park; NamJae Kim; Jae-hyun Kang; Seung Weon Paek; Steve Kwon; Marwah Shafee; Kareem Madkour; Wael ElManhawy; Joe Kwan; Jean-Marie Brunet
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A pattern-based methodology for optimizing stitches in double-patterning technology
Author(s): Lynn T.-N. Wang; Sriram Madhavan; Vito Dai; Luigi Capodieci
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Fast detection of manufacturing systematic design pattern failures causing device yield loss
Author(s): Jean-Christophe Le Denmat; Nelly Feldman; Olivia Riewer; Emek Yesilada; Michel Vallet; Christophe Suzor; Salvatore Talluto
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Topology and context-based pattern extraction using line-segment Voronoi diagram
Author(s): Sandeep Kumar Dey; Panagiotis Cheilaris; Nathalie Casati; Maria Gabrani; Evanthia Papadopoulo
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A systematic framework for evaluating standard cell middle-of-line (MOL) robustness for multiple patterning
Author(s): Xiaoqing Xu; Brian Cline; Greg Yeric; Bei Yu; David Z. Pan
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Self-aligned quadruple patterning-compliant placement
Author(s): Fumiharu Nakajima; Chikaaki Kodama; Koichi Nakayama; Shigeki Nojima; Toshiya Kotani
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Impact of a SADP flow on the design and process for N10/N7 metal layers
Author(s): W. Gillijns; S. M. Y. Sherazi; D. Trivkovic; B. Chava; B. Vandewalle; V. Gerousis; P. Raghavan; J. Ryckaert; K. Mercha; D. Verkest; G. McIntyre; K. Ronse
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An efficient auto TPT stitch guidance generation for optimized standard cell design
Author(s): Nagaraj Chary Samboju; Soo-Han Choi; Srini Arikati; Erdem Cilingir
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Yield-aware mask assignment using positive semi-definite relaxation in LELECUT triple patterning
Author(s): Yukihide Kohira; Chikaaki Kodama; Tomomi Matsui; Atsushi Takahashi; Shigeki Nojima; Satoshi Tanaka
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DTCO at N7 and beyond: patterning and electrical compromises and opportunities
Author(s): Julien Ryckaert; Praveen Raghavan; Pieter Schuddinck; Huynh Bao Trong; Arindam Mallik; Sushil S. Sakhare; Bharani Chava; Yasser Sherazi; Philippe Leray; Abdelkarim Mercha; Jürgen Bömmels; Gregory R. McIntyre; Kurt G. Ronse; Aaron Thean; Zsolt Tökei; An Steegen; Diederik Verkest
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Layout optimization with assist features placement by model based rule tables for 2x node random contact
Author(s): Jinhyuck Jun; Minwoo Park; Chanha Park; Hyunjo Yang; Donggyu Yim; Munhoe Do; Dongchan Lee; Taehoon Kim; Junghoe Choi; Gerard Luk-Pat; Alex Miloslavsky
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Standard cell design in N7: EUV vs. immersion
Author(s): Bharani Chava; David Rio; Yasser Sherazi; Darko Trivkovic; Werner Gillijns; Peter Debacker; Praveen Raghavan; Ahmad Elsaid; Mircea Dusa; Abdelkarim Mercha; Julien Ryckaert; Diederik Verkest
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Layout dependent effects analysis on 28nm process
Author(s): Helen Li; Mealie Zhang; Waisum Wong; Huiyuan Song; Wei Xu; Philippe Hurat; Hua Ding; Yifan Zhang; Michel Cote; Jason Huang; Ya-ch Lai
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Breaking through 1D layout limitations and regaining 2D design freedom Part I: 2D layout decomposition and stitching techniques for hybrid optical and self-aligned multiple patterning
Author(s): Hongyi Liu; Jun Zhou; Yijian Chen
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Full chip two-layer CD and overlay process window analysis
Author(s): Rachit Gupta; Shumay Shang; John Sturtevant
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Quantitative evaluation of manufacturability and performance for ILT produced mask shapes using a single-objective function
Author(s): Heon Choi; Wei-long Wang; Chidam Kallingal
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Akaike information criterion to select well-fit resist models
Author(s): Andrew Burbine; David Fryer; John Sturtevant
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Fast source optimization by clustering algorithm based on lithography properties
Author(s): Masashi Tawada; Takaki Hashimoto; Keishi Sakanushi; Shigeki Nojima; Toshiya Kotani; Masao Yanagisawa; Nozomu Togawa
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Statistical modeling of SRAM yield performance and circuit variability
Author(s): Qi Cheng; Yijian Chen
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Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node
Author(s): Sushil Sakhare; Darko Trivkovic; Tom Mountsier; Min-Soo Kim; Dan Mocuta; Julien Ryckaert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; Mircea Dusa
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Incorporating DSA in multipatterning semiconductor manufacturing technologies
Author(s): Yasmine Badr; J. Andres Torres; Yuansheng Ma; Joydeep Mitra; Puneet Gupta
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Design layout analysis and DFM optimization using topological patterns
Author(s): Ji Xu; Karthik N. Krishnamoorthy; Edward Teoh; Vito Dai; Luigi Capodieci; Jason Sweis; Ya-Chieh Lai
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Automation for pattern library creation and in-design optimization
Author(s): Rock Deng; Elain Zou; Sid Hong; Jinyan Wang; Yifan Zhang; Jason Sweis; Ya-Chieh Lai; Hua Ding; Jason Huang
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A new lithography hotspot detection framework based on AdaBoost classifier and simplified feature extraction
Author(s): Tetsuaki Matsunawa; Jhih-Rong Gao; Bei Yu; David Z. Pan
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A methodology to optimize design pattern context size for higher sensitivity to hotspot detection using pattern association tree (PAT)
Author(s): Shikha Somani; Piyush Pathak; Piyush Verma; Sriram Madhavan; Luigi Capodieci
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20nm CMP model calibration with optimized metrology data and CMP model applications
Author(s): Ushasree Katakamsetty; Dinesh Koli; Sky Yeo; Colin Hui; Ruben G. Ghulghazaryan; Burak Aytuna; Jeff Wilson
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Topography aware DFM rule based scoring for silicon yield modeling
Author(s): Vikas Tripathi; Ushasree Katakamsetty; Sky Yeo; Colin Hui
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A compact model to predict pillar-edge-roughness effects on 3D vertical nanowire MOSFETs using the perturbation method
Author(s): Pu Wang; Chuyang Hong; Qi Cheng; Yijian Chen
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Efficient etch bias compensation techniques for accurate on-wafer patterning
Author(s): Mohamed Salama; Ayman Hamouda
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An efficient lithographic hotspot severity analysis methodology using Calibre PATTERN MATCHING and DRC application
Author(s): ZeXi Deng; ChunShan Du; Lin Hong; LiGuo Zhang; JinYan Wang
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A holistic methodology to drive process window entitlement and its application to 20nm logic
Author(s): Lalit Shokeen; Ayman Hamouda; Mark Terry; Dan J. Dechene; Stephen Hsu; Michael Crouse; Pengcheng Li; Keith Gronlund; Gary Zhang
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Practical DTCO through design/patterning exploration
Author(s): Neal Lafferty; Jason Meiring; Mohamed Bahnas; Joseph O'Neill; Toshikazu Endo; Dan Schumacher; James Culp; Glenn Wawrzynski; Gurpreet Singh Lamba; Kostas Adam; John Sturtevant; Chris McGinty
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Comparison of OPC job prioritization schemes to generate data for mask manufacturing
Author(s): Travis Lewis; Vijay Veeraraghavan; Kenneth Jantzen; Stephen Kim; Minyoung Park; Gordon Russell; Mark Simmons
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VLSI physical design analyzer: A profiling and data mining tool
Author(s): Shikha Somani; Piyush Verma; Sriram Madhavan; Fadi Batarseh; Robert C. Pack; Luigi Capodieci
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The cell pattern correction through design-based metrology
Author(s): Yonghyeon Kim; Kweonjae Lee; Jinman Chang; Taeheon Kim; Daehan Han; Kyusun Lee; Aeran Hong; Jinyoung Kang; Bumjin Choi; Joosung Lee; Kyehee Yeom; Jooyoung Lee; Hyeongsun Hong; Kyupil Lee; Gyoyoung Jin
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Breaking through 1D layout limitations and regaining 2D design freedom part II: stitching yield modeling and optimization
Author(s): Jun Zhou; Hongyi Liu; Ting Han; Yijian Chen
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Automatic DFM methodology for bit line pattern dummy
Author(s): Mohamed Bahr
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