This PDF file contains the front matter associated with SPIE Proceedings Volume 9424 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

Power Spectral Density (PSD) analysis is an important part of understanding line-edge and linewidth roughness in lithography. But uncertainty in the measured PSD, both random and systematic, complicates interpretation. It is essential to understand and quantify the sources of measured PSD uncertainty and to develop mitigation strategies. In this work, both analytical derivations and simulations of rough features are used to evaluate data window functions for reducing spectral leakage, and to understand the impact of data detrending on biases in PSD and autocovariance function measurement. The Welch window was found to be best among the windows tested. Linear detrending for line-edge roughness measurement results in underestimation of the low-frequency PSD. Measuring multiple edges per measured SEM image reduces this bias.

A frequency domain 3 sigma LER characterization methodology combining the standard deviation and power spectral density (PSD) methods is proposed. In the new method, the standard deviation is calculated in the frequency domain instead of the spatial domain as in the conventional method. The power spectrum of the LER is divided into three regions: low frequency (LF), middle frequency (MF) and high frequency (HF) regions. The frequency region definition is based on process visual comparisons. Three standard deviation numbers are used to characterize the LER in the three frequency regions. Pattern wiggling can be detected quantitatively with a wiggling factor which is also proposed in this paper.

We have investigated in a numerical study the determination of sidewall roughness (SWR) from top down scanning electron microscopy (SEM) images. In a typical metrology application, top-down SEM images are acquired in a (critical-dimension) SEM and the roughness is analyzed. However, the true size, shape and roughness characteristics of resist features are not fully investigated in the analysis of top-down SEM images. In reality, rough resist features are complex three-dimensional structures and the characterization naturally extends to the analysis of SWR. In this study we randomly generate images of rough lines and spaces, where the lines are made of PMMA on a silicon substrate. The lines that we study have a length of 2 µm, a width of 32nm and a height of 32 nm. The SWR is modeled by using the power spectral density (PSD) function of Palasantzas, which characterizes roughness by the standard deviation σ, correlation length ξ and roughness exponent α . The actual roughness is generated by application of the method of Thorsos in two dimensions. The images are constructed by using a home-built program for simulating electron-specimen interactions. The program that we have developed is optimized for complex arbitrary geometries and large number of incident low energy primary electrons by using multi-core CPUs and GPUs. The program uses the dielectric function model for inelastic scattering events and has an implementation specifically for low energy electrons. A satisfactory comparison is made between the secondary electron yields from the home-built program and another program found in literature. In order to reduce the risk of shrinkage, we use a beam energy of 300 eV and a spot size of 3 nm. Each pixel is exposed with 20 electrons on average (≈ 276 µC/cm²), following the Poisson distribution to account for illumination shot noise. We have assumed that the detection of electrons is perfect and does not introduce additional noise. We measure line edge roughness (LER) in simulated top-down SEM images of randomly generated rough lines by using PSD analysis. The measurements are then compared to the actual SWR that was used to generate the rough lines. We conclude that the bias in the determination of SWR is a non-linear function of the correlation length ξ3D of the actual SWR. The measured correlation length ξ 2D shows a linear trend with the correlation length ξ 3D of the SWR. From another simulation run, we conclude that the relation between measured LER in the top-down image and the standard deviation ξ 3D of the SWR is linearly biased. We see that the amount of bias relates to the correlation length ξ 3D of the SWR: The bias in the determination of SWR from top-down images increases for decreasing correlation length ξ 3D of the actual SWR. The results of this study, with respect to the metrology of rough resist features, touches upon the reliability and comparability of roughness characterization in top-down images.

A novel method of sub-nanometer uncertainty for the line profile measurement using TEM (Transmission Electron Microscope) images is proposed to calibrate CD-SEM (Critical Dimension Scanning Electron Microscope) line width measurement and to standardize line profile measurement through reference metrology. The proposed method has been validated for profile of Si line and photoresist features in our previous investigations. In this article, we apply the methodology to line profile measurements of advanced-FinFET (Fin-shaped Field-Effect Transistor) features. The FinFET features are sliced as thin specimens of 100 nm thickness by FIB (Focused Ion Beam) micro sampling system. Cross-sectional images of the specimens are obtained then by TEM. The profiles of fin, hardmask and dummy gate of FinFET features are evaluated using TEM images. The width of fin, the length of hardmask, and the length of dummy gate of FinFET features are measured and compared to CD-SEM measurement. The TEM results will be used to implement CD-SEM and CD-AFM reference metrology.

For Gate-all-around (GAA) MOSFETs the nanowires are suspended between source and drain anchors allowing conformal deposition of the gate around (i.e., GAASiNW) the silicon nanowire channel. 3DSEM measurement show that silicon wires tend to buckle between the source and drain anchors as function of their diameter and length. This phenomenon can impact device performance and therefore needs to be characterized. Resent metrology research performed on Silicon nanowires fabricated over a Boron Nitride (BN) layer demonstrated that Silicon nanowires spatial orientation is influenced by local electrostatic charge induced by the SEM electron beam irradiation. The scanning electron beam leads to charging of the floating conductive silicon wires and dielectric BN layer. Difference in charging mechanisms of the two materials lead to the formation of Coulomb forces acting between the wires and the BN layer.

We were able to change the spatial orientation of Silicon nanowires by modifying scanning conditions which effectively controls the amount of charging induced by the SEM. Strong charging, which corresponds to high dose leads to change of silicon wires spatial orientation, they appear straight in SEM top view and tilt image planes. Reducing charging by the means of scan rate increase or lower number of scanned frames saves the silicon wires buckled in their natural state.

Overlay metrology accuracy is a major concern for our industry. Advanced logic process require more tighter overlay control for multipatterning schemes. TIS (Tool Induced Shift) and WIS (Wafer Induced Shift) are the main issues for IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). Methods of compensation have been introduced, some are even very efficient to reduce these measured offsets. Another related question is about the overlay target designs. These targets are never fully representative of the design rules, strong efforts have been achieved, but the device cannot be completely duplicated. Ideally, we would like to measure in the device itself to verify the real overlay value. Top down CDSEM can measure critical dimensions of any structure, it is not dependent of specific target design. It can also measure the overlay errors but only in specific cases like LELE (Litho Etch Litho Etch) after final patterning. In this paper, we will revisit the capability of the CDSEM at final patterning by measuring overlay in dedicated targets as well as inside a logic and an SRAM design. In the dedicated overlay targets, we study the measurement differences between design rules gratings and relaxed pitch gratings. These relaxed pitch which are usually used in IBO or DBO targets. Beyond this “simple” LELE case, we will explore the capability of the CDSEM to measure overlay even if not at final patterning, at litho level. We will assess the hybridization of DBO and CDSEM for reference to optical tools after final patterning.

We will show that these reference data can be used to validate the DBO overlay results (correctables and residual fingerprints).

Most fabrication facilities today use imaging overlay measurement methods, as it has been the industry’s reliable workhorse for decades. In the last few years, third-generation Scatterometry Overlay (SCOL™) or Diffraction Based Overlay (DBO-1) technology was developed, along another DBO technology (DBO-2). This development led to the question of where the DBO technology should be implemented for overlay measurements. Scatterometry has been adopted for high volume production in only few cases, always with imaging as a backup, but scatterometry overlay is considered by many as the technology of the future. In this paper we compare imaging overlay and DBO technologies by means of measurements and simulations. We outline issues and sensitivities for both technologies, providing guidelines for the best implementation of each. For several of the presented cases, data from two different DBO technologies are compared as well, the first with Pupil data access (DBO-1) and the other without pupil data access (DBO-2). Key indicators of overlay measurement quality include: layer coverage, accuracy, TMU, process robustness and robustness to process changes. Measurement data from real cases across the industry are compared and the conclusions are also backed by simulations. Accuracy is benchmarked with reference OVL, and self-consistency, showing good results for Imaging and DBO-1 technology. Process sensitivity and metrology robustness are mostly simulated with MTD (Metrology Target Designer) comparing the same process variations for both technologies. The experimental data presented in this study was done on ten advanced node layers and three production node layers, for all phases of the IC fabrication process (FEOL, MEOL and BEOL). The metrology tool used for most of the study is KLA-Tencor’s Archer 500LCM system (scatterometry-based and imaging-based measurement technologies on the same tool) another type of tool is used for DBO-2 measurements.

Finally, we conclude that both imaging overlay technology and DBO-1 technology are fully successful and have a valid roadmap for the next few design nodes, with some use cases better suited for one or the other measurement technologies. Having both imaging and DBO technology options available in parallel, allows Overlay Engineers a mix and match overlay measurement strategy, providing back up when encountering difficulties with one of the technologies and benefiting from the best of both technologies for every use case.

Patterning process control of advanced nodes has required major changes over the last few years. Process control needs of critical patterning levels since 28nm technology node is extremely aggressive showing that metrology accuracy/sensitivity must be finely tuned.

The introduction of pitch splitting (Litho-Etch-Litho-Etch) at 14FDSOInm node requires the development of specific metrologies to adopt advanced process control (for CD, overlay and focus corrections). The pitch splitting process leads to final line CD uniformities that are a combination of the CD uniformities of the two exposures, while the space CD uniformities are depending on both CD and OVL variability.

In this paper, investigations of CD and OVL process control of 64nm minimum pitch at Metal1 level of 14FDSOI technology, within the double patterning process flow (Litho, hard mask etch, line etch) are presented.

Various measurements with SEMCD tools (Hitachi), and overlay tools (KT for Image Based Overlay – IBO, and ASML for Diffraction Based Overlay – DBO) are compared. Metrology targets are embedded within a block instanced several times within the field to perform intra-field process variations characterizations.

Specific SEMCD targets were designed for independent measurement of both line CD (A and B) and space CD (A to B and B to A) for each exposure within a single measurement during the DP flow.

Based on those measurements correlation between overlay determined with SEMCD and with standard overlay tools can be evaluated.

Such correlation at different steps through the DP flow is investigated regarding the metrology type. Process correction models are evaluated with respect to the measurement type and the intra-field sampling.

In the current paper we are addressing three questions relevant for accuracy: 1. Which target design has the best performance and depicts the behavior of the actual device? 2. Which metrology signal characteristics could help to distinguish between the target asymmetry related overlay shift and the real process related shift? 3. How does uncompensated asymmetry of the reference layer target, generated during after-litho processes, affect the propagation of overlay error through different layers? We are presenting the correlation between simulation data based on the optical properties of the measured stack and KLA-Tencor’s Archer overlay measurements on a 28nm product through several critical layers for those accuracy aspects.

Overlay in lithography becomes much more challenging due to the shrink of device node and multi-patterning approach. Consequently, the specification of overlay becomes tighter, and more complicated overlay control methods like high order or field-by-field control become mandatory. In addition, the tight overlay specification starts to raise another fundamental question: accuracy. Overlay inaccuracy is dominated by two main components: one is measurement quality and the other is representing device overlay. The latter is because overlay is being measured on overlay targets, not on the real device structures. We investigated the following for accurate overlay measurement: optimal target design by simulation; optimal recipe selection using the index of measurement quality; and, the correlation with device pattern’s overlay.

Simulation was done for an advanced memory stack for optimal overlay target design which provides robustness for the process variation and sufficient signal for the stack. Robustness factor and sufficient signal factor sometimes contradicting each other, therefore there is trade-off between these two factors. Simulation helped to find the design to meet the requirement of both factors. The investigation involves also recipe optimization which decides the measurement conditions like wavelength. KLA-Tencor also introduced a new index which help to find an accurate measurement condition. In this investigation, we used CD-SEM to measure the overlay of device pattern after etch or decap process to check the correlation between the overlay of overlay mark and the overlay of device pattern.

Computational metrology target design requires both an accurate metrology simulation engine and an accurate geometric model. This paper deals with the later. Optical critical dimension metrology and cross-section SEM are demonstrated as two useful methods of geometric model verification with differing capabilities. Specifically, a methodology is proposed which allows the metrology engineer to quantify the level of accuracy required by the model as a function of the tolerable uncertainty in the prediction of metrology performance metrics. The methodology identifies a subset of model parameters which need to be verified enabling the metrology engineer to invest the minimum effort in stack and topography verification which will lead to performing target designs on the first design round.

Overlay metrology tool suppliers are offering today several options to their customers: Different hardware (Image Based Overlay or Diffraction Based Overlay), different target designs (with or without segmentation) or different target sizes (from 5 um to 30 um). All these variations are proposed to resolve issues like robustness of the target towards process variations, be more representative of the design or increase the density of measurements.

In the frame of the development of a triple patterning BEOL scheme of 10 nm node layer, we compare IBO targets (standard AIM, AIMid and multilayer AIMid). The metrology tools used for the study are KLA-Tencor’s nextgeneration Archer 500 system (scatterometry- and imaging-based measurement technologies on the same tool).

The overlay response and fingerprint of these targets will be compared using a very dense sampling (up to 51 pts per field). The benefit of indie measurements compared to the traditional scribes is discussed. The contribution of process effects to overlay values are compared to the contribution of the performance of the target. Different targets are combined in one measurement set to benefit from their different strengths (performance vs size).

The results are summarized and possible strategies for a triple patterning schemes are proposed.

Critical dimension scanning electron microscope (CD-SEM) metrology has long used empirical approaches to determine edge locations. While such solutions are very flexible, physics-based models offer the potential for improved accuracy and precision for specific applications. Here, Monte Carlo simulation is used to generate theoretical linescans from single step and line/space targets in order to build a physics-based analytical model. The resulting analytical model fits the Monte Carlo simulation results for different feature heights, widths, and pitches. While more work is required to further develop this scheme, this model is a candidate for a new class of improved edge detection algorithms for CD-SEMs.

Traditional metrology solutions are facing a range of challenges at the 1X node such as three dimensional (3D) measurement capabilities, shrinking overlay and critical dimension (CD) error budgets driven by multi-patterning and via in trench CD measurements. Hybrid metrology offers promising new capabilities to address some of these challenges but it will take some time before fully realized. This paper explores new capabilities currently offered on the in-line Critical Dimension Scanning Electron Microscope (CD-SEM) to address these challenges and enable the CD-SEM to move beyond measuring bottom CD using top down imaging.

Device performance is strongly correlated with Fin geometry causing an urgent need for 3D measurements. New beam tilting capabilities enhance the ability to make 3D measurements in the front-end-of-line (FEOL) of the metal gate FinFET process in manufacturing. We explore these new capabilities for measuring Fin height and build upon the work communicated last year at SPIE¹. Furthermore, we extend the application of the tilt beam to the back-end-of-line (BEOL) trench depth measurement and demonstrate its capability in production targeting replacement of the existing Atomic Force Microscope (AFM) measurements by including the height measurement in the existing CDSEM recipe to reduce fab cycle time.

In the BEOL, another increasingly challenging measurement for the traditional CD-SEM is the bottom CD of the self-aligned via (SAV) in a trench first via last (TFVL) process. Due to the extremely high aspect ratio of the structure secondary electron (SE) collection from the via bottom is significantly reduced requiring the use of backscatter electrons (BSE) to increase the relevant image quality. Even with this solution, the resulting images are difficult to measure with advanced technology nodes. We explore new methods to increase measurement robustness and combine this with novel segmentation-based measurement algorithm generated specifically for BSE images. The results will be contrasted with data from previously used methods to quantify the improvement. We also compare the results to electrical test data to evaluate and quantify the measurement performance improvements.

Lastly, according to International Technology Roadmap for Semiconductors (ITRS) from 2013, the overlay 3 sigma requirement will be 3.3 nm in 2015 and 2.9 nm in 2016. Advanced lithography requires overlay measurement in die on features resembling the device geometry. However, current optical overlay measurement is performed in the scribe line on large targets due to optical diffraction limit. In some cases, this limits the usefulness of the measurement since it does not represent the true behavior of the device. We explore using high voltage imaging to help address this urgent need. Novel CD-SEM based overlay targets that optimize the restrictions of process geometry and SEM technique were designed and spread out across the die. Measurements are done on these new targets both after photolithography and etch. Correlation is drawn between the two measurements. These results will also be compared to conventional optical overlay measurement approaches and we will discuss the possibility of using this capability in high volume manufacturing.

A novel methodology was established for determining critical dimension scanning electron microscope (CD-SEM) optimum measurement condition of sub-20 nm resist patterns for 0.33NA EUV lithography yielding both small shrinkage and high precision. To investigate dependency of resist shrinkage on pattern size and electron beam irradiation condition, shrinkage of 18, 32, and 45 nm EUV resist patterns was measured over a wide range of beam conditions. A shrinkage trend similar to that of ArF resist patterns was observed for 32 and 45 nm, but 18 nm pattern showed a different dependence on acceleration voltage. Conventional methodology developed for ArF resist pattern to predict shrinkage and precision using the Taguchi method was applied to EUV resist pattern to examine the extendibility of the method. Predicted shrinkage by Taguchi method for 32 and 45 nm patterns agreed with measurements. However, the prediction error increases considerably as the pattern size decreases from 32 to 18 nm because there is a significant interaction between acceleration voltage and irradiated electron dose in L18 array used in the Taguchi method. Thus, we proposed a new method that consists of separated prediction procedures of shrinkage and precision using both a shrinkage curve and the Taguchi method, respectively. The new method was applied to 18 nm EUV resist pattern, and the optimum measurement condition with shrinkage of 1.5 nm and precision of 0.12 nm was determined. Our new method is a versatile technique which is applicable not only to fine EUV resist pattern but also to ArF resist pattern.

Simulating SEM images is important in order to optimize SEM subsystems and the setup of the SEM for specific tasks, such as new devices and fabrication methods, as well as to complete simulation flows in lithography and nanofabrication. Monte Carlo simulators have been used for these purposes, but their disadvantage is the low speed of simulation. A fast analytic simulator of SEM images, ASEM, is presented in this paper, which takes into account the most important factors in SEM: electron scattering in 3D samples composed of various materials, electrical fields, the properties and geometry of detectors, and charging. This allows for a simulation accuracy approaching that of Monte Carlo, while the simulation time is on the scale of one minute. Examples of simulations and their comparison to actual experiments are presented with various detectors, samples, electrical fields and charging, including the contrast reversal effect due to charging. Simulations of SEM images using resist profiles exported from a lithography simulator are also presented.

SEMATECH has initiated a program to develop massively-parallel electron beam defect inspection (MPEBI). Here we use JMONSEL simulations to generate expected imaging responses of chosen test cases of patterns and defects with ability to vary parameters for beam energy, spot size, pixel size, and/or defect material and form factor. The patterns are representative of the design rules for an aggressively-scaled FinFET-type design. With these simulated images and resulting shot noise, a signal-to-noise framework is developed, which relates to defect detection probabilities. Additionally, with this infrastructure the effect of detection chain noise and frequency dependent system response can be made, allowing for targeting of best recipe parameters for MPEBI validation experiments, ultimately leading to insights into how such parameters will impact MPEBI tool design, including necessary doses for defect detection and estimations of scanning speeds for achieving high throughput for HVM.

A Monte Carlo electron scattering simulation tool that can create SEM images of 3D features with arbitrary geometry has been developed. This is combined with both a stochastic resist model and synthetic 3D features to probe the effect of the effect of roughness on SEM measurements. Sidewall roughness makes it difficult to precisely identify the true feature width of a line because the roughness increases the SEM signal non-proportionally to the amount of material with which it is interacting. LER generally under predicts sidewall surface roughness because the SEM has an averaging effect as the electron beam interacts with a volume of material. LER becomes a better measure of surface roughness as the correlation length of the surface roughness increases. Decreasing film thickness causes a decrease in the linewidth and increase in LER measured by SEM, especially for features 35 nm thick and below. This occurs even if the true 3D feature width and roughness is approximately constant, meaning that the apparent change in linewidth and LER is a metrology effect. Threshold based estimations of line edges are difficult because the threshold choice that best matches the true feature width changes with the feature geometry. Model based library fits of linescans do not appear to provide a solution because sidewall roughness and sidewall angle have similar effects on the linescan meaning no unique linescan likely exists.

Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes – which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

The semiconductor industry continues to push the limits of immersion lithography through multiple patterning techniques for printing features with critical dimension 20 nm and below. As a result overlay has become one of the critical lithography control parameters impacting device performance and has a stringent budget for yielding at smaller half pitch nodes. Overlay has several sources of errors related to scanner, lens, mask, and wafer. Lithographers have developed both linear and higher order field and wafer models to successfully compensate for the static fingerprints from different sources of error. After the static modeled portion of the fingerprint is removed, the remaining overlay error can be characterized as unstable modeled error or un-modeled error, commonly called uncorrectable residual error. This paper explores the fundamental relationship of overlay to wafer geometry through mechanisms of process-induced contributions to the wafer overlay, categorized as plastic and elastic wafer deformation. Correlation of overlay to local features such as slip lines is proven experimentally. The paper describes methodologies and geometry-induced overlay metrics for the application of wafer geometry to perform overlay feedback and feed forward applications. Feedback applications allow for process development and controlling semiconductor processes through in-line monitoring of wafers. Feed forward applications could include geometrybased corrections to the scanner for compensating non-static wafer geometry related overlay errors, and grouping wafers based on higher-order geometry.

With the device dimensions moving towards the 1X node and below, the semiconductor industry is rapidly approaching the point where existing metrology, inspection and review tools face huge challenges in terms of resolution, the ability to resolve 3D and the throughput. Due to the advantages of sub-nanometer resolution and the ability of true 3D scanning, scanning probe microscope (SPM) and specifically atomic force microscope (AFM) are considered as alternative technologies for CD-metrology, defect inspection and review of 1X node and below.

In order to meet the increasing demand for resolution and throughput of CD-metrology, defect inspection and review, TNO has previously introduced the parallel SPM concept, consisting of parallel operation of many miniaturized SPMs on a 300 and 450 mm wafer. In this paper we will present the proof of principle of the parallelization for metrology and inspection. To give an indication of the system’s specifications, the throughput of scanning is 4500 sites per hour, each within an area of 1 μm² and 1024 ×1024 pixels.

The conventional optical lever detection technique involves optical components and its precise mechanical alignment. An additional technical limit is the weight of the optical system, in case a top-scanner is used in high speed and high precision metrology. An alternative represents the application of self-actuated AFM cantilevers with integrated 2DEG piezoresistive deflection sensors. A significant improvement in performance of such cantilevers with respect to deflection sensitivity and temperature stability has been achieved by using an integrated Wheatstone bridge configuration. Due to employing effective cross-talk isolation and temperature drift compensation the performance of these cantilevers was significantly improved. In order to enhance the speed of AFM measurements we are presenting a fast cantilever-approach technology, Q-factor-control and novel adaptive scanning speed procedure. Examples of AFM measurements with high scanning speed (up to 200 lines/s) committed to advanced lithography process development are shown.

This paper aims at unraveling the mystery of damage in high speed AFMs for 1X node and below. With the device dimensions moving towards the 1X node and below, the semiconductor industry is rapidly approaching the point where existing metrology, inspection and review tools face huge challenges in terms of resolution, the ability to resolve 3D, and throughput.

In this paper, we critically asses the important issue of damage in high speed AFM for metrology and inspection of semiconductor wafers. The issues of damage in four major scanning modes (contact mode, tapping mode, non-contact mode, and peak force tapping mode) are described to show which modes are suitable for which applications and which conditions are damaging. The effects of all important scanning parameters on resulting damage are taken into account for materials such as silicon, photoresists and low K materials.

Finally, we recommend appropriate scanning parameters and conditions for several use cases (FinFET, patterned photoresist, HAR structures) that avoid exceeding a critical contact stress such that sample damage is minimized.

In conclusion, we show using our theoretical analysis that selecting parameters that exceed the target contact stress, indeed leads to significant damage. This method provides AFM users for metrology with a better understanding of contact stresses and enables selection of AFM cantilevers and experimental parameters that prevent sample damage.

Modern nano-metrology instruments require calibration references with nanometer accuracy in the x, y, and z directions. A common problem is the accurate calibration in the z direction (height). For example, it is generally not difficult to obtain accurate x- and y- calibration references for a Scanning Probe Microscope (SPM). It is, however, much more difficult to obtain accurate z-axis results. It is difficult to control z-axis piezo dynamics because during scanning in the xy-plane the x-and y-axes move at a constant rate whiles the z axis does not. Furthermore due to the high cost of producing calibration standards, the microscope is often calibrated at only one height. However, if the relationship between the measured z height and the actual z height is not linear, then the height measurements will not be correct. In this paper, we will present a method for the fabrication of calibration references with: (i) sub-10 nm features and (ii) multiple step heights on one reference, allowing for better calibration of the non-linearity in the z direction.

In this paper, we present our most recent approach on the extraction of reliable atomic force microscopy (AFM) tip dimensions from scanning electron microscopy (SEM) images in order to answer future requirements on ever shrinking CD AFM tips. We demonstrate the capabilities of a newly developed, fully automatic analysis software based on advanced SEM image modeling and user a-priori knowledge integration in SEM image analysis algorithm. The impact of such breakthrough technology will be shown as a function of its stability and robustness by varying tip shape, imaging settings, and SEM setup parameters. The extracted values are compared to data yielded from a commonly used SEM image analysis approach based on threshold type algorithms, and directly related to reference CD AFM measurements. We will discuss the prospective challenges accompanied with shrinking tip dimensions and the potential of a comprehensive data fusion approach, which can be used for both R&D and high volume production.

Simulations of Mueller matrix spectroscopic ellipsometry (MMSE) based scatterometry are used to predict sensitivity to dimensional changes and defects in directed self-assembly (DSA) patterned contact hole structures fabricated with phase-separated polystyrene-b-polymethylmethacrylate (PS-b-PMMA) before and after etch. The optical signature of Mueller matrix (MM) elements has a complex dependence on the structure topography and orientation, depolarization, and optical properties of the materials associated with the surface and any underlying layers. Moreover, the symmetry properties associated with MM elements provide an excellent means of measuring and understanding the topography of periodic nanostructures. A forward problem approach to scatterometry or optical model based simulations is used to investigate MMSE sensitivity to various DSA based contact hole structures and its limits to characterize DSA induced defects such as hole placement inaccuracy, missing vias, profile inaccuracy of the PMMA cylinder, and process induced defects such as presence of residual PMMA after etching.

Directed self-assembly (DSA) of block copolymers (BCPs) is a rising technique for sub-20 nm patterning. To fully harness DSA capabilities for patterning, a detailed understanding of the three dimensional (3D) structure of BCPs is needed. By combining sequential infiltration synthesis (SIS) and scanning transmission electron microscopy (STEM) tomography, we have characterized the 3D structure of self-assembled and DSA BCPs films with high precision and resolution. SIS is an emerging technique for enhancing pattern transfer in BCPs through the selective growth of inorganic material in polar BCP domains. Here, Al₂O₃ SIS was used to enhance the imaging contrast and enable tomographic characterization of BCPs with high fidelity. Moreover, by utilizing SIS for both 3D characterization and hard mask fabrication, we were able to characterize the BCP morphology as well as the alumina nanostructures that would be used for pattern transfer.

Advanced nodes require precise detection and control of intricate profile details – scatterometry is tool of choice for such requirements. Scatterometry is a model-based technique, and needs extensive reference metrology for qualification. Such reference measurements are costly, time-consuming and often destructive causing delays in deployment. With increasing number of scatterometry steps in flow, and the requirement to collect more reference data points to statistically qualify shrinking metrology specifications, the cost and time for reference metrology is exponentially increasing. This work is aimed to significantly reduce this need. We developed a novel methodology whereby scatterometry spectral information itself is used to predict “virtual” reference data. We qualify this methodology on several key applications from 20nm and 14nm node. We find that performance of solution developed using proposed methodology is indeed similar to performance of solution obtained using real reference data, thereby significantly reducing the lead time to develop scatterometry solutions.

Optical scatterometry is widely used in the process control of integrated circuits (IC) manufacturing due to its inherent advantages such as nondestruction, high sampling rate, large aerial coverage and low-cost. However, in the conventional inverse problem solvent of optical scatterometry, the measurement errors are usually excessively simplified as normally distributed errors, which deviate from the actual complex ones. In this work, we will demonstrate that there exist typical outlying measurement errors in the measurement signature, and these outlying measurement errors will notably affect the result of each iteration step in the conventional Gauss-Newton (GN) method. By performing a method based on the principle of least trimmed squared estimator (LTS) regression instead of each GN iteration step, the higher measurement accuracy of a nanostructure can be achieved. The remarkably improved reconstruction of a deep-etched multilayer grating has demonstrated the feasibility of the proposed method.

Methods for solving Maxwell’s equations are integral part of optical metrology and computational lithography setups. Applications require accurate geometrical resolution, high numerical accuracy and/or low computation times. We present a finite-element based electromagnetic field solver relying on unstructured 3D meshes and adaptive hp-refinement. We apply the method for simulating light scattering off arrays of high aspect-ratio nano-posts and FinFETs.

Critical dimension and overlay measurements have become a key challenge in microelectronics process control, and the weight of metrology in the success of a patterning technique is increasing. For the 14 nm node, the limit of scanner resolution can be overcome by double patterning, which requires a maximum overlay variability of 3 nm between the two reticles of the first metal level. In the double patterning case of metal layers, critical dimension of line spaces and overlay are no longer independent. In this paper, the possibility of a common measurement after the second lithography is studied. Scatterometry has been used to fit successfully the critical dimension of the two sublevels. As sensitivity to overlay is too low in device-like target, a strategy has been implemented from diffraction-based overlay measurement. So it becomes possible to provide information on the lithography step quality before the second etch process to enable rework if necessary. Finally a scatterometry target has been designed to fit simultaneously the two critical dimensions and overlay. This target, which is designed to maximize overlay sensitivity, has been placed in the next 14 nm CMOS product and is expected to make this scatterometry method even more attractive.

Traditional ellipsometric measurements of copper gratings are limited to Angstrom resolution and are rather insensitive to changes in the critical dimension (CD) or pitch of the structure. By adding another grating per- pendicular and with larger CD and pitch, sensitivity is greatly enhanced. The spectra of one dimensional grat- ings is largely featureless over a wide range of CDs while crossed-gratings exhibit large minima which shift with changing CDs of less than an Angstrom. This improvement is due to plasmonic activity in the crossed-grating, demonstrated in detail here. Mueller matrix element analysis under azimuthal rotation provides information about cross-polarization and plasmon coupling conditions.

Scatterometry mark design for improvement of the metrology performance is investigated in this joint work by ASML and STMicroelectronics. The studied marks are small, enabling metrology within the device area. The new mark-design approach reduces the effects from the mark-edges during the metrology measurement. For this, small assist-features are integrated in the mark design on the wafer. Thereby the new designs: 1. enlarge the metrology measurement-window, 2. optimize the repeatability and accuracy of the metrology at given mark size, 3. allow added functionality to existing marks within the current mark area, such as monitoring process asymmetry or multiple layer information, 4. allow for mark miniaturization at equal performance, enabling intra-field positioning. With this metrology tool-optical proximity correction (MT-OPC) included in the mark design, the metrology window is enhanced, while improved on-product overlay performance is obtained.

Along with the increased miniaturization of semiconductor electronic devices, the design rules of advanced semiconductor devices shrink dramatically. [1] One of the main challenges of lithography step is the layer-to-layer overlay control. Furthermore, DPT (Double Patterning Technology) has been adapted for the advanced technology node like 28nm and 14nm, corresponding overlay budget becomes even tighter. [2][3] After the in-die mask registration (pattern placement) measurement is introduced, with the model analysis of a KLA SOV (sources of variation) tool, it’s observed that registration difference between masks is a significant error source of wafer layer-to-layer overlay at 28nm process. [4][5] Mask registration optimization would highly improve wafer overlay performance accordingly. It was reported that a laser based registration control (RegC) process could be applied after the pattern generation or after pellicle mounting and allowed fine tuning of the mask registration. [6]

In this paper we propose a novel method of mask registration correction, which can be applied before mask writing based on mask exposure map, considering the factors of mask chip layout, writing sequence, and pattern density distribution. Our experiment data show if pattern density on the mask keeps at a low level, in-die mask registration residue error in 3sigma could be always under 5nm whatever blank type and related writer POSCOR (position correction) file was applied; it proves random error induced by material or equipment would occupy relatively fixed error budget as an error source of mask registration. On the real production, comparing the mask registration difference through critical production layers, it could be revealed that registration residue error of line space layers with higher pattern density is always much larger than the one of contact hole layers with lower pattern density. Additionally, the mask registration difference between layers with similar pattern density could also achieve under 5nm performance. We assume mask registration excluding random error is mostly induced by charge accumulation during mask writing, which may be calculated from surrounding exposed pattern density. Multi-loading test mask registration result shows that with x direction writing sequence, mask registration behavior in x direction is mainly related to sequence direction, but mask registration in y direction would be highly impacted by pattern density distribution map. It proves part of mask registration error is due to charge issue from nearby environment. If exposure sequence is chip by chip for normal multi chip layout case, mask registration of both x and y direction would be impacted analogously, which has also been proved by real data. Therefore, we try to set up a simple model to predict the mask registration error based on mask exposure map, and correct it with the given POSCOR (position correction) file for advanced mask writing if needed.

In order to handle the upcoming 1x DRAM overlay and yield requirements, metrology needs to evolve to more accurately represent product device patterns while being robust to process effects. One way to address this is to optimize the metrology target design. A viable solution needs to address multiple challenges. The target needs to be resistant to process damage. A single target needs to measure overlay between two or more layers. Targets need to meet design rule and depth of focus requirements under extreme illumination conditions. These must be achieved while maintaining good precision and throughput with an ultra-small target. In this publication, a holistic approach is used to address these challenges, using computationally optimized metrology targets with an advanced overlay control loop.

As design rule shrink, overlay has been critical factor for semiconductor manufacturing. However, the overlay error which is determined by a conventional measurement with an overlay mark based on IBO and DBO often does not represent the physical placement error in the cell area. The mismatch may arise from the size or pitch difference between the overlay mark and the cell pattern. Pattern distortion caused by etching or CMP also can be a source of the mismatch. In 2014, we have demonstrated that method of overlay measurement in the cell area by using DBM (Design Based Metrology) tool has more accurate overlay value than conventional method by using an overlay mark. We have verified the reproducibility by measuring repeatable patterns in the cell area, and also demonstrated the reliability by comparing with CD-SEM data. We have focused overlay mismatching between overlay mark and cell area until now, further more we have concerned with the cell area having different pattern density and etch loading. There appears a phenomenon which has different overlay values on the cells with diverse patterning environment. In this paper, the overlay error was investigated from cell edge to center. For this experiment, we have verified several critical layers in DRAM by using improved(Better resolution and speed) DBM tool, NGR3520.

We recently built a 405nm laser based optical interferometry system for 9nm node patterned wafer defect inspection. Defects with volumes smaller than 15nm by 90nm by 35nm have been detected. The success of defect detection relied on accurate mechanical scanning of the wafer and custom engineered image denoising post-processing. To further improve the detection sensitivity, we designed a higher precision XYZ scanning stage and replaced the laser source with an incoherent LED to remove the speckle noise. With these system modifications, we successfully detected both defects and surface contamination particles in bright-field imaging mode. Recently, we have upgraded this system for interferometric defect inspection.

Coherent extreme ultraviolet beams from tabletop high harmonic generation offer several revolutionary capabilities for observing nanoscale systems on their intrinsic length and time scales. By launching and monitoring hypersonic acoustic waves in such systems, we characterize the mechanical properties of sub-10nm layers and find that the material densities remain close to their bulk values while their elastic properties are significantly modified. Moreover, within the same measurement, by following the heat dissipation dynamics from 30-750nm-wide nanowires, we uncover a new thermal transport regime in which closely-spaced nanoscale heat sources can surprisingly cool more efficiently than widelyspaced heat sources of the same size.

In this work, the spectral emission proprieties of a droplet-based laser-produced plasma are investigated in the VUV range. These studies are performed with a spectrograph operating from 30 nm to 180 nm at a spectral resolution of 0.1 nm. The emission spectra are recorded for different droplet-based metal fuels such as tin, indium and gallium in the presence of different background gas pressure levels. The experimental results are relevant for alternative light sources that would be needed for future wafer inspection tools. In addition, the experimental results help to determine the Out- Of-Band (OOB) radiation emission of the EUV source. By tuning the type of fuel, the laser energies and the background gas, the LPP light source shows good capabilities to be operated as a tunable light source that covers a spectral emission range from the EUV to the sub-200 nm range.

Successful implementation of directed self-assembly in high volume manufacturing is contingent upon the ability to control the new DSA-specific local defects such as “dislocations” or “line-shifts” or “fingerprint-like” defects. Conventional defect inspection tools are either limited in resolution (brightfield optical methods) or in the area / number of defects to investigate / review (SEM). Here we explore in depth a scatterometry-based technique that can bridge the gap between area throughput and detection resolution. First we establish the detection methodology for scatterometry-based defect detection, then we compare to established methodology. Careful experiments using scatterometry imaging confirm the ultimate resolution for defect detection of scatterometry-based techniques as low as <1% defect per area sampled – similar to CD-SEM based detection, while retaining a 2 orders of magnitude higher area sampling rate.

Aerial image measurement system (AIMS^TM) has been widely used for wafer level inspection of mask defects. Reported inspection flows include die-to-die (D2D) and die-to-database (D2DB) methods. For patterns that do not repeat in another die, only the D2DB approach is applicable. The D2DB method requires accurate simulation of AIMS measurements for a mask pattern. An optical vectorial model is needed to depict the mask diffraction effect in this simulation. To accurately simulate the imaging results, a rigorous electro-magnetic field (EMF) model is essential to correctly take account of the EMF scattering induced by the mask topography, which is usually called the mask 3D effect.

In this study, the mask 3D model we use is rigorous coupled-wave analysis (RCWA), which calculates the diffraction fields from a single plane wave incidence. A hybrid Hopkins-Abbe method with RCWA is used to calculate the EMF diffraction at a desired accuracy level while keeping the computation time practical. We will compare the speed of the hybrid Hopkins-Abbe method to the rigorous Abbe method.

The matching between simulation and experiment is more challenging for AIMS than CD-SEM because its measurements provide full intensity information. Parameters in the mask 3D model such as film stack thickness or film optical properties, is optimized during the fitting process. We will report the fitting results of AIMS images for twodimensional structures with various pitches. By accurately simulating the AIMS measurements, it provides a necessary tool to perform the mask inspection using the D2DB approach and to accurately predict the mask defects.

With continuously shrinking design rules and corresponding low-k1 lithography, defectivity and yield are increasingly dominated by systematic patterning defects. The size of these yield-limiting defects is shrinking along with feature size, making their detection and verification more difficult. We discuss a novel, holistic approach to pattern defect detection and control, which integrates full chip layout analysis and hybrid wafer metrology data to predict wafer locations with highest probability for defect occurrence. We assess the various components of this flow by an experimental study on a 10 nm BEOL process at IMEC, using state-of-the-art negative tone development (NTD) and triple Litho-Etch patterning process.

With continuing dimension shrinkage using the TWINSCAN NXT:1950i scanner on the 28nm node and beyond, the imaging depth of focus (DOF) becomes more critical. Focus budget breakdown studies [Ref 1, 5] show that even though the intrafield component stays the same this becomes a larger relative percentage of the overall DOF. Process induced topography along with reduced Process Window can lead to yield limitations and defectivity issues on the wafer. To improve focus margin, a study has been started to determine if some correlations between scanner levelling performance, product layout and topography can be observed. Both topography and levelling intrafield fingerprints show a large systematic component that seems to be product related. In particular, scanner levelling measurement maps present a lot of similarities with the layout of the product. The present paper investigates the possibility to model the level sensor’s measured height as a function of layer design densities or perimeter data of the product. As one component of the systematics from the level sensor measurements is process induced topography due to previous deposition, etching and CMP, several layer density parameters were extracted from the GDS’s. These were combined through a multiple variable analysis (PLS: Partial Least Square regression) to determine the weighting of each layer and each parameter. Current work shows very promising results using this methodology, with description quality up to 0.8 R² and expected prediction quality up to 0.78 Q². Since product layout drives some intrafield focus component it is also important to be able to assess intrafield focus uniformity from post processing. This has been done through a hyper dense focus map experiment which is presented in this paper.

It is increasingly difficult to determine degree of completion of the patterning and the distribution at the DRAM Cell Patterns. When we research DRAM Device Cell Pattern, there are three big problems currently, it is as follows. First, due to etch loading, it is difficult to predict the potential defect. Second, due to under layer topology, it is impossible to demonstrate the influence of the hotspot. Finally, it is extremely difficult to predict final ACI pattern by the photo simulation, because current patterning process is double patterning technology which means photo pattern is completely different from final etch pattern. Therefore, if the hotspot occurs in wafer, it is very difficult to find it.

CD-SEM is the most common pattern measurement tool in semiconductor fabrication site. CD-SEM is used to accurately measure small region of wafer pattern primarily. Therefore, there is no possibility of finding places where unpredictable defect occurs. Even though, "Current Defect detector" can measure a wide area, every chip has same pattern issue, the detector cannot detect critical hotspots. Because defect detecting algorithm of bright field machine is based on image processing, if same problems occur on compared and comparing chip, the machine cannot identify it. Moreover this instrument is not distinguished the difference of distribution about 1nm~3nm. So, "Defect detector" is difficult to handle the data for potential weak point far lower than target CD.

In order to solve those problems, another method is needed. In this paper, we introduce the analysis method of the DRAM Cell Pattern Hotspot.

High-end semiconductor lithography requirements for CD, focus and overlay control drive the need for diffraction-based metrology^1,2,3,4 and integrated metrology⁵. In the advanced nodes, more complex lithography techniques (such as multiple patterning), use of multi-layer overlay measurements in process control, advanced device designs (such as advanced FinFET), as well as advanced materials (like hardmasks) are introduced. These pose new challenges for lithometro cycle time, cost, process control and metrology accuracy. In this publication a holistic approach is taken to face these challenges via a novel target design, a brand new implementation of multi-layer overlay measurement capability in diffraction-based mode and integrated metrology.

The continuing trend of shrinking dimension and the related specifications requires tightening of control loops. To support the tighter control loops, the metrology sampling plans will require increasing sampling density and frequency. This study shows that tighter control of scanner focus and AEI CD and profile parameters requires sampling schemes with intra-field measurement points, and a frequent update of the corrections. This drives the need for high-speed smalltarget metrology. Experiments show that this can be achieved by the YieldStar angle resolved scatterometer, demonstrating measurements on areas of 16×16μm² for focus metrology and 12×12μm² for CD metrology, at a MAM time below 0.5s.

Copper interconnects have been adopted in advanced semiconductor manufacturing due to benefits of reduced RC delay, cross talk and power consumption. With each technology node, interconnects reduce in size resulting in increased line resistivity, a critical metric in determining the device performance. Reactive Ion Etching (RIE) and Copper Chemical Mechanical Polishing (Cu CMP) are two of the key back end of the line (BEOL) processes that affect the interconnect performance. Due to variations from incoming processes and the inherent variability induced by these processes, dielectric trench depth and resulting copper line height variations that can potentially result from these processes have direct impact to RC delay.

Traditional inline metrology methods used are time consuming and do not provide the needed wafer level metrics. In addition, measurement of remaining dielectric thickness on solid pads is not a good representative of the actual device structures and has been inaccurate for process due to dishing of the copper pads. Efficient control of BEOL processes requires measurement of metal line thickness and other critical profile parameters from which resistance can be extracted. In order to relate BEOL process steps and understand their interactions, it is necessary to have a directly comparable measurement methodology on a similar measurement structure.

Over the past several years, scatterometry has been proven as the only metrology method to provide the full profile information of the Cu lines. Scatterometry is a diffraction based optical measurement technique using Rigorous Coupled Wave Analysis (RCWA), where light diffracted from a periodic structure is used to characterize the details of profile. Unique algorithms, such as Holistic Metrology can be used to make the scatterometry development process faster.

In this paper, we will present how scatterometry can be used to measure copper line height on 3D structures and how feed forward from RIE can be applied for control of Cu CMP process for 20nm technology node. The importance of incoming trench depth variations is demonstrated for CMP polish time control in order to stabilize the copper line height. Validation data is presented for different scatterometry models including accuracy, repeatability and DoE tracking. Electrical resistance is shown to correlate to the copper trench profile measured by scatterometry. The paper will demonstrate the capability for reducing copper line height variation and the correlation of the reducing trench height variation to improved stabilization of electrical resistance.

Hybrid metrology (HM) is the practice of combining measurements from multiple toolset types in order to enable or improve metrology for advanced structures. HM is implemented in two phases: Phase-1 includes readiness of the infrastructure to transfer processed data from the first toolset to the second. Phase-2 infrastructure allows simultaneous transfer and optimization of raw data between toolsets such as spectra, images, traces – co-optimization. We discuss the extension of Phase-1 to include direct high-bandwidth communication between toolsets using a hybrid server, enabling seamless fab deployment and further laying the groundwork for Phase-2 high volume manufacturing (HVM) implementation. An example of the communication protocol shows the information that can be used by the hybrid server, differentiating its capabilities from that of a host-based approach. We demonstrate qualification and production implementation of the hybrid server approach using CD-SEM and OCD toolsets for complex 20nm and 14nm applications. Finally we discuss the roadmap for Phase-2 HM implementation through use of the hybrid server.

Integrate circuit (IC) technology is going through multiple changes in terms of patterning techniques (multiple patterning, EUV and DSA), device architectures (FinFET, nanowire, graphene) and patterning scale (few nanometers). These changes require tight controls on processes and measurements to achieve the required device performance, and challenge the metrology and process control in terms of capability and quality. Multivariate data with complex nonlinear trends and correlations generally cannot be described well by mathematical or parametric models but can be relatively easily learned by computing machines and used to predict or extrapolate. This paper introduces the predictive metrology approach which has been applied to three different applications. Machine learning and predictive analytics have been leveraged to accurately predict dimensions of EUV resist patterns down to 18 nm half pitch leveraging resist shrinkage patterns. These patterns could not be directly and accurately measured due to metrology tool limitations. Machine learning has also been applied to predict the electrical performance early in the process pipeline for deep trench capacitance and metal line resistance. As the wafer goes through various processes its associated cost multiplies. It may take days to weeks to get the electrical performance readout. Predicting the electrical performance early on can be very valuable in enabling timely actionable decision such as rework, scrap, feedforward, feedback predicted information or information derived from prediction to improve or monitor processes. This paper provides a general overview of machine learning and advanced analytics application in the advanced semiconductor development and manufacturing.

Hybrid metrology, e.g. the combination of several measurement techniques to determine critical dimensions, is an important approach to meet the needs of semiconductor industry. A proper use of hybrid metrology may not only yield more reliable estimates for the quantitative characterization of 3-D structures but also a more realistic estimation of the corresponding uncertainties. Recent developments at the National Institute of Standards and Technology (NIST) feature the combination of optical critical dimension (OCD) measurements and scanning electron microscope (SEM) results. The hybrid methodology offers the potential to make measurements of essential 3-D attributes that may not be otherwise feasible. However, combining techniques gives rise to essential challenges in error analysis and comparing results from different instrument models, especially the effect of systematic and highly correlated errors in the measurement on the ¬χ² function that is minimized. Both hypothetical examples and measurement data are used to illustrate solutions to these challenges.

The on product overlay specification and Advanced Process Control (APC) is getting extremely challenging particularly after the introduction of multi-patterning applications like Spacer Assisted Double Patterning (SADP) and multipatterning techniques like N-repetitive Litho-Etch steps (LE^N, N ≥ 2). When the latter is considered, most of the intrafield overlay contributors drop out of the overlay budget. This is a direct consequence of the fact that the scanner settings (like dose, illumination settings, etc.) as well as the subsequent processing steps can be made very similar for two consecutive Litho-Etch layers. The major overlay contributor that may require additional attention is the Image Placement Error (IPE). When the inter-layer overlay is considered, controlling the intra-field overlay contribution gets more complicated. In addition to the IPE contribution, the TWINSCAN^TM lens fingerprint in combination with the exposure settings is going to play a role as well. Generally speaking, two subsequent functional layers have different exposure settings. This results in a (non-reticle) additional overlay contribution.

In this paper, we have studied the wafer overlay correction capability by RegC® in addition to the TWINSCAN^TM intrafield corrections to improve the on product overlay performance. RegC® is a reticle intra-volume laser writing technique that causes a predictable deformation element (RegC® deformation element) inside the quartz (Qz) material of a reticle. This technique enables to post-process an existing reticle to correct for instance for IPE. Alternatively, a pre-determined intra-field fingerprint can be added to the reticle such that it results in a straight field after exposure. This second application might be very powerful to correct for instance for (cold) lens fingerprints that cannot be corrected by the scanner itself. Another possible application is the intra-field processing fingerprint. One should realize that a RegC® treatment of a reticle generally results in global distortion of the reticle. This is not a problem as long as these global distortions can be corrected by the TWINSCAN^TM system (currently up to the third order). It is anticipated that the combination of the RegC® and the TWINSCAN^TM corrections act as complementary solutions. These solutions perfectly fit into the ASML Litho InSight (LIS) product in which feedforward and feedback corrections based on YieldStar overlay measurements are used to improve the on product overlay.

On-product overlay can be improved through the use of context data from the fab and the scanner. Continuous improvements in lithography and processing performance over the past years have resulted in consequent overlay performance improvement for critical layers. Identification of the remaining factors causing systematic disturbances and inefficiencies will further reduce overlay. By building a context database, mappings between context, fingerprints and alignment & overlay metrology can be learned through techniques from pattern recognition and data mining. We relate structure (‘patterns’) in the metrology data to relevant contextual factors. Once understood, these factors could be moved to the known effects (e.g. the presence of systematic fingerprints from reticle writing error or lens and reticle heating). Hence, we build up a knowledge base of known effects based on data. Outcomes from such an integral (‘holistic’) approach to lithography data analysis may be exploited in a model-based predictive overlay controller that combines feedback and feedforward control [1]. Hence, the available measurements from scanner, fab and metrology equipment are combined to reveal opportunities for further overlay improvement which would otherwise go unnoticed.

This paper demonstrates the synergy between X-rays techniques and scatterometry, and the benefits to combine the data to improve the accuracy and precision for in-line metrology. Particular example is given to show that the hybridization addresses the challenges of aggressive patterning. In 10nm node back-end-of-line (BEOL) integration, we show that the hybridized data between scatterometry and simultaneous X-Ray Fluorescence (XRF) and X-ray Photoelectron Spectroscopy (XPS) provided the closest dimensional correlation to TEM results compared to the individual technique and CDSEM.

Grazing-Incidence Small Angle X-ray Scattering (GISAXS) offers the ability to probe large sample areas, providing three-dimensional structural information at high detail in a thin film geometry. In this study we exploit the application of GISAXS to structures formed at one step of the LiNe (Liu-Nealey) flow using chemical patterns for directed self-assembly of block copolymer films. Experiments conducted at the Argonne National Laboratory provided scattering patterns probing film characteristics at both parallel and normal directions to the surface. We demonstrate the application of new computational methods to construct models based on scattering measured. Such analysis allows for extraction of structural characteristics at unprecedented detail.

CD uniformity requirements at 20nm and more advanced nodes have challenged the precision limits of CD-SEM metrology, conventionally used for scanner qualification and in-line focus/dose monitoring on product wafers. Optical CD metrology has consequently gained adoption for these applications because of its superior precision, but has been limited adopted, due to challenges with long time-to-results and robustness to process variation. Both of these challenges are due to the limitations imposed by geometric modeling of the photoresist (PR) profile as required by conventional RCWA-based scatterometry. Signal Response Metrology (SRM) is a new technique that obviates the need for geometric modeling by directly correlating focus, dose, and CD to the spectral response of a scatterometry tool. Consequently, it suggests superior accuracy and robustness to process variation for focus/dose monitoring, as well as reducing the time to set up a new measurement recipe from days to hours. This work describes the fundamental concepts of SRM and the results of its application to lithography metrology and control. These results include time to results and measurement performance data on Focus, Dose and CD measurements performed on real devices and on design rule metrology targets.

Helium ion microscopy (HIM) has been used to study nanopatterns formed in block copolymer (BCP) thin films. Owing to its’ small spot size, minimal forward scattering of the incident ion and reduced velocity compared to electrons of comparable energy, HIM has considerable advantages and provides pattern information and resolution not attainable with other commercial microscopic techniques.

In order to realize the full potential of BCP nanolithography in producing high density ultra-small features, the dimensions and geometry of these BCP materials will need to be accurately characterized through pattern formation, development and pattern transfer processes. The preferred BCP pattern inspection techniques (to date) are principally atomic force microscopy (AFM) and secondary electron microscopy (SEM) but suffer disadvantages in poor lateral resolution (AFM) and the ability to discriminate individual polymer domains (SEM). SEM suffers from reduced resolution when a more surface sensitive low accelerating voltage is used and low surface signal when a high accelerating voltage is used. In addition to these drawbacks, SEM can require the use of a conductive coating on these insulating materials and this reduces surface detail as well as increasing the dimensions of coated features. AFM is limited by the dimensions of the probe tip and a skewing of lateral dimension results. This can be eliminated through basic geometry for large sparse features, but when dense small features need to be characterized AFM lacks reliability. With this in mind, BCP inspection by HIM can offer greater insight into block ordering, critical dimensions and, critically, line edge roughness (LER) a critical parameter whose measurement is well suited to HIM because of its’ enhanced edge contrast.

In this work we demonstrate the resolution capabilities of HIM using various BCP systems (lamellar and cylinder structures). Imaging of BCP patterns of low molecular weight (MW)/low feature size which challenges the resolution of HIM technique. Further, studies of BCP patterns with domains of similar chemistry will be presented demonstrating the superior chemical contrast compared to SEM. From the data, HIM excels as a BCP inspection tool in four distinct areas. Firstly, HIM offers higher resolution at standard imaging conditions than SEM. Secondly, the signal generated from He⁺ is more surface sensitive and enables visualization of features that cannot be resolved using SEM. Thirdly; superior chemical contrast enables the imaging of un etched samples with almost identical chemical composition. Finally, dimensional measurement accuracy is high and consistent with requirements for advanced lithographic masks.

Tip-enhanced Raman spectroscopy (TERS), with nanometer spatial resolution, has the capability to monitor chemical composition, strain, and activated dopants and is a promising metrology tool to aid the semiconductor R&D processes. This paper addresses the major challenges which limit the application of TERS from routine measurement: the lack of comparability, reproducibility, calibration, and standardization. To address these issues, we have developed a robust test structure and the ability to generate high-quality tips using a high volume manufacturing (HVM) approach. The qualifying data will be presented.

While semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory, an increased emphasis has been placed on reducing the influence known contributors have toward the on product overlay budget. With a machine learning technique known as function approximation, we use a neural network to gain insight to how known contributors, such as those collected with scanner metrology, influence the on product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system. As a real world application, inline metrology can be used to measure overlay for a few wafers while using the trained function to approximate overlay vector maps for the entire lot of wafers. With the approximated overlay vector maps for all wafers coming off the track, a process engineer can redirect wafers or lots with overlay signatures outside the standard population to offline metrology for excursion validation. With this added flexibility, engineers will be given more opportunities to catch wafers that need to be reworked, resulting in improved yield. The quality of the derived corrections from measured overlay metrology feedback can be improved using the approximated overlay to trigger, which wafers should or shouldn’t be, measured inline. As a development or integration engineer the approximated overlay can be used to gain insight into lots and wafers used for design of experiments (DOE) troubleshooting. In this paper we will present the results of a case study that follows the machine learning function approximation approach to data analysis, with production overlay measured on an inline metrology system at SK hynix.

Multiple electron beam SEMs enable detecting structures of few nanometer in diameter at much higher throughputs than possible with single beam electron microscopes at comparable electron probe parameters. Although recent multiple beam SEM development has already demonstrated a large speed increase¹, higher throughputs are still required to match the needs of many semiconductor applications². We demonstrate the next step in the development of multi-beam SEMs by increasing the number of beams and the current per beam. The modularity of the multi-beam concept ensures that design changes in the multi-beam SEM are minimized.

With the introduction of N2x and N1x process nodes, leading-edge factories are facing challenging demands of shrinking design margins. Previously un-corrected high-order signatures, and un-compensated temporal changes of high-order signatures, carry an important potential for improvement of on-product overlay (OPO). Until recently, static corrections per exposure (CPE), applied separately from the main APC correction, have been the industry’s standard for critical layers [1], [2]. This static correction is setup once per device and layer and then updated periodically or when a machine change point generates a new overlay signature. This is a non-ideal setup for two reasons. First, any drift or sudden shift in tool signature between two CPE update periods can cause worse OPO and a higher rework rate, or, even worse, lead to yield loss at end of line. Second, these corrections are made from full map measurements that can be in excess of 1,000 measurements per wafer [3].

Advanced overlay control algorithms utilizing Run-to-Run (R2R) CPE can be used to reduce the overlay signatures on product in High Volume Manufacturing (HVM) environments. In this paper, we demonstrate the results of a R2R CPE control scheme in HVM. The authors show an improvement up to 20% OPO Mean+3Sigma values on several critical immersion layers at the 28nm and 14 nm technology nodes, and a reduction of out-of-spec residual points per wafer (validated on full map). These results are attained by closely tracking process tool signature changes by means of APC, and with an affordable metrology load which is significantly smaller than full wafer measurements.

The capabilities and limitations of angular scatterometry for a structure pitch much less than the optical wavelength are experimentally investigated using a 100-nm pitch Al-wire grid polarizer on a SiO₂ substrate. Three CW laser sources of wavelengths (244 nm, 405 nm and 633 nm) are used to measure the 0-order diffraction (reflection) across an incident angle range of 8° to 80°. The grating profile is defined by seven parameters (pitch, bottom linewidth, top linewidth, fused silica undercut, Al thickness, horizontal and vertical extent of top rounding). Rigorous coupled wave analysis (RCWA) simulations show that the reflectivity versus angle results are sensitive to changes in all of these parameters. The simulations act as a baseline library for the scatterometry measurements. Fitting the experimental curves with the corresponding simulation parameters results in a determination of the grating profile. As expected the shorter wavelength measurements provide the most sensitivity, but good precision is obtained at all three wavelengths. The measurements are in good agreement with destructive cross section scanning electron microscopy measurements.

While feature size in lithography process continuously becomes smaller, defect sizes on blank wafers become more comparable to device sizes. Defects with nm-scale characteristic size could be misclassified by automated optical inspection (AOI) and require post-processing for proper classification. Atomic force microscope (AFM) is known to provide high lateral and the highest vertical resolution by mechanical probing among all techniques. However, its low throughput and tip life in addition to the laborious efforts for finding the defects have been the major limitations of this technique. In this paper we introduce automatic defect review (ADR) AFM as a post-inspection metrology tool for defect study and classification for 300 mm blank wafers and to overcome the limitations stated above. The ADR AFM provides high throughput, high resolution, and non-destructive means for obtaining 3D information for nm-scale defect review and classification.

Feedback control of overlay errors to the scanner is a well-established technique in semiconductor manufacturing [1]. Typically, overlay errors are measured, and then modeled by least-squares fitting to an overlay model. Overlay models are typically Cartesian polynomial functions of position within the wafer (X_w, Y_w), and of position within the field (X_f, Y_f). The coefficients from the data fit can then be fed back to the scanner to reduce overlay errors in future wafer exposures, usually via a historically weighted moving average. In this study, rather than using the standard Cartesian formulation, we examine overlay models using Zernike polynomials to represent the wafer-level terms, and Legendre polynomials to represent the field-level terms. Zernike and Legendre polynomials can be selected to have the same fitting capability as standard polynomials (e.g., second order in X and Y, or third order in X and Y). However, Zernike polynomials have the additional property of being orthogonal over the unit disk, which makes them appropriate for the wafer-level model, and Legendre polynomials are orthogonal over the unit square, which makes them appropriate for the field-level model. We show several benefits of Zernike/Legendre-based models in this investigation in an Advanced Process Control (APC) simulation using highly-sampled fab data. First, the orthogonality property leads to less interaction between the terms, which makes the lot-to-lot variation in the fitted coefficients smaller than when standard polynomials are used. Second, the fitting process itself is less coupled – fitting to a lower-order model, and then fitting the residuals to a higher order model gives very similar results as fitting all of the terms at once. This property makes fitting techniques such as dual pass or cascading [2] unnecessary, and greatly simplifies the options available for the model recipe. The Zernike/Legendre basis gives overlay performance (mean plus 3 sigma of the residuals) that is the same as standard Cartesian polynomials, but with stability similar to the dual-pass recipe. Finally, we show that these properties are intimately tied to the sample plan on the wafer, and that the model type and sampling must be considered at the same time to demonstrate the benefits of an orthogonal set of functions.

This paper focuses on orthogonal model corrections where model parameters do not influence each other as long as the measurement layout is sufficiently symmetric. For the grid correction we used Zernike polynomials, and for the intrafield correction we used a two-dimensional set of Legendre polynomials. We enabled these corrections by developing a transformation matrix as an exposure tool is incapable of correcting such orthogonal polynomials. Simulation with OVALiS shows that the linear parameters get stabilized by several factors when using a combined Zernike/Legendre model. The correlation between linear and higher order parameters disappears, and overlay mean plus 3-sigma improves up to ~15–20%. Simulated data agrees well with experimental and electrical data. Additionally, we introduced an interpolated metric that probed the wafer and field with a dense grid. This interpolated metric showed that the Zernike/Legendre model-based correction does not cause over-correction like that seen on standard polynomial models. We have tested higher order process corrections comprehensively by enabling an orthogonal model, as well as by making use of interpolated metrics to monitor the overlay performance. These orthogonal models can be implemented in the production line based on inline overlay data where interpolated metrics will ensure that there is no over-correction and no negative impact on product.

In this paper, we examine the sensitivity of scatterometry for the 3D isolation mounts on the substrate by applying PML in RCWA. We analyze the reflectance from the silicon and resist single mount and the silicon double mounts on the silicon substrate. First, we investigate the beam width dependences of reflectance. Second, we show the propagation properties of the electromagnetic fields propagating for the isolation mounts on the silicon substrate. Third, we show the reflectance properties by changing the mount length and width on the Si substrate. Finally, we examine the wavelength properties of reflectance calculated by changing the mount length, width and height for single mount and the silicon mount positions for the double silicon mounts. Then, we understand the scatterometry observation is possible in several microns beam width.

Persistently shrinking design rules and increasing process complexity require tight overlay control thereby making it imperative to choose the most suitable overlay measurement technique and complementary target design. In this paper we describe an assessment of various target designs from FEOL to BEOL on 20-nm process. Both scatterometry and imaging based methodology were reviewed for several key layers on A500LCM tool, which enables the use of both technologies. Different sets of targets were carefully designed and printed, taking into consideration the process and optical properties of each layer. The optimal overlay target for a given layer was chosen based on its measurement performance.

In advanced semiconductor industries, the overlay error budget is getting tighter due to shrinkage in technology. To fulfill the tighter overlay requirements, gaining every nanometer of improved overlay is very important in order to accelerate yield in high-volume manufacturing (HVM) fabs. To meet the stringent overlay requirements and to overcome other unforeseen situations, it is becoming critical to eliminate the smallest imperfections in the metrology targets used for overlay metrology. For standard cases, the overlay metrology recipe is selected based on total measurement uncertainty (TMU). However, under certain circumstances, inaccuracy due to target imperfections can become the dominant contributor to the metrology uncertainty and cannot be detected and quantified by the standard TMU. For optical-based overlay (OBO) metrology targets, mark asymmetry is a common issue which can cause measurement inaccuracy, and it is not captured by standard TMU. In this paper, a new calibration method, Archer Self-Calibration (ASC), has been established successfully in HVM fabs to improve overlay accuracy on image-based overlay (IBO) metrology targets. Additionally, a new color selection methodology has been developed for the overlay metrology recipe as part of this calibration method. In this study, Qmerit-calibrated data has been used for run-to-run control loop at multiple devices. This study shows that color filter can be chosen more precisely with the help of Qmerit data. Overlay stability improved by 10~20% with best color selection, without causing any negative impact to the products. Residual error, as well as overlay mean plus 3-sigma, showed an improvement of up to 20% when Qmerit-calibrated data was used. A 30% improvement was seen in certain electrical data associated with tested process layers.

Mass production of nanostructured surfaces relies on the periodic repetition of micrometre scale patterns. A unit cell with nanometre features in the micrometre size range is repeated thousands of times. The ensemble can used as a diffraction grating for visible light. The relative intensity distribution of the diffraction orders is characteristic for the grating and sensitive to nanometre scale changes. A newly designed subwavelength diffraction setup allows the measurement in real time of the diffraction pattern of an illuminated polymer grating with only one detector image. The setup records diffraction patterns of, for example, polymer gratings with intentionally low scattering contrast and line features ranging from 610 to 80 nm. Thus, sub-100 nm features can be traced. The comparison of the measured diffraction patterns with simulated patterns allows to sense nanometre scale deviations from fabrication goals.

The performance of CD-SEMs directly affects the measured values of critical dimensions (CDs) at the time of their measurement. Tracking the performance of CD-SEMs is necessary to establish trust in their results and provide guidance for preventive maintenance and tune-ups. When the measured CDs are out of specification in manufacturing, it is crucial to determine whether this is due to process variation or the metrology tool itself. Multiple methods that use linewidth measurements have been employed thus far; however, they suffer from linewidth variations on the wafer, as well as from variations of line edge and linewidth roughness. Here, we report a method that is capable of providing a quantitative extraction of the SEM performance based on advanced algorithms. The method is independent of linewidth, line edge roughness and linewidth roughness, and has high sensitivity. This software, QSEM, was developed to automatically evaluate image quality and assign a value to that quality. The image quality value is based on multiple factors such as noise, sharpness, analysis of histograms, and contrast. The sensitivity of the software was evaluated; a good correlation between image quality results and linewidth variation due to SEM performance was established. Using QSEM to analyze SEM images allows the performance of CDSEMs to be tracked for proper calibration and preventive maintenance, as well as to resolve the dispute between failure in the process or the metrology.

For several decades, the semiconductor industry has been controlling site flatness of the starting wafer material by defining tight specs on industry-standard site flatness metrics such as SFQR (Site Frontsurface-referenced least sQuares/Range) and ESFQR (Edge Site Frontsurface-referenced least sQuares/Range) that scale with technology nodes. The need for controlling site flatness of the starting material stems from previous research that shows that site flatness directly impacts lithography defocus. The wafer flatness variation changes significantly due to wafer processing downstream such as CMP, etch, and film deposition. Hence, for 2X nm and smaller technology nodes with very stringent focus process windows, it is critical to control wafer flatness variations at critical steps along the semiconductor process flow. In this paper, the capability of an interferometer-based patterned wafer metrology tool to predict lithography defocus is validated by comparison to scanner leveling data. The patterned wafer metrology tool is used to characterize the impact of near-edge flatness changes on the critical dimension (CD) of the contact holes due to different edge CMP process conditions. The results of the characterization illustrate how a site flatness specification or threshold can be developed for critical patterning steps. The paper also illustrates how the patterned wafer metrology tool can be used to identify processes causing site flatness variations. Finally, the site flatness variation at these processes can be monitored using the pattern wafer metrology tool to detect process drifts and excursion before patterning.

Scatterometry critical dimension (SCD) technology in state of the art semiconductor manufacturing is a well-accepted and powerful technique to determine profile properties such as critical dimensions, sidewall angles, trench depths as well as layer thicknesses of microelectronic structures. The amount and combination of information receivable via SCD measurements makes it, as long as interpreted correctly and incoming process variations especially incoming material variations are well understood, superior to other measurement techniques such as critical dimension scanning electron microscopy (CDSEM), transmission electron microscopy (TEM) or atomic force microscopy (AFM). For high throughput inline process monitoring and feedback SCD models are usually generated for uniform gratings having fixed pitches representing dense areas of the microelectronic chip design. However, for purposes such as improvement in process tool matching, wafer uniformity or optical proximity correction (OPC) it is of great value if the measured test patterns do have different layout properties being representative for other design elements and styles as well. In this paper a through pitch SCD measurement within the shallow trench isolation (STI) layer on the 28nm node is presented. This approach allows to interpret, to tune and to monitor process tool behavior for different pattern densities using only one single specially designed lithography mask. Two different use cases are shown: for varying pitch sizes either the designed line CD or the designed space CD is kept constant. General SCD modelling approaches and examples to illustrate the key idea and practical use will be provided.

Scanning Electron Microscopy (SEM) is widely used to measure Critical Dimensions (CD) in semiconductor lithography processes. Correlation between the CD-SEM metrology and target profile has drawing attention from metrology community [1]. In this paper, we use a recently developed CD-SEM simulator [2-3] to investigate some artifacts of SEM metrology. The simulation consists of two parts. First part is a stochastic resist modeling for lines and spaces through pitch, exposure dose and focus. Second part is CD-SEM simulation. Both CD and LWR extracted from experimental CD-SEM images were used to train the SEM model. Two types of artifacts were found to be metrology dependent: the first artifact is that a CD-SEM measures CD at various heights across pitch for the same SEM threshold. The second artifact is a misleading CD measurement for trenches not fully developed. By overlapping the CD-SEM simulation with 3D lithography simulation, correlation between CD-SEM metrology and target 3D profile is studied. Finally, a Process Window (PW) analysis based on both experiment and simulation is presented, using the simulated features and SEM images to correct the experimental PW.

Advanced design nodes require more complex lithography techniques, such as double patterning, as well as advanced materials like hard masks. This poses new challenge for overlay metrology and process control. In this publication several step are taken to face these challenges. Accurate overlay metrology solutions are demonstrated for advanced memory devices.

For advanced lithography metrology, SCD (Scatterometry Critical Dimension) is a common metrology technique applied to control processes. SCD has the capability to report accurate data information such as CD (Critical Dimensions), photoresist SWA (Side Wall Angle) and photoresist HT (Height). The shape of photoresist correlates with inline process controllers, namely scanner focus and dose. However, SCD is a model-based metrology method. In order to decode the process controllers, it requires computation from a geometric model. Once the model extracts the resist shape information from the spectra, one needs further correlation of those geometric parameters with the process controllers for monitoring. Thus, information loss through multiple modeling is a major concern. Indeed, during data transformation, noise and model approximation can distort the signals, in other words, the critical parameters, focus and dose, may not be measured accurately. This study therefore seeks a methodology to monitor focus and dose with the least amount of information transformation. Signal Response Metrology is a new measurement technique that obviates the need for geometric modeling by directly correlating focus, dose or CD to the spectral response of a SCD-based metrology tool.

Electrostatic discharge (ESD) problem resulting from charges on wafers is a serious concern in IC manufacturing. As is discovered in our paper, three types of defect, AA (active area) damage, IMD (Inter Metal Dielectric) crack and Via hole W corrosion that are confirmed to be induced by lithography process related ESD charging effect. We carefully studied the mechanism of these ESD charging effect by DOE splits and succeeded to dig out that these electric charge major comes from the lithography develop process. In the lithography coating and developing wafer process, the wafer will be at high spin speed at many of the steps which will easy help to store the electric charge on the wafer. In our study, the rinse step in developing process is the most key factor to store the electric charge on wafer. In generally, the higher rinse speed, the higher positive electric charge. Furthermore, we also discovered that the different step in develop rinse process have different impact on charge level, in which the acceleration and deceleration step has the highest charge voltage.

As to minimize and eliminate the ESD damage in lithography process, we finally carry out the simplified recipe optimization solution which only need optimize for the develop rinse speed with different in-coming surface charge level and process application, so that can be easy implemented in the worldwide fabs.

Scanner Focus window of the lithographic process becomes much smaller due to the shrink of the device node and multipatterning approach. Consequently, the required performance of scanner focus becomes tighter and more complicated. Focus control/monitoring methods such as “field-by-field focus control” or “intra-field focus control” is a necessity. Moreover, tight scanner focus performance requirement starts to raise another fundamental question: accuracy of the reported scanner focus.

The insufficient accuracy of the reported scanner focus using the existing methods originates from:

a) Focus measurement quality, which is due to low sensitivity of measured targets, especially around the nominal production focus.

b) The scanner focus is estimated using special targets, e.g. large pitch target and not using the device-like structures (irremovable aberration impact).

Both of these factors are eliminated using KLA-Tencor proprietary “Focus Offset” technology.

The Liu-Nealey (LiNe) chemo-epitaxy Directed Self Assembly flow has been screened thoroughly in the past years in terms of defects. Various types of DSA specific defects have been identified and best known methods have been developed to be able to get sufficient S/N for defect inspection to help understand the root causes for the various defect types and to reduce the defect levels to prepare the process for high volume manufacturing. Within this process development, SEM-review and defect classification play a key role. This paper provides an overview of the challenges that DSA brings also in this metrology aspect and we will provide successful solutions in terms of making the automated defect review. In addition, a new Real Time Automated Defect Classification (RT-ADC) will be introduced that can save up to 90% in the time required for manual defect classification. This will enable a much larger sampling for defect review, resulting in a better understanding of signatures and behaviors of various DSA specific defect types, such as dislocations, 1-period bridges and line wiggling.

Embedded defect types continue to be a challenge for scanning electron microscopes (SEM) review solutions. Though high energy beams can be used to image these defect types, they cause damage to the reviewed sites. Also, imaging all review sites at higher electron energy has often resulted in low topography surface defects to be non-visible due to high penetration depth. In this work we present a method in which defects are reviewed at non-destructive lower electron energies and only the non-visual review sites are reviewed at higher electron energies to image any potential additional defect types. The non-visual defects are identified inline during review using automatic defect classification attributes.

In order to optimize the time to market of the newest technology nodes and maximize their profitability, advanced semiconductor manufacturers need to adapt their yield enhancement strategies to their current development stage. During very early development, gross Defectivity at some critical process steps often makes it impractical to use broadband plasma or laser scanning micro-defect patterned wafer inspection techniques: such sensitive defect inspections capture a large number of defects, producing wafer defect maps so heavily populated that even wafer level signature are difficult to visualize.

As the technology node of semiconductor industry is being driven into more advanced 28 nm and beyond, the critical dimension (CD) error budget at after-development inspection (ADI) stage and its control are more and more important and difficult (1-4). 1 nm or even 0.5 nm CD difference is critical for process control. 0.5~1 nm drift of poly linewidth will result in a detectable off-target drift of device performance. The 0.5~1 nm CD drift of hole or metal linewidth on the backend interconnecting layers can potentially contribute to the bridging of metal patterns to vias, and thereby impact yield. In this paper, we studied one function in the scanning electron microscope (SEM) measurement, i.e. the adjustment of brightness and contrast (ABC). We revealed how the step of addressing focus and even the choice of addressing pattern may bring in a systematic error into the CD measurement. This provides a unique insight in the CD measurement and the measurement consistency of through-pitch (TP) patterns and functional patterns.

Layout pattern density impacts mask critical dimension uniformity (MCDU) as well as wafer critical dimension uniformity (WCDU) performances in some aspects. In patterning the dense contact array with negative tone development (NTD) process, the abrupt pattern density change around the array edge of a NTD clear tone reticle arises as a very challenging issue for achieving satisfactory WCDU. Around the array boundary, apart from the MCDU greatly impacted by the abrupt pattern density change, WCDU in lithographic process is also significantly influenced by the optical flare and chemical flare effects. This study investigates the pattern density effect induced MCDU and WCDU variations. Various pattern densities are generated by the combination of fixed array pattern and various sub-resolution assist feature (SRAF) extension regions for quantifying the separated WCD variation budget contributed by MCD variation, chemical flare effect and optical flare effect. With the proper pattern density modulation outside the array pattern on a clear tone reticle, MCD variation across array can be eliminated, optical flare and chemical flare effects induced WCD variation is also greatly suppressed.

As integrated circuit (IC) industry steps into immersion lithography’s era, defectivity in photolithography becomes more complex which requires more efforts in the analysis and solution finding when compared to traditional dry lithographic process. In this paper, we focus on one type of immersion defect from memory or flash memory devices with typical mask layouts. Since the use of self-aligned double patterning (SADP) or other double patterning techniques, the original single pattern layer has to be split into 2 mask layers: logic area vs cell area. One characteristic of such split process is that the total mask transmission rate (TR) is above 70%, with extended open area and a pattern area with a transmission rate close to 50%. This indicates that it may have special defect mechanism and type compared to logic devices. We have found one type of residue defect with center ring-like map. We have studied this defect with different development recipes and analyzed their underlying mechanisms. We have also studied the effect of different immersion photoresists including types with top-coating and without top-coating, as well as the effect of bottom anti-reflection coating (BARC) substrate (organic-BARC/Si-BARC). The results of our study will be presented and discussed.

The use of purified carbon dioxide (CO₂) has become a reality for leading edge 193 nm immersion lithography scanners. Traditionally, both dry and immersion 193 nm lithographic processes have constantly purged the optics stack with ultrahigh purity compressed dry air (UHPCDA). CO₂ has been utilized for a similar purpose as UHPCDA. Airborne molecular contamniation (AMC) purification technologies and analytical measurement methods have been extensively developed to support the Lithography Tool Manufacturers purity requirements. This paper covers the analytical tests and characterizations carried out to assess impurity removal from 3.0 N CO₂ (beverage grade) for its final utilization in 193 nm and EUV scanners.

The technological challenges that have been overcome to make extreme ultraviolet lithography (EUV) a reality have been enormous1. This vacuum driven technology poses significant purity challenges for the gases employed for purging and cleaning the scanner EUV chamber and source. Hydrogen, nitrogen, argon and ultra-high purity compressed dry air (UHPCDA) are the most common gases utilized at the scanner and source level. Purity requirements are tighter than for previous technology node tools. In addition, specifically for hydrogen, EUV tool users are facing not only gas purity challenges but also the need for safe disposal of the hydrogen at the tool outlet. Recovery, reuse or recycling strategies could mitigate the disposal process and reduce the overall tool cost of operation. This paper will review the types of purification technologies that are currently available to generate high purity hydrogen suitable for EUV applications. Advantages and disadvantages of each purification technology will be presented. Guidelines on how to select the most appropriate technology for each application and experimental conditions will be presented. A discussion of the most common approaches utilized at the facility level to operate EUV tools along with possible hydrogen recovery strategies will also be reported.

Measurement and control of line edge roughness (LER) is one of the most challenging issues facing patterning technology. As the critical dimensions (CD) of patterned structures decrease, LER of only a few nanometers can negatively impact device performance. Here, Mueller matrix spectroscopic ellipsometry (MMSE) based scatterometry is used to determine LER in periodic line-space structures in 28 nm pitch Si fin samples fabricated by directed selfassembly (DSA) patterning. The optical response of the Mueller matrix (MM) elements is influenced by structural parameters like pitch, CD, height, and side-wall angle (SWA), as well as the optical properties of the materials. Evaluation and decoupling MM element response to LER from other structural parameters requires sensitivity analysis using simulations of optical models that include LER. Here, an approach is developed that quantifies Si fin LER by comparing the optical responses generated by systematically varying the grating shape and measurement conditions. Finally, the validity of this approach is established by comparing the results obtained from top down scanning electron microscope (SEM) images and cross-sectional TEM image of the 28 nm pitch Si fins.

The maximum amount of repulsive force applied to the surface plays a very important role in damage of tip or sample in Atomic Force Microscopy(AFM). So far, many investigations have focused on peak repulsive forces in tapping mode AFM in steady state conditions. However, it is known that AFM could be more damaging in transient conditions. In high-speed scanning, and in presence of 3D nano structures (such as FinFET), the changes in topography appear in time intervals shorter than the response time of the cantilever. In this case, the tip may crush into the sample by exerting much higher forces than for the same cantilever-sample distance in steady state situations. In this study the effects of steep upward steps in topography on the tip-sample interactions have been investigated, and it has been found that the order(s) of magnitude higher forces can be applied. The information on the worst case scenario obtained by this method can be used for selection of operation parameters and probe design to minimize damage in high-speed imaging. The numerically obtained results have been verified with the previous works in steady state regime. Based on this investigation the maximum safe scanning speed has been obtained for a case study.

Electron beam induced surface damage in general, and resist shrinkage in particular, are serious issues in any form of electron beam based metrology. Previous studies investigated dimensional changes that occur in resists that were exposed to electron beams. This work builds on these previous studies to consider changes to the material properties of the exposed resists and other materials using quantitative nano-mechanical mapping scanning probe microscopy. Initial data has shown clearly that there are measurable material differences between pre- and post-electron beam exposure. To study this change iArF photo-resists are exposed to varying electron beam energies and doses. These regions are then measured via SPM for dimensional and material property changes. These changes in the exposed areas are correlated to those predicted by modeled results.