This PDF file contains the front matter associated with SPIE Proceedings Volume 8684, including the Title Page, Copyright Information, Table of Contents, Introduction and Conference Committee listing.

Design for manufacturability (DFM) has become a key enabler of integrated circuit (IC) production over the past decade. In this paper a comprehensive DFM program for IC designs at the 28nm node and beyond is described from the perspective of a fabless design company. Challenges for future technology nodes are also explored.

Conventional resolution enhancement techniques (RET) are becoming increasingly inadequate at addressing the challenges of sub-wavelength lithography. In particular, features show high sensitivity to process variation in low-k₁ lithography. While advanced mask optimization techniques such as process window optical proximity correction (PWOPC) exist to address this, they modify electrical properties of shapes in a way that is incommunicable to the designer. A more design-aware approach for improving printability is to perform retargeting, which is a modification of target layout shapes to improve their process window. Retargeting can be performed rule-based or model-based. The former has fast runtime but is not a scalable technique since rules cannot cover the entire search space of two-dimensional shape configurations, especially with technology scaling. The latter provides more coverage of complex 2-D optical interactions compared to rules, but suffers from high runtime and inability to communicate modified design intent back to the designer. In this paper, we explore an alternative approach to retargeting which overcomes the drawbacks of both these methods. We develop a target optimization method based on knowledge of source and the diffraction pattern of the layout. We demonstrate that target optimization can be performed at fast runtime using just the Fourier transform of the layout. This approach is more scalable than rule-based retargeting, but also allows communication of modified design intent by integration into extraction tools.

Self-aligned double patterning (SADP) has become a promising technique to push pattern resolution limit to sub-22nm technology node. Although SADP provides good overlay controllability, it encounters many challenges in physical design stages to obtain conflict-free layout decomposition. In this paper, we study the impact on placement by different standard cell layout decomposition strategies. We propose a SADP friendly standard cell configuration which provides pre-coloring results for standard cells. These configurations are brought into the placement stage to help ensure layout decomposability and save the extra effort for solving conflicts in later stages.

As the current 193nm ArF immersion lithography technology is approaching its bottleneck, multiple patterning techniques have to be introduced to fulfill the process requirements in the sub-20nm technology node. Among all different patterning techniques, triple patterning lithography (TPL) is one of the major options for 14 nm or 10 nm technology node, which has a substantial requirement on process control and cost control at the same time. Patterning decomposition is the key step for the success of TPL. In the conventional TPL lithography, a constant spacing distance d_min is used to determine whether two nearby features should be on the same mask. However, in reality, the no-print and the best-print scenarios can never be separated by a clear constant number. Indeed, the decomposition criteria is closed related to lithography printing parameters, pattern types, and geometry distances. The conventional spacing rule with a constant number is way too simple. In this paper, we re-evaluate the conventional minimum spacing rule and utilize a local pattern cost model to evaluate our previous optimal TPL algorithm. Given a user specified local pattern aware cost model, our algorithm can easily embed the model into our formulation and compute an optimal solution. This demonstrates the extendability and robustness of our previous TPL algorithm.

Among double patterning techniques, Self-aligned double patterning (SADP) has the advantage of good mask overlay control, which has made SADP a popular double patterning method for sub-32nm technology nodes. However, SADP process places several limitations on design flexibility. This work exploits an alternative post routing approach that has the flexibility to resolve lithography violations without the overhead of repeated rule checking. In addition, it allows for successive refinement in the definition of lithographic violations as the process node matures, and implementation of fixes as localized ECO (Engineering Change Order) operations without needing to reroute the complete design.

A pattern matching methodology that identifies non-decomposition-friendly designs and provides localized guidance for layout-fixing is presented for double patterning lithography. This methodology uses a library of patterns in which each pattern has been pre-characterized as impossible-to-decompose and annotated with a design rule for guiding the layout fixes. A pattern matching engine identifies these problematic patterns in design, which allows the layout designers to anticipate and prevent decomposition errors, prior to layout decomposition. The methodology has been demonstrated on a 180 um² layout migrated from the previous 28nm technology node for the metal 1 layer. Using a small library of just 18 patterns, the pattern matching engine identified 119 out of 400 decomposition errors, which constituted coverage of 29.8%.

In this paper, we propose a new flexible routing method for Self-Aligned Double Patterning (SADP). SADP is one of the most promising candidates for patterning sub-20 nm node advanced technology but wafer images must satisfy tighter constraints than litho-etch-litho-etch process. Previous SADP routing methods require strict constraints induced from the relation between mandrel and trim patterns, so design freedom is unexpectedly lost. Also these methods assume to form narrow patterns by trimming process without consideration of resolution limit of optical lithography. The proposed method realizes flexible SADP routing with dynamic coloring requiring no decomposition to extract mandrel patterns and no worries about coloring conflicts. The proposed method uses realizable trimming process only for insulation of patterns. The effectiveness of the proposed method is confirmed in the experimental comparisons.

As semiconductor manufacturing migrates to more advanced technology nodes, the performance improvement anticipated from scaling has failed to match expectations. This failure is due to the emergence of layout-dependent effects (LDEs) not encountered in the design flow prior 65nm process node. We propose a novel methodology that allows the early detection of LDEs during schematic creation. Different from all previous works, this methodology accurately calculates LDEs by interfacing interactively with a simulator tool. Our research indicates that no previous works suggested the use of “on-the-fly” simulation, using Eldo Interactive, to study LDEs. In fact, the use of Calibre tools [2] has been suggested to help the designer check certain basic electrical constraints (like matching) under the existence of LDEs, by specifying the matching condition as a comment added to the original Pyxis schematic netlist. [1] These comments are then transformed into verification rules that are added and checked by Calibre. The proposed flow is tested on a 40nm OTA design, with results not only as accurate as those previously obtained from post-layout analysis, but also equal to or better speed of execution, demonstrating the practicality of using “on-the-fly” simulation to detect and resolve LDEs early in the design flow.

Given the deployment delays for EUV, several next generation lithography (NGL) options are being actively researched. Several cost-effective NGL solutions, such as self-aligned double patterning through sidewall image transfer (SIT) and directed self-assembly (DSA), in conjunction with process integration challenges, mandate grating-like pattern design. As part of the GRATEdd project, we have evaluated the design cost of grating-based design for ASICs (application specific ICs). Based on our observations we have engineered fundamental changes to the primary ASIC design components to make scaling affordable and useful in deeply scaled sub-20 nm technologies: unidirectional-M1 based standard cells, application-specific smart SRAM synthesis, and statistical and self-healing analog design.

Self-aligned double patterning (SADP) lithography is a leading candidate for 14nm node lower-metal layer fabrication. Besides the intrinsic overlay-tolerance capability, the accurate spacer width and uniformity control enables such technology to fabricate very narrow and dense patterns. Spacer-is-dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. In the SID process, due to uniform spacer deposition, the spacer shape gets rounded at convex mandrel corners, and disregarding the corner rounding issue during SID decomposition may result in severe residue artifacts on device patterns. Previously, SADP decomposition was merely verified by Boolean operations on the decomposed layers, where the residue artifacts are not even identifiable. This paper proposes a model-based verification method for SID decomposition to identify the artifacts caused by spacer corner rounding. Then targeting residue artifact removal, an enhanced SID decomposition flow is introduced. Simulation results show that residue artifacts are removed effectively through the enhanced SID decomposition strategy.

Self-aligned quadruple patterning (SAQP) process is a proven technique for deep nano-scale IC manufacturing, while its mask design and layout decomposition strategy is less intuitive. In this paper, we examine both 2- and 3-mask SAQP process characteristics and develop various decomposition methods to achieve higher feature density and 2-D design flexibility. It is demonstrated that by generating assisting mandrels, SAQP layout decomposition can be degenerated into a SADP decomposition problem for which mature algorithms already exist in our EDA industry. Moreover, a spacer-expansion mask concept is introduced and a grouping/coloring algorithm to assign feature colors is developed for 3-mask SAQP layout decomposition. Finally, several 2-D layouts are successfully decomposed, showing the functionality of the decomposition method we proposed.

Self-aligned sextuple patterning (SASP) is a promising technique to scale down the half pitch of IC features to sub- 10nm region. In this paper, the process characteristics and decomposition methods of both positive-tone (pSASP) and negative-tone SASP (nSASP) techniques are discussed, and a variety of decomposition rules are studied. By using a node-grouping method, nSASP layout conflicting graph can be significantly simplified. Graph searching and coloring algorithm is developed for feature/color assignment. We demonstrate that by generating assisting mandrels, nSASP layout decomposition can be degenerated into an nSADP decomposition problem. The proposed decomposition algorithm is successfully verified with several commonly used 2-D layout examples.

Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently LELEEC process was proposed to overcome the limitations, where the third mask is used to generate the end-cuts. In this paper we propose the first study for LELEEC layout decomposition. Conflict graphs and end- cut graphs are constructed to extract all the geometrical relationships of input layout and end-cut candidates. Based on these graphs, integer linear programming (ILP) is formulated to minimize the con ict number and the stitch number.

As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits; subresolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. AF placement algorithms can be categorized broadly as either rule-based (RB), model-based (MB). However, combining these different algorithms into new integrated solutions may enable a more optimal overall solution. RBAF is the baseline AF placement method for many previous technology nodes. Although RBAF algorithm complexity limits its use with very extreme illumination, RBAF is still a powerful option in certain scenarios. One example is for repeating patterns in memory arrays. RBAF algorithms can be finely optimized and verified experimentally without the building of complex models. RBAF also guarantees AF placement consistency based only on the very local geometric environment, which is important in applications where consistent signal propagation is of critical importance. MBAF algorithms deliver the ability to reliably place assist features for enhanced process window control across a wide variety of layout feature configurations and aggressive illumination sources. These methods optimize sophisticated AF placement to improve main feature PW but without performing full main feature OPC. The flexibility of MBAF allows for efficient investigations of future technology nodes as the number of interactions between local layout features increases beyond what RBAF algorithms can effectively support Based on hybrid approach algorithms combining features of the different algorithms using both RBAF and MBAF methods, the generation and placement of SRAF can be a good alternative. Combining of two kinds of SRAF placement options might result in relatively improved process window compared to an independent approach since two methods are capable of supplement each other with a complementary advantages. In this paper we evaluate the impact of SRAF configuration to pattern profile as well as CD margin window and manufacturing applications of MBAF and Hybrid approach algorithms compared to the current OPC without AF. As a conclusion, we suggest methodology to set up optimum SRAF configuration using these AF methods with regard to process window.

A compact model is developed to study the fin-width roughness (FWR) induced device variability and its impacts on FinFET performance. The perturbation theory is applied to obtain the analytic solution to nonlinear Poisson’s equation by treating FWR as a small deviation/perturbation from the ideal (flat) fin boundary. High accuracy of this compact model is verified with TCAD simulations. Both model calculation and TCAD simulation results show that FWR variation significantly affects FinFET device behavior. The conventional short-channel model is inaccurate to describe the FWR effects. Several types of FWR functions are studied and important device parameters such as V_t.sat, V_t.lin, DIBL are extracted from TCAD simulations, all of which are found sensitive to FWR variation.

Lithography pattern line-edge roughness (LER) has important device implications such as device variability, current leakage and dielectric breakdown. This study characterizes how LER impacts device performance in terms of spatial frequency distribution. In the front-end of device fabrication, it is shown that low-frequency fin LER causes large FinFET device variability and becomes more severe for advanced device nodes. The effect of the dielectric/metal line LER spatial frequency distribution on the dielectric breakdown and resistance-capacitance (RC) variation for interconnects was studied. It is found that low-frequency LER introduces the highest electrostatic field due to surface charge localization, resulting in an increase in the occurrence of a dielectric breakdown path. The critical frequency range that contributes the most to device variability also evolves with device nodes. On the other hand, RC variation shows negligible dependency on LER amplitude and frequency.

The impacts of self-aligned triple patterning (SATP) and self-aligned quadruple patterning (SAQP) process variability on SRAM circuit performance are studied in this paper. Different types of SRAM circuit variability such as intra-cell and inter-cell variability are discussed. Spatially periodic variation patterns of a SRAM array fabricated with SATP process is identified, while spatial variation of SAQP based SRAM array is found to be less significant. Statistical TCAD simulations are carried out to examine the process variability induced fluctuation of SRAM circuit performance. It is found that SRAM static noise margin (SNM) shrinks with increased variations in line-width roughness and CD, especially when the technology node is scaled down. Despite the SATP/SAQP process variability and the related SNM reduction, our simulations show that the induced fluctuation of SRAM circuits is still manageable. It is also confirmed that circuit stability and manufacturing yield of SAQP based SRAM are better than SATP based SRAM.

Time-dependent dielectric breakdown (TDDB) is becoming a critical reliability issue, since the electric field across dielectric increases as technology scales. Moreover, dielectric reliability is aggravated when interconnect spacings vary due to (vias and wires) mask misalignment. Although dielectric reliability can be mitigated by a larger interconnect pitch, such a guardband leads to significant area overhead. In this paper, we propose to improve dielectric reliability through a post-layout optimization. In the layout optimization, we locally shave and/or shift a fraction of wire width to increase the spacing between wires, and/or between adjacent-layer vias and wires. Our experimental results show that the layout optimization can improve interconnect lifetime by 9% to 10%. Separately, we also propose a signal-aware chip-level TDDB reliability estimation method which estimates TDDB stress time of interconnects using net signals obtained from a vectorless analysis. By using the signal-aware analysis method, we show that chip-level TDDB lifetime is approximately twice that obtained using the conventional analysis approach which assumes interconnects are always under electrical stress.

In this paper, we analyze advantages and disadvantages of various extraction-based techniques applied to colorless and colored double patterning layouts. Two techniques are presented: (1) an effective dielectric constant-based technique, which modifies the dielectric constants to obtain an equivalent capacitance change as would result from mask misalignment, and (2) an offset-based, less conservative technique, that proposes the use of custom corners. Experimental results illustrate the impact of double patterning on the parasitics, and allow us to compare these techniques.

As technology nodes scale beyond 20nm node, design complexity increases and printability issues become more critical and hard for RET techniques to fix. It is now mandatory for designers to run lithography checks prior to tape out and acceptance by the foundry. As lithography compliance became a sign-off criterion, lithography hotspots are increasingly treated like DRC violations. In the case of lithography hotspot, layout edges that should be moved to fix the hotspot are not necessarily the edges directly touching it. As a result of that, providing the designer with a suggested layout movements to fix the lithography hotspot is becoming a necessity. Software solutions generating hints should be accurate and fast. In this paper we are presenting a methodology for providing hints to the designers to fix Litho-hotspots in the 20nm and beyond.

Integrated circuits suffer from serious layout printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to help reducing these systematic sub-wavelength lithography variations. From CAD point of view, regular layouts can be treated as repeated patterns that are arranged in arrays. In most modern mask synthesis and verification tools, cell based hierarchical processing has been able to identify repeating cells by analyzing the design’s cell placement; however, there are some routing levels which are not inside the cell and yet they create an array-like structure because of the underlying topologies which could be exploited by detecting repeated patterns in layout thus reducing simulation run-time by simulating only the representing cells and then restore all the simulation results in their corresponding arrays. The challenge is to make the array detection and restoration of the results a very lightweight operation to fully realize the benefits of the approach. A novel methodology for detecting repeated patterns in a layout is proposed. The main idea is based on translating the layout patterns into string of symbols and construct a “Symbolic Layout”. By finding repetitions in the symbolic layout, repeated patterns in the drawn layout are detected. A flow for layout reduction based on arrays-detection followed by pattern-matching is discussed. Run time saving comes from doing all litho simulations on the base-patterns only. The pattern matching is then used to restore all the simulation results over the arrays. The proposed flow shows 1.4x to 2x run time enhancement over the regular litho simulation flow. An evaluation for the proposed flow in terms of coverage and run-time is drafted.

In today’s semiconductor industry, both the pure-play and independent device manufacturer (IDM) foundries are constantly and rigorously competing for market share. The acknowledged benefit for customers who partner with these foundries includes a reduced cost-of-ownership, along with the underwritten agreement of meeting or exceeding an aggressive time-to-market schedule. Because the Semiconductor Manufacturing International Corporation (SMIC) is one of the world-wide forerunners in the foundry industry, one of its primary concerns is ensuring continual improvement in its fab’s turnaround time (TAT), especially given that newer technology nodes and their associated processes are increasing in complexity, and consequently, in their time-to-process. In assessing current runtime data trends at the 65nm and 40nm technology nodes, it was hypothesized that hardware and software utilization improvements could accomplish a reduced overall TAT. By running an experiment using the Mentor Graphics Calibre® Cluster Manager (CalCM) software, SMIC was able to demonstrate just over a 30% aggregate TAT improvement in conjunction with a greater than 90% average utilization of all hardware resources. This paper describes the experimental setup and procedures that predicated the reported results.

This paper addresses a methodology for building robust design rules by using design based metrology (DBM). Conventional method for building design rules has been using a simulation tool and a simple pattern spider mask. At the early stage of the device, the estimation of simulation tool is poor. And the evaluation of the simple pattern spider mask is rather subjective because it depends on the experiential judgment of an engineer. In this work, we designed a huge number of pattern situations including various 1D and 2D design structures. In order to overcome the difficulties of inspecting many types of patterns, we introduced Design Based Metrology (DBM) of Nano Geometry Research, Inc. And those mass patterns could be inspected at a fast speed with DBM. We also carried out quantitative analysis on PWQ silicon data to estimate process variability. Our methodology demonstrates high speed and accuracy for building design rules. All of test patterns were inspected within a few hours. Mass silicon data were handled with not personal decision but statistical processing. From the results, robust design rules are successfully verified and extracted. Finally we found out that our methodology is appropriate for building robust design rules.