This PDF file contains the front matter associated with SPIE Proceedings Volume 8327, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

The upcoming 14nm logic node will require lithographic patterning of complex layout patterns with minimum pitches of approximately 44nm to 50nm. This requirement is technically feasible by reusing existing 20nm litho-etch-litho-etch (LELE) double patterning (DPT) methods with very strong restricted design rules. However, early indications are that the cost-effective design and patterning of these layouts will require lithographic methods with additional resolution, especially in two-dimensional configurations. If EUV lithography reaches maturity too late, the 14nm logic node will need other lithographic techniques and the corresponding physical design rules and EDA methodologies to be available. Triple patterning technology (TPT) is a strong option for 14nm node logic on both hole and line-space pattern layers. In this paper we study major implications of a 14nm logic TPT lithographic solution upon physical design, design rules, mask synthesis/EDA algorithms and their process interactions.

A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic process technologies. A noble technology combined a number of potential confliction of DFM techniques into a comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5% improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the positive effect of the DFM techniques.

In this paper, we study the problem of placement-level layout optimization for designs built from cells with unidirectional self-aligned double patterning (SADP) metal-1 interconnect. Our goal is to minimize the number of potential bridging hotspots in design layouts using predictive, machine learning-based models and applying incremental placement adjustments. In the first part of the paper, we explain how to build layout pattern classification models using machine learning methods. Our support vector machine (SVM)-based model predicts a given layout clip as either robust or non-robust. In the second part of the paper, we apply the predictive models to placement-level optimization. Our algorithm identifies and eliminates potential hotspots in standard cell based layout by modifying local cell position.

Double patterning with 193nm optical lithography is inevitable for technology scaling before EUV is ready. In general, there are two major double patterning techniques (DPT): Litho-Etch-Litho-Etch (LELE) and sidewall spacer technology, a Self-Aligned Double Patterning technique (SADP). So far LELE is much more mature than SADP in terms of process development and design flow implementation. However, SADP has stronger scaling potential than LELE due to its smaller design rules on tip-tip and tip-side as well as its intrinsic self-align property. In this paper, we will explain in detail about how to enable a SADP-friendly design flow from multiple perspectives: design constructs, design rules, standard cell library and routing. In addition, the differences between SADP and LELE in terms of design, scaling capability and RC performance will be addressed.

Double patterning using 193nm immersion has been adapted as the solution to enable 2x nm technology nodes until the arrival of EUV tools. As a result the past few years have seen a huge effort in creating double patterning friendly design flows. These flows have so far proposed a combination of decomposition rules at cell level and/or at placement level as well as sophisticated decomposition tools with varying density, design iteration and decomposition complexity penalties. What is more, designers have to familiarize themselves with double patterning challenges and decomposition tools. In this paper an alternative approach is presented that allows the development of dense standard cells with minimal impact on design flow due to double patterning. A real case study is done on 20nm node first metal layer where standard cells are designed without considering decomposition restrictions. The resulting layout is carefully studied in order to establish decomposition or color rules that can map the layout into two masks required for double patterning but without the need of complex coloring algorithms. Since the rules are derived from a decomposition unaware design they do not in return impose heavy restrictions on the design at the cell or placement level and show substantial density gains compared to previously proposed methods. Other key advantages are a simplified design flow without complex decomposition tools that can generate a faster time to market solution all at the same time keeping designers isolated from the challenges of the double patterning. The derived design rules highlight process development path required for design driven manufacturing.

A pattern-based methodology for guiding the generation of DPT-compliant layouts using a foundry-characterized library of "difficult to decompose" patterns with known corresponding solutions is presented. A pattern matching engine scans the drawn layout for patterns from the pattern library. If a match were found, one or more DPT-compliant solutions would be provided for guiding the layout modifications. This methodology is demonstrated on a sample 1.8 mm² layout migrated from a previous technology. A small library of 12 patterns is captured, which accounts for 59 out of the 194 DPT-compliance check violations examined. In addition, the methodology can be used to recommend specific changes to the original drawn design to improve manufacturability. This methodology is compatible with any physical design flows that use automated decomposition algorithms.

Design rules (DRs) are the primary abstraction between design and manufacturing. The optimization of DRs to achieve the correct tradeoff between scaling and yield is a key step in developing a new technology node. In this work we propose a design-of-experiments based framework to optimize DRs, where layouts are generated for different DR values using compaction. By analyzing the impact of DRs on layout scaling, we propose a novel Boolean minimization based approach to reduce the number of layouts that need to be generated through compaction. This methodology provides an automated approach to analyze several DRs simultaneously and discover area-critical DRs and DR interactions. We apply this methodology to middle-of-line (MOL) and Metal1 layer design rules for a commercial 20nm process. Our methodology results in 10 - 10⁵ x reduction in the number of layouts that need to be generated through compaction, and demonstrates the impact of MOL and Metal1 DRs on the area of some standard cell layouts.

Design For Manufacturing (DFM) is becoming essential to ensure good yield for deep sub micron technologies. As design rules cannot anticipate all manufacturing marginalities resulting from problematic 2D patterns, the latter has to be addressed at design level through DFM tools. To deploy DFM strategy on back end levels, STMicroelectronics has implemented a CAD solution for lithographic hotspots search and repair. This allows the detection and the correction, at the routing step, of hotspots derived from lithographic simulation after OPC treatment. The detection of hotspots is based on pattern matching and the repair uses local reroute ability already implemented in Place and Route (PnR) tools. This solution is packaged in a Fast LFD Kit for 28 nm technology and fully integrated in PnR platforms. It offers a solution for multi suppliers CAD vendors routed designs. To ensure a litho friendly repair, the flow integrates a step of local simulation of the rerouted zones. This paper explains the hotspots identification, their detection through pattern matching and repair in the PnR platform. Run time, efficiency rate, timing and RC parasitic impacts are also analyzed.

We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

As IC technologies shrink and via defects remain the same size, the probability of via defects increases. Redundant via insertion is an effective method to reduce yield loss related to via failures, but a large number of extremely complex design rules make efficient automatic via insertion difficult. This paper introduces an automatic redundant via insertion flow which is capable of adopting new technologies and complex design rules extremely quickly. Runtime and efficiency are optimized through a smart insertion scheduling technique. Our experiments show that it efficiently improves redundant via percentage, making designs more robust against via defects.

As the metal pitch continues to shrink, it becomes inefficient, if not impossible, to use traditional via redundancy schemes at and below the 14 nm node. Double-cut vias and via bar connections will either block many adjacent routing resources or make it impossible to pattern at these advanced technologies nodes. In this paper we examine a scalable via redundancy strategy based on local loops. We evaluate the yield and timing impact of local loops and use a 14 nm standard cell library and functional block designs to assess the design cost of local loops. Furthermore, lithography contours and process window simulations are used to demonstrate the manufacturability of this structure. With supporting EDA tools and design-technology co-optimization (DTCO), local loops will become an important via redundancy topology at sub-20nm nodes.

In the SPIE Microlithography DFM conference, the number of papers related to physical design has been steadily increasing in the last few years. Since the majority of the audience in this conference has a background in lithography, some of the physical design-related terminologies and methods described in the presentation may be hard to understand. This paper gives a basic introduction to the physical design that is applicable to lithographers. The goal of the paper is not to enable a lithographer to begin working as a physical designer. Instead, it is to help lithographers understand some of the basics of physical design, so that they can better comprehend other DFM papers presented at the conference.

Variability in performance and power of 40nm and 28nm CMOS cells is highly dependent on the context in which the cells are used. In this study, the effects of context on a number of clock tree cells from standard cell libraries have been investigated. The study also demonstrated how the Litho Electrical Analyzer (LEA) tool from Cadence® is used to analyze the context-dependent variability. During the study, it was observed that the device characteristics including Vth, Idsat, and Ioff are significantly affected by Layout Dependent Effects (LDE), resulting in variability of performance and power of standard cells. Moreover, the dummy diffusions acting as mitigation process offered limited improvement for the effects of context. On the other hand, the cell level variability due to stress was analyzed. So, it is suggested that the relative variability of a cell is determined by its size and structure, and the variability can be improved to some extent by editing the cells' structure. Based on the analysis of the physical sources and properties of LDE, this paper presents a set of layout guidelines for mitigating layout dependent variability of 40 and 28nm CMOS cells.

With the transition to the 32/28 nm platform parameter variations of device and circuit parameters are becoming increasingly important for performance, reliability and yield. Based on a sensitivity analysis, the paper compares the impact of lithography and CMP on circuit parameter variations. Coupling capacitances that can be described by geometrical parameters such as line width and thickness impact signal delay, crosstalk noise and power consumption. Variations of these capacitances thus contribute significantly to parametric yield loss. Based on field solver simulations the most critical devices and interconnections can be identified, providing valuable input during the chip design cycle.

In advanced process technologies, a layout context (that is the layout surrounding a cell) can impact the timing and leakage of a cell due to stress induced by the layout features, Well Proximity Effect (WPE), and other layout-dependent effects. The Litho Electrical Analyzer (LEA) tool from Cadence® is used to perform an analysis on 28nm standard cells in order to assess the variation in the timing and leakage characteristics due to the layout-dependent effects. During the study, the substantial leakage and timing shifts due to the layout contexts were observed. Moreover, the leakage variations were measured, and different levels of correlation of shifts across the PMOS transistors and the corresponding non-correlation between the PMOS and NMOS devices were also observed. Due to cancellation of the positive and negative variations in leakage, and because the leakage variation in Silicon is large, it is recommended to include a flat leakage margin without having added complexity to the leakage analysis flow. In addition, the timing was observed that impacts the slew and load conditions and identified conditions where shifts would be the greatest. Also, several mitigations were identified to reduce the variability of timing due to a context. This paper begins with describing the tools and methodologies used for the performance and power analysis of standard cells. It also explains the delay impact analysis, present delay simulation, Silicon-based results, and proposes guidelines to mitigate the un-modeled LDEs.

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose an efficient variabilityaware compact model characterization methodology based on the linear propagation of variance. Hierarchical spatial variability patterns of selected compact model parameters are directly calculated from transistor array test structures. This methodology has been implemented and tested using transistor I-V measurements and the EKV-EPFL compact model. Calculation results compare well to full-wafer direct model parameter extractions. Further studies are done on the proper selection of both compact model parameters and electrical measurement metrics used in the method.

The 14 nm node is seeing the dominant use of three-dimensional FinFET architectures, local interconnects, multiple patterning processes and restricted design rules. With the adoption of these new process technologies and design styles, it becomes necessary to rethink the standard cell library design methodologies that proved successful in the past. In this paper, we compare the design efficiency and manufacturability of standard cell libraries that use either unidirectional or bidirectional Metal 1. In contrast to previous nodes, a 14 nm 9-track unidirectional standard cell layout results in up to 20% lower energy-delay-area product as compared to the 9-track bidirectional standard cell layout. Manufacturability assessment shows that the unidirectional standard cell layouts save one exposure on Metal 1, reduces process variability by 10% and layout construct count by 2-3X. As a result, the unidirectional standard cell layout could serve as a key enabler for affordable scaling.

Double patterning (DP) in a litho-etch-litho-etch (LELE) process is an attractive technique to scale the K₁ factor below 0.25. For dense bidirectional layers such as the first metal layer (M1), however, density scaling with LELE suffers from poor tip-to-tip (T2T) and tip-to-side (T2S) spacing. As a result, triple-patterning (TP) in a LELELE process has emerged as a strong alternative. Because of the use of a third exposure/etch, LELELE can achieve good T2T and T2S scaling as well as improved pitch scaling over LELE in case further scaling is needed. TP layout decomposition, a.k.a. TP coloring, is much more challenging than DP layout decomposition. One of the biggest complexities of TP decomposition is that a stitch can be between different two-mask combinations (i.e. first/second, first/third, second/third) and, consequently, stitches are color-dependent and candidate stitch locations can be determined only during/after coloring. In this paper, we offer a novel methodology for TP layout decomposition. Rather than simplifying the TP stitching problem by using DP candidate stitches only (as in previous works), the methodology leverages TP stitching capability by considering additional candidate stitch locations to give coloring higher flexibility to resolve decomposition conflicts. To deal with TP coloring complexity, the methodology employs multiple DP coloring steps, which leverages existing infrastructure developed for DP layout decomposition. The method was used to decompose bidirectional M1 and M2 layouts at 45nm, 32nm, 22nm, and 14nm nodes. For reasonably dense layouts, the method achieves coloring solutions with no conflicts (or a reasonable number of conflicts solvable with manual legalization). For very dense and irregular M1 layouts, however, the method was unable to reach a conflict-free solution and a large number of conflicts was observed. Hence, layout simplifications for the M1 layer may be unavoidable to enable TP for the M1 layer. Although we apply the method for TP, the method is more general and can be applied for multiple patterning with any number of masks.

A hybrid self-aligned triple and negative-tone double patterning (HTDP) technique is proposed to achieve improved resolution and quasi-2D IC design flexibility at lower cost. Critical challenges of HTDP process and its key design issues such as overlay, layout decomposition and synthesis are investigated, and possible design solutions are discussed. It is shown that using mandrel (including assisting mandrel) and spacer engineering, HTDP on-grid layout design is a promising approach to break the limitation of 1-D gridded design. Efficient formulation of HTDP layout decomposition/synthesis into a Boolean satisfactory problem is demonstrated. Moreover, by considering geometric constraints of HTDP layout and several process related assumptions, it is possible to significantly reduce the number of layout features and Boolean input variables. Several examples of 2-D layout are used to demonstrate the process of HTDP decomposition/synthesis, as well as the simplification of its algorithm to reduce runtime. Specifically, preliminary results from implementation of a 2-mask HTDP design for patterning a 2-D dense line/space array with pads are reported.

Lithography development has become extremely computationally intensive. For a particular technology node being developed, it is critical to determine the optimum source and OPC/RET for each layer. In this paper we present a flexible new computation system for automation of source, OPC and RET optimization of advanced lithography layers. Of course, before determining the optimum source/RET/OPC of any layer, it is equally critical to determine the design rules which can be manufactured at a particular technology node. The design rule computational lithography problem is a superset of the source/OPC/RET optimization problem. With an automated methodology, time for process development can be reduced dramatically if a process development engineer can determine the design rules through accurate, automated simulation of the entire flow.

As a result, low fidelity patterns due to process variations can be detected and eventually corrected by designers as early in the tape out flow as right after design rule checking (DRC); a step no longer capable to totally account for process constraints anymore. This flow has proven to provide a more adequate level of accuracy when correlating systematic defects as seen on wafer with those identified through LFD simulations. However, at the 32nm and below, still distorted patterns caused by process variation are unavoidable. And, given the current state of the defect inspection metrology tools, these pattern failures are becoming more challenging to detect. In the framework of this paper, a methodology of advanced process window simulations with awareness of chip topology is presented. This method identifies the expected focal range different areas within a design would encounter due to different topology.

The history of dummy fill in semiconductor design goes back many generations of technology development. From its start with planarization requirements, fill needs have expanded across many wafer process manufacturing steps. They include lithography, etch, deposition, surface anneal, and device performance with stress analysis. Modern EDA tools have advanced to automatically place dummy shapes to meet these new requirements. These include placing multi-layer cell constructs, and multi-layer analysis during placement. New fill requirements have affected downstream flows such as extraction and timing analysis, physical verification, and RET flows. Further enhancements to fill tools and flows are under development to meet the total DFM needs for the next generations of chips.

As patterning for advanced processes becomes more challenging, designs must become more process-aware. The conventional approach of running lithography simulation on designs to detect process hotspots is prohibitive in terms of runtime for designers, and also requires the release of highly confidential process information. Therefore, a more practical approach is required to make the In-Design process-aware methodology more affordable in terms of maintenance, confidentiality, and runtime. In this study, a pattern-based approach is chosen for Process Hotspot Repair (PHR) because it accurately captures the manufacturability challenges without releasing sensitive process information. Moreover, the pattern-based approach is fast and well integrated in the design flow. Further, this type of approach is very easy to maintain and extend. Once a new process weak pattern has been discovered (caused by Chemical Mechanical Polishing (CMP), etch, lithography, and other process steps), the pattern library can be quickly and easily updated and released to check and fix subsequent designs. This paper presents the pattern matching flow and discusses its advantages. It explains how a pattern library is created from the process weak patterns found on silicon wafers. The paper also discusses the PHR flow that fixes process hotspots in a design, specifically through the use of pattern matching and routing repair.

Layout verification is essential in the cutting-edge generation. Generally, it uses a lithography simulation (Lithography Compliance Check: LCC) and requires a lot of calculation time. In order to reduce LCC time, we propose a clean pattern matching method by means of a "clean pattern library". The proposed method searches for patterns without hotspots (clean patterns) which usually occupy the most of the chip area. The conventional hotspot pattern matching method has no guarantee that unmatched area is hotspot-free, so LCC is usually applied to the unmatched area. On the other hand, the proposed matching method searches for "clean" patterns so that most of the area need not to be verified. As a result, LCC time can be reduced. This paper shows the detailed flow of the proposed matching method. We present the experimental results of layout verification in our 40nm system LSI designs and the effectiveness of the proposed method is confirmed.

This paper addresses the framework for building critical recommended rules and a methodology for devising scoring models using simulation or silicon data. Recommended rules need to be applied to critical layout configurations (edge or polygon based geometric relations), which can cause yield issues depending on layout context and process variability. Determining of critical recommended rules is the first step for this framework. Based on process specifications and design rule calculations, recommended rules are characterized by evaluating the manufacturability response to improvements in a layout-dependent parameter. This study is applied to critical 20nm recommended rules. In order to enable the scoring of layouts, this paper also discusses a CAD framework involved in supporting use-models for improving the DFM-compliance of a physical design.

Self-Aligned Double Patterning (SADP) has become one of the most promising processes for 20nm node technology and beyond. Despite its robustness against overlay, it is a challenging process for designers since predicting the wafer image instantly is almost impossible. Self-Aligned Quadruple Patterning (SAQP) is also critical technology for sub-10nm process but more complex than SADP, so it is too difficult to design a layout intuitively. Needless to say designing layout by applying N times sidewalls intuitively is impossible for almost everyone. In this paper, we clarify a new intuitive principle for SADP layout. The principle uses "Base patterns" painted in different two colors interchangeably. The proposed method enables us to design SADP layout simply by connecting and cutting fundamental pattern arbitrarily with a few restrictions. Another benefit is that either of two colors in the pattern can be used as mandrel. We can apply the principle to not only SAQP but also N times sidewall processes. Considering these advantages, layout formed by sidewall process becomes designer-friendly.

This paper presents the requirements for the Design for Manufacturability (DFM) checks such as lithography, and Chemical and Mechanical Polishing (CMP) at 28nm technology node, and the need to perform these DFM checks, early in the design phase and with minimum overhead. As a result, this reduces the risk of uncovering some DFM issues at the design tape out time when the changes in a design become expensive. Because IP blocks can be targeted to multiple designs, it is a key requirement that the lithography and CMP checks are accurate and designer-friendly and are easily applied at block-level. This paper describes the block-based methodology that allows the IP designers to perform quickly a comprehensive DFM analysis, including lithography and long-range CMP effects. This paper also explains the integration of the DFM checks into the design flow and correlation results between the block and chip-level checks.

This paper shares the details of the Yield Enhancements that were done at 28nm full chip level sharing the complexity involved in implementing such a flow and then the verification challenges involved , e.g., at mask data preparation. We discuss and present the algorithm used to measure the efficiency of the tool, explaining why we used this algorithm while sharing some alternate algorithms possible. We also share the detailed statistics regarding run time, machine resource, data size, polygon counts etc. We also present good techniques used by us for efficient flow management involved in large complex 28nm chips.

As semiconductor process technology scales down to sub 30nm process node and beyond dimensions, the printability and process window of the lithographic patterns are seriously reduced due to the fundamental limit of the lithography and process variations. In this paper, we introduce a various analysis methodology of pattern variability for higher device performance using with applications of DBV (Design Based Verification). Pattern variability is affected by both pattern process margins and electrical margins such as distribution of gate length. Even if post lithography verification would carry out after model based OPC, Pattern variability is increased not only unpredictable OPC hotspots but also unanticipated hotspots by AEI loading skew in full-chip. Secondly, electrical hotspots which are extracted by tail distributions of gate length are not always reliable enough to represent critical path with gate length of full-chip. We constructed New OCV extraction flow with a full-chip pattern classification that is required for both gate distribution accuracy and analysis of gate tail patterns. In this report, we investigated about the relationship between a pattern feature and pattern distribution of transistor length.

As promising paths to break the diffraction limit of optical lithography, several self-aligned multiple patterning (SAMP) techniques have been proposed to improve the resolution capability recently. In this paper, we show that SATP (selfaligned triple patterning) process variations differ significantly from conventional optical lithography process. It is found that mandrels fabricated by a SATP process usually come up with worse line-width roughness (LWR) and critical-dimension uniformity (CDU) than spacers do. In addition to that, the gap space between two neighboring spacers is often accompanied with a poor CDU. Similar to SATP process, the self-aligned quadruple patterning (SAQP) technique also brings its own characteristics of process variability along with the scaling capability. SAMP process variability (such as intra-cell variability and process multi-modality) and their impacts on device performance of the multiple-gate MOSFETs are discussed. Moreover, we develop an analytic double-gate MOSFET model to study the effects of LWR on both fin thickness and gate misalignment. Numerical simulations are carried out to verify the accuracy of our simplified model. This analytic approach provides an efficient method for compact modeling of LWR induced device variations.

We developed an effective method for evaluating the correlation of shape of Litho and Etching pattern. The purpose of this method, makes the relations of the shape after that is the etching pattern an index in wafer same as a pattern shape on wafer made by a lithography process. Therefore, this method measures the characteristic of the shape of the wafer pattern by the lithography process and can predict the hotspot pattern shape by the etching process. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used wafer CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and lithography management, and this has a big impact on the semiconductor market that centers on the semiconductor business. 2-dimensional shape of wafer quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. In this study, we conducted experiments for correlation method of the pattern (Measurement Based Contouring) as two-dimensional litho and etch evaluation technique. That is, observation of the identical position of a litho and etch was considered. It is possible to analyze variability of the edge of the same position with high precision.

The need to quickly and flexibly characterize the design manufacturability increases as circuit design scales beyond the 22nm node. Improvements in design practices and design software are enabling this process. The use of carefully characterized design subunits (cells) in the general assembly of the chip is one way to ensure that products are optimized for these increasingly difficult lithographic process challenges. Additionally, software for assessing design robustness has been enhanced to deal with ever more complex resolution enhancement techniques. State of the art simulator and verification tool sets provide the necessary step of creating simulation contours and process variability bands upon which various checks can then be performed. The construction of these contours and bands is often hidden from the user as traditional single or double exposure processes of one or two masks are assumed to be used to create the final layout pattern.

Resolution enhancement techniques (RET) such as optical proximity correction (OPC) has become an integral part of the fabrication of integrated circuits to maintain the edge placement integrity of the original circuit design. Conventional OPC schemes are usually shape driven and full chip based, resulting in unpredictability in electrical behavior and huge computational effort. To overcome these drawbacks, a new OPC methodology which is electrically driven and based on cell-wise optimization is proposed. Simulation results when compared to conventional OPC approaches in the literature demonstrate better timing accuracy with reduced mask cost. Depending of the circuit test-set, an average run-time improvement between 3 to 8 times is achieved for circuit size with 100 - 400 cells. Further improvements can be obtained by adopting a hybrid approach by only optimizing the timing performance of critical paths. For the hybrid approach, better timing accuracy can be achieved while incurring little penalty on mask cost.

Lithography and stress effects cause Layout Dependent Variability (LDV), which results in unexpected and unaccounted timing variations. Because standard cells yield unpredicted timing variation due to context differences, the LDV methodology includes the Cell Context Analysis (CCA) flow that provides designers a comprehensive framework to optimize the design layouts and tune the cell's electrical performance. Conventional static timing analysis tools do not incorporate the electrical impact due to nearby context proximity. The LDV methodology includes an Advanced Timing Analysis (ATA) flow that accounts for the electrical impact of cell contexts, which provides more accurate timing results and identifies new timing violations on critical paths. This paper presents the electrical DFM (eDFM) methodologies developed by GLOBALFOUNDRIES using Cadence LEA (Litho Electrical Analyzer) at 28nm technology node. The paper also discusses about the CCA results for more than 40 contexts of each cell and reports mean delay variations of 3% or more.

Despite great effort before design tapeout, there are still some pattern related systematic defects showing up in production, which impact product yield. Through various check points in the production life cycle endeavor is made to detect these defective patterns. It is seen that apart from the known defective patterns, slight variations of polygon sizes and shapes in the known defective patterns also cause yield loss. This complexity is further compounded when interactions among multiple process layers causes the defect. Normally the exact pattern matching techniques cannot detect these variations of the defective patterns. With the currently existing tools in the fab it is a challenge to define the 'sensitive patterns', which are arbitrary variations in the known 'defective patterns'. A design based approach has been successfully experimented on product wafers to detect yield impacting defects that greatly reduces the TAT for hotspot analysis and also provides optimized care area definition to enable high sensitivity wafer inspection. A novel Rule based pattern search technique developed by Anchor Semiconductor has been used to find sensitive patterns in the full chip design. This technique allows GUI based pattern search rule generation like, edge move or edge-to-edge distance range, so that any variations of a particular sensitive pattern can be captured and flagged. Especially the pattern rules involving multiple process layers, like M1-V1-M2, can be defined easily using this technique. Apart from using this novel pattern search technique, design signatures are also extracted around the defect locations in the wafer and used in defect classification. This enhanced defect classification greatly helps in determining most critical defects among the total defect population. The effectiveness of this technique has been established through design to defect correlation and SEM verification. In this paper we will report details of the design based experiments that were successfully run on multiple process layers in production device.

Current metal integration process normally uses hard mask for dry etch process instead of resist to compensate thin resist thickness. As the pattern size becomes smaller, thinner resist thickness is required to get sufficient lithography process window. But this trend increases a risk of systematic hard defect like the metal line bridge in damascene process because of consumption in dielectric material during dry etch process. The sub-32nm patterning with the single exposure is almost on the edge with the 193nm immersion lithography. The smaller lithography CD makes the aerial image contrast worse, which means higher DC level in the unexposed area. This higher DC level, latent image, can sacrifice the resist thickness in the unexposed area and this recessed resist thickness is very harmful for the etch process with the current hard mask which may induce the metal line bridge. Although OPC verification step checks potential hot spot during mask type out flow, there is no predictable method to detect systematic potential defects described above. In this paper, we proposed a new method to detect such potential defects and discussed the performance with wafer result. With this predictable model based search method, the robust patterning process in the sub-32nm node can be developed.

A Double Patterning Technology (DPT)-aware scoring methodology that systematically quantifies the quality of DPTcompliant layout designs is described. The methodology evaluates layouts based on a set of DPT-specific metrics that characterizes layout-induced process variation. Specific metrics include: the spacing variability between two adjacent oppositely-colored features, the density differences between the two exposure masks, and the stitching area's sensitivity to mask misalignment. These metrics are abstracted to a scoring scale from 0 to 1 such that 1 is the optimum. This methodology provides guidance for opportunistic layout modifications so that DPT manufacturability-related issues are mitigated earlier in design. Results show that by using this methodology, a DPT-compliant layout improved from a composite score of 0.66 and 0.78 by merely changing the decomposition solution so that the density distribution between the two exposure masks is relatively equal.