This PDF file contains the front matter associated with SPIE Proceedings Volume 7970, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

Nanoimprint lithography (NIL) has been expected as a low cost lithography solution as well as pattern shrinking capability with superior Critical Dimension (CD) uniformity for several years. However, NIL had been considered having difficulty to be established as mass-production technology, unless the challenge of defectivity control is overcome. The defects of NIL are classified into the non-fill defect, the template defect, and the plug defect. In order to reduce these defects, establishment of the technical infrastructures is important with the innovations of equipment, material, and template technologies. Recently, the investment to lithography becomes heavier burden for a semiconductor device maker, as lithography technology has been more difficult for further pattern shrinking. Therefore, expectation of NIL realization has emerged again. This paper describes current NIL technical status and refers to a future NIL patterning innovation such as a desktop lithography.

As the conventional optical lithography reaches its limit, we are now facing a huge paradigm shift to NGL schemes. There exist several candidates, such as Double Patterning, EUV and Nanoimprint, but they have their own new unconventional technical issues. This paper compares these NGL technologies from an exposure tool vendor's view. For double patterning, overlay is the biggest issue, and reticle heating effect by exposure light gives time dependent and non-linear distortion. As the reticle pattern area is protected with a pellicle, its direct cooling is difficult. The systematic optimization of reticle and lens heating is necessary to reduce the non-linear distortion. Though EUVL is now going to be applied to pre-production, technical issues still need a big leap. For a tool vendor, the extendibility to the resolution beyond 20nm is important. It forces us to use higher NA optics and off-axis illumination. In addition to the well-known mask, source and resist challenges, wavefront and vibration control would be the key issues for exposure tools. Nanoimprint is the last candidate for volume-production for memory application. It can offer the proven fine resolution and good pattern fidelity. The technology matching between nanoimprint technology and the exposure tool is very critical, because the imprint procedure means direct contacts between a tool and a wafer. The fundamental analysis leads us to find a view to cope with the basic issues of such contacts.

Defectivity has been historically identified as a leading technical roadblock to the implementation of nanoimprint lithography for semiconductor high volume manufacturing. The lack of confidence in nanoimprint's ability to meet defect requirements originates in part from the industry's past experiences with 1X lithography and the shortage in end-user generated defect data. SEMATECH has therefore initiated a defect assessment aimed at addressing these concerns. The goal is to determine whether nanoimprint, specifically Jet and Flash Imprint Lithography from Molecular Imprints, is capable of meeting semiconductor industry defect requirements. At this time, several cycles of learning have been completed in SEMATECH's defect assessment, with promising results. J-FIL process random defectivity of < 0.1 def/cm² has been demonstrated using a 120nm half-pitch template, providing proof of concept that a low defect nanoimprint process is possible. Template defectivity has also improved significantly as shown by a pre-production grade template at 80nm pitch. Cycles of learning continue on feature sizes down to 22nm.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned resist on the substrate. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the defect specifications of high end memory devices. Typical defectivity targets are on the order of 0.10/cm2. This work summarizes the results of defect inspections focusing on two key defect types; random non-fill defects occurring during the resist filling process and repeater defects caused by interactions with particles on the substrate. Non-fill defectivity must always be considered within the context of process throughput. The key limiting throughput step in an imprint process is resist filling time. As a result, it is critical to characterize the filling process by measuring non-fill defectivity as a function of fill time. Repeater defects typically have two main sources; mask defects and particle related defects. Previous studies have indicated that soft particles tend to cause non-repeating defects. Hard particles, on the other hand, can cause either resist plugging or mask damage. In this work, an Imprio 500 twenty wafer per hour (wph) development tool was used to study both defect types. By carefully controlling the volume of inkjetted resist, optimizing the drop pattern and controlling the resist fluid front during spreading, fill times of 1.5 seconds were achieved with non-fill defect levels of approximately 1.2/cm². Longevity runs were used to study repeater defects and a nickel contamination was identified as the key source of particle induced repeater defects.

The Jet and Flash Imprint Lithography (J-FIL^TM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 10⁴ - 10⁵imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, imprint replication tools and processes specifically for semiconductor applications. The requirements needed for semiconductors dictate the need for a well defined form factor for both master and replica masks which is also compatible with the existing mask infrastructure established for the 6025 semi standard, 6" x 6" x 0.25" photomasks. Complying with this standard provides the necessary tooling needed for mask fabrication processes, cleaning, metrology, and inspection. The replica form factor has additional features specific to imprinting such as a pre-patterned mesa. A Perfecta^TM MR5000 mask replication tool has been developed specifically to pattern replica masks from an e-beam written master. The system specifications include a throughput of four replicas per hour with an added image placement component of 5nm, 3sigma and a critical dimension uniformity error of less than 1nm, 3sigma. A new process has been developed to fabricate replicas with high contrast alignment marks so that designs for imprint can fit within current device layouts and maximize the usable printed area on the wafer. Initial performance results of this marks are comparable to the baseline fused silica align marks.

Authors are developing a 50kV e-beam direct writer MCC8 [1] with 8 column cells that enables a throughput of 5 wafers per hour. By March 2010, the concept of MCC had been proven with manufacturing the proof-of-concept system (MCCPOC; four column cells) in the Mask-D2I project of Association of Super-Advanced Electronics Technologies (ASET). Following the Mask-D2I project, the development has being focused on improving the position accuracy with MCCPOC system as a direct write tool. The effort is expected to bring a smooth transition to MCC8. In this paper, newly equipped correction technologies for improving the position accuracy is introduced; and the exposure results of field stitching, inter column-cell(CC) stitching, and mix-and-match overlay on Si wafer are presented. Almost the same accuracy results among all CCs are obtained. Mix-and-match overlay result is 5 nm in 3-sigma. Although inter-CC stitching is not required in device manufacturing, but it will be shown as a part of pure evaluation of the tool performance with the result of 5 nm in 3-sigma.

Basic concept and targeted throughput values for IMS Nanofabrication's 50keV electron multibeam Mask Exposure Tool called eMET are outlined and detailed specifications of an eMET Proof-of-Concept Tool are presented. Recent results as obtained with electron and ion multi-beam projection test systems are described and compared with exposure simulations. Exposures were concentrated on ILT as well as OPC test patterns. Good agreement between test system exposures and simulation results is shown proving the accuracy of the theoretical predictions. Aerial image simulations for eMET demonstrate its capability to fully resolve complex patterns down to the 8 nm mask technology node.

Currently, three MAPPER multi-electron beam lithography tools are operational. Two are located at customers, TSMC and LETI, and one is located at MAPPER. The tools at TSMC and LETI are used for process development. These tools each have 110 parallel electron beams and have demonstrated sub-30 nm half pitch resolution in chemically amplified resists. One important step towards the high volume tool is the capability to stitch the exposure of one electron beam to the next. The pre-alpha tool at MAPPER has been upgraded with an interferometer to enable exposures with a scanning stage and demonstrate first beam-to-beam stitching. A scan of 200 micrometers has been used to create a stitch area of 50 x 3 microns. The stitch error over all stitches was found to be below 25 nm. The electron beam position stability during the 10 seconds required for beam-to-beam stitching showed a contribution to the stitch error of 2.3 nm. The beam separation measurement, used to correct the static error, adds about 2.2 nm and the stage stability and linearity adds another 5 nm in the scan (interferometer) direction. In the perpendicular direction the stage instability gives the largest contribution to the stitch error (15 nm) due to the use of capacitive sensors. Overall, the electron beam stability and the beam position correction method work correctly and with sufficient accuracy for the high volume tool, 'Matrix'. The wafer stage for the Matrix system will incorporate full interferometer control to attain the needed positioning accuracy and stability.

According to the ITRS [1] photo mask is a significant challenge for the 22nm technology node requirements and beyond. Mask making capability and cost escalation continue to be critical for future lithography progress. On the technological side mask specifications and complexity have increased more quickly than the half-pitch requirements on the wafer designated by the roadmap due to advanced optical proximity correction and double patterning demands. From the economical perspective mask costs have significantly increased each generation, in which mask writing represents a major portion. The availability of a multi-electron-beam lithography system for mask write application is considered a potential solution to overcome these challenges [2, 3]. In this paper an update of the development status of a full-package high-throughput multi electron-beam writer, called Multi Shaped Beam (MSB), will be presented. Lithography performance results, which are most relevant for mask writing applications, will be disclosed. The MSB technology is an evolutionary development of the matured single Variable Shaped Beam (VSB) technology. An arrangement of Multi Deflection Arrays (MDA) allows operation with multiple shaped beams of variable size, which can be deflected and controlled individually [4]. This evolutionary MSB approach is associated with a lower level of risk and a relatively short time to implementation compared to the known revolutionary concepts [3, 5, 6]. Lithography performance is demonstrated through exposed pattern. Further details of the substrate positioning platform performance will be disclosed. It will become apparent that the MSB operational mode enables lithography on the same and higher performance level compared to single VSB and that there are no specific additional lithography challenges existing beside those which have already been addressed [1].

Directed self-assembly is an emerging technology that to-date has been primarily driven by research efforts in university and corporate laboratory environments. Through these environments, we have seen many promising demonstrations of forming self-assembled structures with small half pitch (<15 nm), registration control, and various device-oriented shapes. Now, the attention turns to integrating these capabilities into a 300mm pilot fab, which can study directed selfassembly in the context of a semiconductor fabrication environment and equipment set. The primary aim of this study is to create a 300mm baseline process of record using a 12nm half-pitch PS-b-PMMA lamellae block copolymer in order to establish an initial measurement of the defect density due to inherent polymer phase separation defects such as dislocations and disclinations.

Bit patterned media (BPM) is a promising candidate for high-density magnetic recording media beyond 2.5 Tb/in². To realize such a high-density BPM, directed self-assembling (DSA) technology is a possible solution. On the other hand, from the viewpoint of low-cost production, nanoimprint lithography is a promising process for the mass-production of such a high-density BPM. We examine the replication of the BPM etching mask by UV nanoimprint process. At first, the BPM silicon master mold consisting of servo pattern with dot array is made by the DSA method using PS-PDMS. For the 30-nm pitch corresponding to the density of 2.5 Tb/in², the nickel stamper is replicated from the silicon master mold by electroplating. The etching mask is transcribed by the UV nanoimprint process with the transparent mold replicated from the nickel mother stamper. On the other hand, as for the DSA-BPM pattern of 17-nm pitch corresponding to the density of 2.5 Tb/in², we adopt an alternative process and confirm the replication possibility.

The Jet and Flash Imprint Lithography (J-FIL^®) process uses drop dispensing of UV curable resists for high resolution patterning. Several applications, including patterned media, are better, and more economically served by a full substrate patterning process since the alignment requirements are minimal. Patterned media is particularly challenging because of the aggressive feature sizes necessary to achieve storage densities required for manufacturing beyond the current technology of perpendicular recording. In this paper, the key process steps for the application of J-FIL to pattern media fabrication are reviewed with special attention to substrate cleaning, vapor adhesion of the adhesion layer and imprint performance at >300 disk per hour. Also discussed are recent results for imprinting discrete track patterns at half pitches of 24nm and bit patterned media patterns at densities of 1 Tb/in².

Atomistic simulations of poly(styrene) (PS) and poly(methylmethacrylate) (PMMA) were performed and used to develop a realistic interaction potential for use in a mesoscale model of the PS-PMMA block co-polymer (BCP) system. The resulting interaction potential includes an attractive PS-PMMA segmental interaction, which is due to the electron dispersion interaction between these polymers. This attractive PS-PMMA interaction is not included in typical simulations of PS-PMMA phase behavior which use repulsive PS-PMMA interactions. Use of such repulsive interactions hastens the convergence of simulations of BCP phase separation and should not change the average phase behavior of such systems. However, failure to include this attractive PS-PMMA interaction can affect a variety of important properties and behaviors of interest including: (1) the width of interfacial regions, (2) the stability and energetics of metastable states such as local defects, and (3) the energy of interaction of BCP phases and morphologies with surfaces. Given the importance of defects and surface interactions in the application of the directed self assembly in BCP lithography in the microelectronics industry such a realistic potential is important. The potential from this mesoscale model was applied to a simple lattice model and showed that it was able to predict the process window for the formation of a lamellar phase for PS-PMMA BCP. However, elimination of the attractive PS-PMMA component broadened this process window by a significant amount suggesting that this component is important in the accurate modeling of BCP films for directed self assembly.

Recent progress in Block Copolymer lithography has shown that guided self-assembly is a viable alternative for pushing forward the resolution limits of optical lithography. The main two self assembly methods considered so far have been the surface chemical modification, which is based on the chemical modification of a brush grafted to the silicon, and the grapho-epitaxy, which is based on creating topographic patterns on the surface. We have tested these two approaches for the 22 nm node and beyond CMOS technology, using PS-PMMA block copolymers synthesized by RAFT (Reversible Addition-Fragmentation Chain Transfer) polymerization.

In this paper, we present our studies on polystyrene-b-polymethylmethacrylate (PS-b-PMMA) block copolymer systems to produce cylindrical morphology in the thin film configuration. More specifically, we focus on the different accessible parameters to optimize the processing conditions for the self-assembly of this block copolymer. We studied the self-assembly process of the block copolymer film spin-coated on different random brushes obtained by varying several parameters such as the film thickness, and the annealing time and temperature. We have shown that the thin-film morphology (in-plane, out-of-plane or mixed ones) critically depends on those different parameters and that a subtle optimization of them will provide almost defect-free nanostructures. We also examined the morphology of the self assembled features in the interior of the block copolymer thin film after the subsequent removal of the PMMA block structured domain. This process leads to the film top-nanostructures spanning across the whole film thickness. We evidenced also that high aspect-ratio nanostructures in bulk silicon can be obtained with such optimized films through CMOS-compatible dry-etching approach. To conclude, we show that the above-optimized self assembly parameters can be directly combined with 193nm-resist based patterns through the graphoepitaxy approach to achieve useful features for advanced lithography.

Reduction of resist filling time was investigated with the aim of improving UV-nanoimprint lithography (UV-NIL) throughput. A novel low volatility, low viscosity resist was developed to enable ink-jetting with minute resist droplets and imprinting under reduced air atmosphere. Direct observation of resist spreading showed that the resist filling process is composed of three steps: A) capillary bridge formation, B) resist spreading, and C) air bubble dissolution. Resist filling time was drastically decreased by changing the atmosphere from helium to a reduced air atmosphere of 0.02MPa. A comparison of 0.7pl and 6pl resist droplets showed that reducing resist droplet size while increasing area density also reduces resist filling time. Improved bubble dissolution speed is thought to result from imprinting under reduced air atmosphere. Moreover, ink-jetting smaller size resist droplets with higher density is thought to have an effect on reducing the time of each of the three steps, particularly bubble dissolution time. Combining dispensing-NIL with imprinting in vacuum is expected to improve UV-NIL throughput.

One of the major concerns with nanoimprint lithography is defecivity. One source of process specific defects is associated with template separation failure. The addition of fluorinated surfactants to the imprint resist is an effective way to improve separation and template lifetime. This study focuses on the development of new reactive fluorinated additives, which function as surfactants and also have the ability to chemically modify the template surface during the imprint process and thereby sustain a low surface energy release layer on the template. Material screening indicated that the silazane functional group is well suited for this role. The new reactive surfactant, di-(3,3,4,4,5,5,6,6,7,7,8,8,8- tridecafluorooctyl)silazane (F-silazane) was synthesized and tested for this purpose. The material has sufficient reactivity to functionalize the template surface and acceptable stability (and thus shelf-life) in the imprint formulation. Addition of F-Silazane to a standard imprint resist formulation significantly improved template release performance and allowed for significantly longer continuous imprinting than the control formulation. A multiple-imprint study using an Imprio® 100 tool confirmed the effectiveness of this new additive.

Nano-Imprint Lithography and a mold, mold replication from an EB master mold as well, those are essential for a large-scale production of patterned media. In nano-imprinting, since it is contact printing, a higher separation force might cause damages to the master and imprinting tool, degradation in pattern quality as well. Those difficulties also work to retard continuous imprinting for the mold replication. Then, we focused on release materials characterization and selection to facilitate clean separation between cured resist and the master. This paper describes a novel release material, and continuous nano-imprinting results with it for replica mold fabrication from an EB master for the patterned media application.

The semiconductor industry is under constant pressure to reduce production costs even as the complexity of technology increases. Lithography represents the most expensive process due to its high capital equipment costs and the implementation of low-k1 lithographic processes, which have added to the complexity of making masks because of the greater use of optical proximity correction, pixelated masks, and double or triple patterning. Each of these mask technologies allows the production of semiconductors at future nodes while extending the utility of current immersion tools. Low-k1 patterning complexity combined with increased data due to smaller feature sizes is driving extremely long mask write times. While a majority of the industry is willing to accept times of up to 24 hours, evidence suggests that the write times for many masks at the 22 nm node and beyond will be significantly longer. It has been estimated that funding on the order of $50M to $90M for non-recurring engineering (NRE) costs will be required to develop a multiple beam mask writer system, yet the business case to recover this kind of investment is not strong. Moreover, funding such a development poses a high risk for an individual supplier. The structure of the mask fabrication marketplace separates the mask writer equipment customer (the mask supplier) from the final customer (wafer manufacturer) that will be most effected by the increase in mask cost that will result if a high speed mask writer is not available. Since no individual company will likely risk entering this market, some type of industry-wide funding model will be needed.

In the latest ITRS roadmap updated in July 2010, Maskless remains identified as one of the candidate to address lithography needs for the sub-16nm technology nodes. The attractiveness of this solution in terms of cost and flexibility linked to the throughput potential of the massively parallel writing solutions maintain the interest of large scale IC manufacturers, such as TSMC⁽¹⁾ and STMicroelectronics, to push the development of this technology. In July 2009, LETI and MAPPER have initiated an open collaborative program IMAGINE focused on the assessment of the MAPPER technology. This paper reports on the key results obtained during this first assessment year in terms of: resolution capabilities, stitching performances, technology reliability and infrastructure development. It also provides an extensive overview on the maturity degree and the ability of this low energy accelerating voltage multibeam option to answer to the industry needs in the 2015 horizon.

Massively E-beam maskless lithography (MEBML2) is one of the potential solutions for 32-nm half-pitch and beyond. In the past, its relatively low throughput restricted EBDW development to mostly mask making, small volume wafer production and prototyping. Recently the production worthy ML2 approaches, >10,000 e-beams writing in parallel, have been proposed by MAPPER, KLA and IMS. These approaches use raster scan in pattern writing. Hence the bitmap is certainly the final data format. The bitmap format used to have huge data volume with fine pixel size to maintain the CD accuracy after electron proximity correction (EPC). Data handling becomes necessary, especially on data transmission rate. The aggregated data transmission rate would be up to 1963 Tera bits per second (bps) for a 10 WPH tool using 1-nm pixel size and 1-bit gray level. It needs 19,630 fibers each transmitting 10 Gbps. The data rate per beam would be >20 Gbps in 10,000-beam MEBML2. Hence data reduction using bigger pixel size to achieve sub-nm EPC accuracy is crucial for reducing the fiber number to the beam number. In this paper, the writing-error-enhanced-factor to quantitatively characterize the impact of CD accuracy by various total blur in resist is reported; and we propose the vernier pattern to verify sub-nm CD accuracy and the in-house dithering raster method to achieve sub-0.2-nm CD accuracy using multiple-nm pixel sizes, which could reduce the need of the aggregated data rate to 11%, 33%, 44% and 79% of 1963 Tbps on 22-nm, 16-nm, 11-nm, 8-nm node respectively.

Electron beam lithography has been used in the production of integrated circuits for decades. However, due to the limitation of throughput it was not a viable solution for high volume manufacturing and its biggest application is the production of semiconductor masks. For many considerations it has particularly now become desirable to eliminate the semiconductor mask and introduce maskless lithography for semiconductor fabrication. Multiple Electron Beam Maskless Lithography (MEBML2) has been proposed as a solution to overcome the traditional source current limitation of an electron beam system by using many thousands of parallel electron beamlets to write a pattern directly on the wafer. In developing the MEBML2 tool the challenges have shifted and, in absence of the mask, the system data path has emerged as one of the central challenges. The main theme in the data path development is bandwidth. The required raw bandwidth at the patterning beams is determined by throughput and resolution, i.e. pixel size and number of intensity modulation levels. To achieve a production worthy throughput at 10 wafers per hour in a Gaussian-beam-based maskless lithography system, by writing 3.5-nm pixels at 2 levels (on/off) which is required for the 22-nm lithography node, the required aggregate bandwidth at the beam blanker array is up to 45 Tbit/s. Such a large bandwidth requirement means that the data path architecture is mainly characterized by the bandwidth of the data streams in the system. Compression techniques can be used to reduce the intermediate data stream bandwidth requirements and consequently lead to simplifying the system design, reducing power consumption and footprint, but come at the cost of increased data processing complexity and possible limitations on throughput. In this paper we will show results from the development of a prototype data path for the Gaussian-beam-based maskless lithography system. A new concept for data processing and storage is proposed. The vertex-based processing and storage technique is adopted to reduce memory usage considerably, with only modest requirements on the hardware resources. It reveals that a realistically implementable data path system for the maskless lithography tool in high volume manufacturing is feasible.

The semiconductor industry is moving to highly regular designs, or 1D gridded layouts, to enable scaling to advanced nodes, as well as improve process latitude, chip size and chip energy consumption. The fabrication of highly regular ICs is straightforward. Poly and metal layers are arranged into 1D layouts. These 1D layouts facilitate a two-step patterning approach: a line-creation step, followed by a line-cutting step, to form the desired IC pattern (See Figure 1). The first step, line creation, can be accomplished with a variety of lithography techniques including 193nm immersion (193i) and Self-Aligned Double Patterning (SADP). It appears feasible to create unidirectional parallel lines to at least 11 nm half-pitch, with two applications of SADP for pitch division by four. Potentially, this step can also be accomplished with interference lithography or directed self assembly in the future. The second step, line cutting, requires an extremely high-resolution lithography technique. At advanced nodes, the only options appear to be the costly quadruple patterning with 193i, or EUV or E-Beam Lithography (EBL). This paper focuses on the requirements for a lithography system for "line cutting", using EBL to complement Optical. EBL is the most cost-effective option for line cutting at advanced nodes for HVM.

Complex mask shapes will be required on critical layer masks for 20nm logic node, threatening to explode the mask write times. Model-Based Mask Data Preparation (MB-MDP) has been introduced to reduce the shot count required to write complex masks while simultaneously improving resolution and dose margin of sub-100nm features. For production use of MB-MDP, a number of questions have been raised and answered. This paper summarizes these potential issues and their resolutions. In particular, the paper takes an in-depth look at one of the questions: impact of overlapping shots on heating effect. The paper concludes that while heating effect is an important issue for all e-beam writing even with conventional non-overlapping shots, overall dose density per unit time over microns of space is the principal driver behind heating effects. Highly local shot density and shot sequencing does not affect heating significantly, particularly for smaller shots. MB-MDP does not introduce any additional concerns.

The authors have succeeded in employing nanoimprint lithography (NIL) to form diffraction gratings of distributed feedback laser diodes (DFB LDs) used in optical communication. We have fabricated more than 300 phase-shifted DFB LDs on a 2-in. InP substrate. The devices have indicated comparable characteristics including uniformity and reliability with those fabricated by conventional electron beam lithography. We have also demonstrated a novel concept of a mold containing various types of grating patterns in a field ("VARI-mold"). By utilizing the new mold, DFB LDs with various emission wavelengths are formed simultaneously on a wafer. It indicates that one VARI-mold is possible to be applied to various kinds of product, leading to the cost reduction of the molds and the total NIL process. The results of this study indicate that NIL is a promising candidate of the production technique for phase-shifted DFB LDs featuring low cost and high throughput.

Nano Imprint Lithography (NIL) is a promising technology that combines low costs with high throughput for fabrication of sub 100 nm scale features. One of the first application areas in which NIL is used is manufacturing of various types of LED's. The wafers used for producing LED's are typically III/V semiconductor materials grown with epitaxial processes. These types of substrates suffer from growth defects like hexagonal spikes, vpits, waferbowing, atomic steps and surface corrugations on a scale of few 10 μm or even large islands of irregularities. The mentioned irregularities are particularly disturbing when NIL based processes are utilized to create patterns onto the wafer surface. The nanopatterns created by NIL can be applied to control metal organic vapour phase epitaxy (MOVPE) growth of GaN nanorods. This paper will show that NIL is an excellent technology to produce nanopatterned GaN substrates highly suitable to grow defect free arrays of positioncontrolled nanorods for ultrahigh brightness LED applications.

HP has previously demonstrated the roll-to-roll (R2R) fabrication of active-matrix display backplanes using the Self-Aligned Imprint Lithography (SAIL) process. This approach permits a single imprint step to create a multi level mask comprising all patterns required for subsequent etching steps, obviating the need for multiple alignment steps. In this paper the imprint lithography technique and aspects of SAIL are reviewed. New work using imprint processing to generate structural templates, with aspect ratios approaching 6:1, for fluid containment will be presented. Arrays of transparent well structures, formed on a flexible transparent substrate provide the basis for a color display filter matrix that is filled by inkjet deposition of pigmented resins. A primary benefit of this approach is precise color pattern definition. A separation between primary color fields of 4 microns is realized without risk of color mixing or overlap. Components patterned with high absolute precision by imprint lithography were readily integrated with parts from other sources to yield flexible color reflective display demonstrator panels. This work highlights the flexibility of imprint processing and its suitability for use with a wide variety of materials and in differing applications.

NRAM technology, a non-volatile memory based on the use of carbon nanotubes, overcomes the limitations of other memory technology types (including traditional Flash), for sub-40nm nodes, and is currently developed in manufacturing fabs. The NRAM technology process flow involves the deposition of a film of carbon nanotubes onto silicon wafers at several of the critical layers (using spin coating techniques). In this paper, we present the key steps of the development and characterization of carbon nanotube processes applied to NRAM technology, focusing on specific deposition techniques, thickness control, and defectivity.

REBL (Reflective Electron Beam Lithography) is a program for the development of a novel approach for highthroughput maskless lithography. The program at KLA-Tencor is funded under the DARPA Maskless Nanowriter Program. A DPG (digital pattern generator) chip containing over 1 million reflective pixels that can be individually turned on or off is used to project an electron beam pattern onto the wafer. The DARPA program is targeting 5 to 7 wafers per hour at the 45 nm node, and this paper will describe improvements to both increase the throughput as well as extend the system to the 2x nm node and beyond. This paper focuses on three specific areas of REBL technology. First, a new column design has been developed based on a Wien filter to separate the illumination and projection beams. The new column design is much smaller, and has better performance both in resolution and throughput than the first column which used a magnetic prism for separation. This new column design is the first step leading to a multiple column system. Second, the rotary stage latest results of a fully integrated DPG CMOS chip with lenslets will be reviewed. An array of over 1 million micro lenses which is fabricated on top of the CMOS DPG chip has been developed. The microlens array eliminates crosstalk between adjacent pixels, maximizes contrast between on and off states, and provides matching of the NA between the DPG reflector and the projection optics.

Electron Beam Direct Write (EBDW) lithography is used in the IC manufacturing industry to sustain optical lithography for prototyping applications and low volume manufacturing. It is also used in R&D to develop advanced technologies, ahead of mass production. As microelectronics is now moving towards the 32nm node and beyond, the specifications in terms of dimension control and roughness becomes tighter. In addition, the shrink of the size and pitch of features significantly reduces the process window of lithographic tools. In EBDW, the standard proximity effects corrections only based on dose modulation show difficulties to provide the required Energy Latitude for patterning structures designed below 45nm. A new approach is thus needed to improve the process window of EBDW lithography and push its resolution capabilities. In previous papers, a new writing strategy based on multiple pass exposure has been introduced and optimized to pattern critical dense lines. This new technique consists in adding small electron Resolution Improvement Features (eRIFs) on top of the nominal structures. Then this new design is exposed in two successive passes with optimized doses. Previous studies were led to evaluate this new writing technique and establish rules to optimize the design of the eRIF. Significant improvements have already been demonstrated on SRAM and Logic structures down to the 16nm node. These results were obtained with a tool dedicated to the 45nm node. The next step of this work is thus to automatically implement the eRIF to correct large-scale layouts. In this paper, a new data preparation flow is set up for EBDW lithography. It uses the eRIF solution as a full advanced correction method for critical structures. The specific correction rules established in our previous studies are implemented to improve the CD control and the patterning of corners and line ends. Moreover, the dose and shape of the eRIFs are automatically tuned to best fit the nominal design. This work is done with "INSCALE^®", the new data preparation software from ASELTA Nanographics. This data preparation flow is then applied on layouts down to the 22nm node. Comparisons with the standard dose modulation flow demonstrate that adding eRIFs significantly improves the process window and thus the resolution of e-beam tools. It also shows that the multiple pass exposure technique can be used as a specific correction method on large scale layouts.

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing with high speed optical data transport for switching the electron beams. In this way electron optical columns can be made with a throughput of 10 wafers per hour. The amount of data for each 26mm x 33mm field is 8 Tbyte. The data rate is approximately 3 Tbyte per second. In order to realize overlay the patterns for different fields on the wafer need to be slightly adjusted. Additionally it is beneficial for the electron optics design to be able to correct a number of tool parameters on the data. For this it is desirable to be able to correct the pattern data in real time. By implementing the correction algorithms on an FPGA test board it has been demonstrated that it is possible to perform the corrections on the exposed data real time. By using a pixel size of 3.5nm, a CDu and overlay contribution of smaller than 1nm 3s is obtained. A datapath for 10wph based on an FPGA implementation that stores the switching data uncompressed in DRAM fits in 4 racks of 2 meters high, with a footprint of 600mm x 700mm each. By replacing the FPGA by an ASIC implementation, and by using real time decompression, the footprint can be reduced in a later stage.

It is now obvious that the path leading to denser IC has become hazardous since 193nm scanners have been operating beyond their resolution limit. However if the tools that could provide photo-lithographers with some relief are not in production yet, luckily enough, good progresses were made in developing alternative photolithography techniques. Among them, massively parallel mask less lithography stands out as a serious candidate since it can achieve the required resolution at the right cost of ownership provided targeted throughput performance is reached. This paper will focus on this latter technique and more precisely, will report on part of the development works performed at CEA/LETI using the MAPPER technology inside the open multi-partners program IMAGINE. Data preparation is certainly not the easiest part in the technology. Indeed, layouts are basically turned into huge bitmap streams containing the information to be sent to the thousands of parallel beams working all together to print the patterns correctly. Addressing the low energy specific case, we had studied several ways of performing this step involving geometrical correction with and without dose modulation. The results were analysed against the achieved design to wafer fidelity and the robustness of the patterns with respect to process variations and shot noise. The intention of the paper is therefore to give a status towards where E-Beam Proximity Correction (EBPC) performance stands today using current MAPPER alpha tool. It will also provide with some insights about how corrections will be performed on the HVM tool.

For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face the nodes well below 32nm half pitch in the next 2~3 years. Despite being able to achieve the required resolution, which is now possible with electron beam direct write variable shaped beam (EBDW VSB) equipment and resists, it becomes critical to precisely reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a later placed contact to be able to land on it. Up to now, the control of printed patterns such as line ends is achieved by a proximity effect correction (PEC) which is mostly based on a dose modulation. This investigation of the line end shortening (LES) includes multiple novel approaches, also containing an additional geometrical correction, to push the limits of the available data preparation algorithms and the measurement. The designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and measured at Fraunhofer Center Nanoelectronic Technologies (CNT) using its state of the art electron beam direct writer and CD-SEM. Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large production like pattern in the range of our target CDs in dense line space features smaller than 40nm will be shown.

We report wet development technique for directed self-assembly lithography pattern. For typical diblock copolymer, poly (styrene-block-methyl methacrylate) (PS-b-PMMA), the PMMA area is removed by O₂ plasma. However, O₂ plasma attack also etches off PS area simultaneously. As a result, the thickness of residual PS pattern is thinner and it causes degradation of PS mask performance. PS thickness loss in the device integration is not desirable as etching mask role. In this work, we applied wet development technique which could be higher selectivity to keep PS film thickness after pattern formation. Especially, we propose the method using low pressure mercury lamp and conventional TMAH (2.38%) as developer. It is expected to accomplish pattern formation in one track with coating, baking, exposure and development.

The current photolithography technology is approaching the physical barrier to the minimum achievable feature size. To produce smaller devices, new resolution enhancement technologies must be developed. Double exposure lithography has shown promise as a potential pathway that is attractive because it is much cheaper than double patterning lithography and it can be deployed on existing imaging tools. Double patterning uses two photoresist layers to transfer the final pattern to a hard mask layer. This paper proposes a novel double exposure patterning method that combines two consecutive exposures of mask patterns with an intermediate image reversal processing step in a single photoresist layer. The proposed method has a low cost-of-ownership, since only one photoresist layer is used. Using simple "primitive" mask patterns for the various exposures, the method produces complex patterns that cannot be achieved by conventional double exposure methods. This approach mitigates also the diffraction distortion effects of inside corners present particularly in highly regular lithography patterns. In case of triple exposure, the diffraction rounding of the outside corners can be mitigated as well. This approach can be retrofitted into existing older photolithography generations, obviating in many cases the use of optical proximity corrections and thus boosting the yields significantly.

A novel laser interference lithography system with enhanced tunablility in pattern periodicity and coverage has been designed and tested for large-area nano-patterning in a wide range of a pattern frequency. The tunable feature has been achieved by using two rotational mirrors on expanded beam paths at specific angles for a designed period. With a 325 nm laser wavelength, uniform resist nano-patterns of 250, 500, and 750 nm have been experimentally demonstrated on a 4-inch silicon substrate. This new interferometer configuration offers a convenient and robust way to prepare large-area nanostructures with superior tunability in pattern periods.

Evanescent-wave imaging is demonstrated using solid-immersion Lloyd's-mirror interference lithography (SILMIL) at λ = 325 nm to produce 44-nm half-pitch structures (numerical aperture, NA = 1.85). At such an ultra-high NA the image depth is severely compromised due to the evanescent nature of the exposure, and the use of reflections from plasmonic under-layers is discussed as a possible solution. Simulations and modelling show that image depths in excess of 100 nm should be possible with such a system, using silver as the plasmonic material. The concept is scalable to 193 nm illumination using aluminium as the plasmonic reflector, and simulation results are shown for 26-nm half-pitch imaging into a 37-nm thick resist layer using this scheme.

Nanoimprint technology already demonstrated high resolution capability using hard master stamps in the mid 90's. Considering this as a well known technology, there are still restrictions making nanoimprint lithography (NIL) a competitive "next generation lithography" technique. This paper will address limitations in regard to large area master stamp manufacturing, resolution and lifetime using soft UV-NIL imprint lithography on stamps fabricated by massively parallel ion beam lithography provided by the CHARPAN tool. It provides detailed information of sub- 15 nm (dots, grids and lines) replication processes at master fabrication, working stamp replication and imprinting.

In this paper scatterometry sensitivity up to 28nm HP resin pattern and beyond by using RCWA (Rigorous Coupled Wave-analysis) simulation is described. A criterion, defined as the sum of the absolute difference of the reflectivity values between the nominal and slightly different conditions from nominal through the spectrum, is introduced. The criterion of this analysis is a kind of quantification of the sensitivity comparing with 65 nm HP resist pattern of ArF immersion lithography process.

We have developed a Crestec Surface Electron emission Lithography (CSEL) for mass production of semiconductor devices. CSEL system is 1:1 electron projection lithography using surface electron emitter. In first report, we confirmed that a test bench of CSEL resolved below 30 nm pattern over 0.2 um square area. Practical resolution of the system is limited by the chromatic aberration. We improved the resolution of the prototype CSEL system by reducing the initial energy spread of electrons and/or by increasing the electric field intensity. An energy spread of emitted electrons of a nanosilicon planar ballistic electron emitter (PBE) is very small. After that, the prototype CSEL system exposed sub-micron patterns distributed over 3 mm square area in last report. In this study, we examine the prototype CSEL system exposed deep sub-micron pattern over full-field for practical use. The experimental column of the system is composed of the PBE and a stage as a collector electrode that is parallel to the electron source. An accelerating voltage of about -5 kV is applied to the electron source with respect to the collector. The target wafer and PBE are set between two magnets. The two magnets generate vertical magnetic field of 0.5 T to the surface of the target wafer. A gap between the electron source and the target wafer is adjusted to a focus length depending on electron trajectories in the electromagnetic field in the system. The electron source projects a patterned electron image on the target since the patterned mask was formed on the surface electrode of the electron source. The electrons are emitted from openings of the mask. When a pulsed bias voltage is applied to the electron source, the electron source emits a patterned surface electron beam. The beam strikes the resist film coated on the target wafer and make replica of the pattern. We indicate the system exposes line patterns of about 200 nm in width over large area. An advantage of CSEL is high resolution due to small chromatic aberration, and another advantage is potentially high throughput because the coulomb blur is small without any crossover in the electron optics. When we get sufficient current from the electron source the throughput can be more than 100 wafers/hour.

As critical dimensions in Logic chips continue to shrink, EBDW (E-Beam Direct Write) will play a growing role. EBDW is capable of patterning 2D shapes at extremely high resolution. EBDW will pattern low-density critical wafer-layers, complementing optical lithography in high volume manufacturing. E-beam landing energies ranging from 5 keV to 100 keV are used in EBDW today. The choice of e-beam energy effects resolution, throughput and overlay errors due to thermal effects. We present an analysis of the tradeoffs of various e-beam landing energies. We examine 5 keV, 7.5 keV, 10 keV, 20 keV and 50 keV. We use a simple column design and SIMION 8 simulation software. SIMION 8 (from Scientific Instrument Services, Inc.) is used for electrostatic lens analysis and charged particle trajectory modeling We examine: 1. Resolution (beam dose profile in resist) 2. Overlay errors due to thermal effects (beam power) Low energy EBDW has advantages in resist sensitivity and thermal control. Its disadvantages include lower beam current and a requirement for very thin resist. High energy EBDW has advantages in beam current and resolution. Its disadvantages include wafer heating and low resist sensitivity. With set requirements for resolution and thermal expansion, we report findings of beam profile and beam dose at various beam energies.

Traditionally, e-beam direct write lithography has been too slow for most lithography applications. E-beam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the uncertainty with regards to the optical lithography roadmap beyond the 22 nm technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for high volume wafer processing. For this work, we report on the development and current status of a new maskless, direct write e-beam lithography tool which has the potential for high volume lithography at and below the 22 nm technology node. A Reflective Electron Beam Lithography (REBL) tool is being developed for high throughput electron beam direct write maskless lithography. The system is targeting critical patterning steps at the 22 nm node and beyond at a capital cost equivalent to conventional lithography. Reflective Electron Beam Lithography incorporates a number of novel technologies to generate and expose lithographic patterns with a throughput and footprint comparable to current 193 nm immersion lithography systems. A patented, reflective electron optic or Digital Pattern Generator (DPG) enables the unique approach. The Digital Pattern Generator is a CMOS ASIC chip with an array of small, independently controllable lens elements (lenslets), which act as an array of electron mirrors. In this way, the REBL system is capable of generating the pattern to be written using massively parallel exposure by ~1 million beams at extremely high data rates (~ 1Tbps). A rotary stage concept using a rotating platen carrying multiple wafers optimizes the writing strategy of the DPG to achieve the capability of high throughput for sparse pattern wafer levels. The lens elements on the DPG are fabricated at IMEC (Leuven, Belgium) under IMEC's CMORE program. The CMOS fabricated DPG contains ~ 1,000,000 lens elements, allowing for 1,000,000 individually controllable beamlets. A single lens element consists of 5 electrodes, each of which can be set at controlled voltage levels to either absorb or reflect the electron beam. A system using a linear movable stage and the DPG integrated into the electron optics module was used to expose patterns on device representative wafers. Results of these exposure tests are discussed.

The recent algorithm Corner is a transform-based technique to represent a circuit layout image for electron beam direct write lithography systems. We improve the lossless circuit layout compression algorithm Corner so that 1) it requires fewer symbols during the corner transform, 2) it has a simpler and faster decoding process, and 3) it requires a similar amount of memory for the decoding process.

The commercialization of 32 nm lithography has been made possible by using double patterning, a technique that allows for an increased pattern density, potentially, through resist freezing and high precision pattern registration. Recent developments in directed self assembly (DSA) also uses resist freezing for stabilizing positive tone resists used in graphoepitaxy. We have developed a method of patterning an open source, positive tone EUV resist using electron beam lithography (EBL), and studied a novel way of freezing a positive tone EUV photoresists through electron beam induced crosslinking. Through metrological analysis, crosslinked pattern was observed to retain consistent critical dimensions (CD) and line-edge roughness (LER) after they were annealed at temperatures higher than the glass transition of the photoresist. This process has been used to freeze patterned EUV photoresists, which have been subsequently used for directed self assembly of PS-b-PMMA and has potential applications in double patterning in an LFLE scenario.