This PDF file contains the front matter associated with SPIE Proceedings Volume 7823, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

A survey created supported by SEMATECH and administered by David Powell Consulting was sent to microelectronics industry leaders to gather information about the mask industry as an objective assessment of its overall condition. The survey was designed with the input of semiconductor company mask technologists and merchant mask suppliers. This year's assessment is the ninth in the current series of annual reports. With ongoing industry support, the report can be used as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries. It will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results will be used to guide future investments pertaining to critical path issues. This year's survey was basically the same as the 2005 through 2009 surveys. Questions are grouped into categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns, and Services. Within each category are multiple questions that result in a detailed profile of both the business and technical status of the critical mask industry. This profile combined with the responses to past surveys represents a comprehensive view of changes in the industry.

When it comes to the absorber etching of EUV (Extreme Ultra-Violet) mask, it is important to understand the mechanism of how a sidewall protection film is formed in the TaBO etching process and TaBN etching process. According to our evaluations, the sidewall protection film formed in the TaBO etching process is constituted by a fluorocarbon polymer generated through the dissociation of gas, which then acts as a sidewall protection film. On the other hand, the sidewall protection film formed in the TaBN etching process is considered an etching product. By controlling those sidewall protection films, it has become possible to determine the critical dimension (CD) of TaBO for the 44-nm L/S on mask pattern (11-nm node) to implement vertical etching using TaBN in accordance with the TaBO dimension. In doing this, a CUD of 1.7 nm (3 sigma) and CD linearity of 5.2 nm (44 to 1000 nm) are achieved. To ensure a good absorber etching shape, it is necessary to keep resist until etching is complete, and for this reason the resist selection ratio is also important.

Photomask Japan each year hosts a meeting inviting the conference attendees to actively participate in a discussion on a selected topic. The topic selected for this year is on new mask inspection and metrology techniques that are just emerging in the market, namely, aerial/wafer image based inspection and metrology, and optical high sampling frequency CD uniformity measurement. The panel discussion hopes to identify potential values of each technique and at the same time discover any challenge if the industry were to adopt such technique.

In writing 22nm logic contacts with 193nm immersion, curvilinear sub-resolution assist features will be desirable on masks. Curvilinear sub-resolution assist features are good for high volume chips where the wafer volume outweighs considerations for mask write times. For those chips, even 40 hour write times are tolerated for mask writing. For lower-volume production of SOC designs, such write times are economically unacceptable. 8 to 12 hours of write times are feasible for these designs. Previous papers at 2010 Photomask Japan described model-based mask data preparation (MB-MDP) techniques using circular apertures on production e-beam writers writing curvilinear ideal ILT patterns that reduced e-beam write-times by nearly a factor of two over conventional approach writing Manhattanized ILT patterns. This puts the curvilinear assist features within the realm of high-volume production. However, the write times are still too long for SOC designs. This paper describes a new technique that reduces mask write time further. Resist-exposed SEM images will be shown, written by JEOL JBX-3200MV. E-beam shot count comparisons for an ideal ILT mask pattern will be made with the conventional methods, demonstrating a 44% decrease in blanking time. In addition, a comparison study is shown indicating that an ideal ILT mask pattern that would take 63 hours with conventional fracturing can be written in about 14 hours using MB-MDP. AIMS projected images demonstrate the pattern fidelity on the wafer.

Multi-beam writing becomes mandatory for future technology nodes in order to stay within reasonable realization times for leading-edge complex masks and templates. IMS Nanofabrication has developed multi-beam projection techniques implementing a programmable aperture plate system (APS) and charged-particle projection optics with 200x reduction. Proof-of-concept of multi-beam writing on static substrates was demonstrated in 2009 using the CHARPAN tool with 10keV ion multi-beams and the RIMANA tool with 50keV electron multi-beams. For the first time projection multibeam writing on moving substrates is presented as made achievable by upgrading the CHARPAN Tool with a laserinterferometer controlled stage to realize a POWS (Proof-Of-Writing-Strategy) tool configuration. With the RIMANA Tool 50keV e-beam exposures of ILT (Inverse Lithography Technique) patterns are demonstrated.. The status of the development of a 50keV electron Mask Exposure Tool (eMET) is presented and the targeted writing speeds of eMET POC and eMET HVM systems are outlined.

Photomask lithography for the 22nm technology node and beyond requires new approaches in equipment as well as mask design. Multi Shaped Beam technology (MSB) for photomask patterning using a matrix of small beamlets instead of just one shaped beam, is a very effective and evolutionary enhancement of the well established Variable Shaped Beam (VSB) technique. Its technical feasibility has been successfully demonstrated ^[2]. One advantage of MSB is the productivity gain over VSB with decreasing critical dimensions (CDs) and increasing levels of optical proximity correction (OPC) or for inverse lithography technology (ILT) and source mask optimization (SMO) solutions. This makes MSB an attractive alternative to VSB for photomask lithography at future technology nodes. The present paper describes in detail the working principles and advantages of MSB over VSB for photomask applications. MSB integrates the electron optical column, x/y stage and data path into an operational electron beam lithography system. Multi e-beam mask writer specific requirements concerning the computational lithography and their implementation are outlined here. Data preparation of aggressive OPC layouts, shot count reductions over VSB, data path architecture, write time simulation and several aspects of the exposure process sequence are also discussed. Analysis results of both the MSB processing and the write time of full 32nm and 22nm node critical layer mask layouts are presented as an example.

The semiconductor industry is under constant pressure to reduce production costs even as technology complexity increases. Lithography represents the most expensive process due to its high capital equipment costs and the implementation of low-k1 lithographic processes, which has added to the complexity of making masks through the greater use of optical proximity correction, pixelated masks, and double or triple patterning. Each of these mask technologies allows the production of semiconductors at future nodes while extending the utility of current immersion tools. Low k1 patterning complexity combined with increased data due to smaller feature sizes is driving extremely long mask write times. While a majority of the industry is willing to accept mask write times of up to 24 hours, evidence suggests that the write times for many masks at the 22 nm node and beyond will be significantly longer. It has been estimated that $50M+ in non-recurring engineering (NRE) costs will be required to develop a multiple beam mask writer system, yet the business case to recover this kind of investment is not strong. Moreover, funding such a development is a high risk for an individual supplier. The problem is compounded by a disconnect between the tool customer (the mask supplier) and the final mask customer that will bear the increased costs if a high speed writer is not available. Since no individual company will likely risk entering this market, some type of industry-wide funding model will be needed. Because SEMATECH's member companies strongly support a multiple beam technology for mask writers to reduce the write time and cost of 193 nm and EUV masks, SEMATECH plans to pursue an advanced mask writer program in 2011 and 2012. In 2010, efforts will focus on identifying a funding model to address the investment to develop such a technology.

High resolution sub resolution assist features (SRAFs) are challenging to pattern, especially on photomasks with pattern density variations and beam corrections. This paper presents analysis techniques of SRAF resist resolution performance and manufacturing robustness. Electron beam proximity effects and their correction methods impact aerial image quality. Resist resolution and LER depend strongly on the aerial image, and these effects will be looked at theoretically and experimentally with CDSEM and reflected die-to-die inspection techniques. A quantitative understanding of resolution process latitude is important in SRAF patterning, especially when one considers beam corrections that are used to compensate for effects like electron fogging and etch loading.

For the next years optical lithography stays at 193nm with a numerical aperture of 1.35. Mask design becomes more complex, mask and lithography specification tighten and process control becomes more important than ever. Accurate process control is a key factor to success to maintain a high yield in chip production. One of the key parameters necessary to assure a good and reliable functionality of any integrated circuit is the Critical Dimension Uniformity (CDU). There are different contributors which impact the total wafer CDU: mask CD uniformity, scanner repeatability, resist process, lens fingerprint, wafer topography etc. In this work we focus on improvement of intra-field CDU at wafer level by improving the mask CD signature using a CDC200^TM tool from Carl Zeiss SMS. The mask layout used is a line and space dark level of a 45nm node Non Volatile Memory (NVM). A prerequisite to improve intra-field CDU at wafer level is to characterize the mask CD signature precisely. For CD measurement on mask the newly developed wafer level CD metrology tool WLCD32 of Carl Zeiss SMS was used. The WLCD32 measures CD based on proven aerial imaging technology. The WLCD32 measurement data show an excellent correlation to wafer CD data. For CDU correction the CDC200^TM tool is used which utilizes an ultrafast femto-second laser to write intra-volume shading elements (Shade-In Elements^TM) inside the bulk material of the mask. By adjusting the density of the shading elements, the light transmission through the mask is locally changed in a manner that improves wafer CDU when the corrected mask is printed. In the present work we will demonstrate a closed loop process of WLCD32 and CDC200^TM to improve mask CD signature as one of the main contributors to intra-field wafer CDU. Furthermore we will show that the process window will be significantly enlarged by improvement of intra-field CDU. An increase of 20% in exposure latitude was observed.

The ray tracing of electron based on Monte Carlo is simulated by GEANT software to investigate the electron scattering property in ArF photomask and EUV photomask. By Monte Carlo simulation, we have presented the mechanism of electron scattering in EUV photomask and simulated the electron distribution which gives rise to change the patterning performance of EUV photomask, compared with those of ArF photomask. Furthermore, the overlay error of EUV photomask has been analyzed by the charging model. EUV photomask has the additional electron distribution in the range of 2um, which comes from the strong electron scattering at Mo/Si multilayer. Because of this additional electron distribution, EUV photomask has the pattern size error due to proximity effect of electron when the conventional Gaussian function is used to correct the proximity effect of ArF photomask. The maximum residual error due to the proximity effect in EUV photomask is 7nm. Furthermore, we have confirmed that the linearity of pattern size is so different from ArF photomask and it is well explained with the Gaussian blur model based on the electron distribution of EUV photomask.

Image modeling and simulation are critical to extending the limits of leading edge lithography technologies used for IC making. Simultaneous source mask optimization (SMO) has become an important objective in the field of computational lithography. SMO is considered essential to extending immersion lithography beyond the 45nm node. However, SMO is computationally extremely challenging and time-consuming. The key challenges are due to run time vs. accuracy tradeoffs of the imaging models used for the computational lithography. We present a new technique to be incorporated in the SMO flow. This new approach is based on the reduced basis method (RBM) applied to the simulation of light transmission through the lithography masks. It provides a rigorous approximation to the exact lithographical problem, based on fully vectorial Maxwell's equations. Using the reduced basis method, the optimization process is divided into an offline and an online steps. In the offline step, a RBM model with variable geometrical parameters is built self-adaptively and using a Finite Element (FEM) based solver. In the online step, the RBM model can be solved very fast for arbitrary illumination and geometrical parameters, such as dimensions of OPC features, line widths, etc. This approach dramatically reduces computational costs of the optimization procedure while providing accuracy superior to the approaches involving simplified mask models. RBM furthermore provides rigorous error estimators, which assure the quality and reliability of the reduced basis solutions. We apply the reduced basis method to a 3D SMO example. We quantify performance, computational costs and accuracy of our method.

As a photomask feature size shrinks, chrome (Cr) dry etching process is one of the most critical steps which define the performance of critical dimensions (CDs). In consequence, plasma conditions should be maintained stable in a etch chamber. In this work, advanced methodologies using plasma monitoring tools are introduced; Optical Emission Spectroscopy (OES) and the Self-Excited Electron Resonance Spectroscopy (SEERS). After an etch chamber was monitored with these tools, plasma conditions could be categorized with respect to the three parameters; the spectra, the electron collision rate, and the electron density distributions. Finally, it is possible to predict the CD performance of the chamber by checking the specific plasma parameters.

Variations in critical dimension (CD) as a function of the proximity of an individual feature to other exposed areas are a continuing problem both in mask fabrication and in optical lithography. For example, the CD uniformity (CDU) may degrade significantly depending on the proximity to densely or sparsely exposed areas. These pattern density effects will continue to worsen as feature sizes decrease to 22 nm and below. Pattern density effects in electron beam lithography using chemically amplified resists are believed to arise from several sources. One such source, fogging, refers to the backscattering of secondary electrons onto the resist to cause deviations from the nominal pattern size. A second contributor is acid volatility, where photogenerated acid is presumed to redeposit on the wafer or mask during exposure or bake; here we refer to this effect as chemical flare. A third source of pattern density effects is develop loading, which results in local depletion of developer in highly exposed regions. All three of these may simultaneously contribute to a net observed CD variation. In this report we describe the application of two different techniques for evaluating these proximity effects. The first is based on electron-beam lithography patterning, and compares CD values of test patterns which are exposed under brightfield and dark-field conditions. The second uses a series of different test patterns formed by DUV (248nm) exposure and a custom liquid flow cell to separately characterize resist related density effects.

In this paper, new metric, acid concentration distribution image log slope (AILS) is suggested to predict pattern failure in photo lithography. By introducing AILS, pattern fidelity can be determined as numbers. With evaluating at the top 10% and bottom 10% of photo resist, various kinds of pattern failures are categorized and they can be predicted to be failed or not. The simulation results are compared with wafer experiment results and shows great prediction accuracy. In order to evaluate hot spot regarding pattern failure in all possible pitch and duty ratio, in-house image quality analysis tool is used and compared with wafer experimental results. Minimum normalized AILS (NAILS) to cause pattern bridge is larger than that to cause lift off. Both pattern failures are dependent of AILS and CD but the effect of CD on pattern failure is stronger than AILS's

The continued shrink of integrated circuit patterns increases the demand for reticle enhancement techniques (RET). The application of Sub Resolution Assist Features (SRAFs) is pushing mask processes to the resolution limit. Many Chemically Amplified Resists (CAR) used in current photomask processes do not have the capability to fully meet the current demand for SRAF resolution. Often the resulting quality of small SRAFs suffers from pattern fidelity limitations like Line End Shorting (LES) and corner rounding. While small SRAFs might physically resolve on the mask, these limitations cause massive nuisance detections at defect inspections. In a productive environment, high levels of nuisance detections are not acceptable due to the cycle time impact from classification and review. The AMTC systematically investigated the SRAF capability of different mask processes in order to better understand the process limitations as well as to predict the manufacturability of customer patterns. This investigation uses high sensitivity inspections of a specially designed test pattern to determine the SRAF capability limits. An overview of the predicted SRAF capabilities for different resists and blank substrates is provided along with verification on customer layouts.

The lithography challenges posed by the 22 nm node continue to place stringent requirements on photomasks. The dimensions of the mask features continue to shrink more deeply into the sub-wavelength scale. In this regime residual mask electromagnetic field (EMF) effects due to mask topography can degrade the imaging performance of critical mask patterns by degrading the common lithography process window and by magnifying the impact of mask errors or MEEF. Based on this, an effort to reduce the mask topography effect by decreasing the thickness of the mask absorber was conducted. In this paper, we will describe the results of our effort to develop and characterize a binary mask substrate with an absorber that is approximately 20-25% thinner than the absorber on the current Opaque MoSi on Glass (OMOG) binary mask substrate. For expediency, the thin absorber development effort focused on using existing absorber materials and deposition methods. It was found that significant changes in film composition and structure were needed to obtain a substantially thinner blank while maintaining an optical density of 3.0 at 193 nm. Consequently, numerous studies to assess the mask making performance of the thinner absorber material were required and will be described. During these studies several significant mask making advantages of the thin absorber were discovered. The lower film stress and thickness of the new absorber resulted in improved mask flatness and up to a 60% reduction in process-induced mask pattern placement change. Improved cleaning durability was another benefit. Furthermore, the improved EMF performance of the thinner absorber [1] was found to have the potential to relieve mask manufacturing constraints on minimum opaque assist feature size and opaque corner to corner gap. Based on the results of evaluations performed to date, the thinner absorber has been found to be suitable for use for fabricating masks for the 22 nm node and beyond.

The proportion of mask fabrication in the total cost budget for IC production is increasing, particularly for the double patterning generation. Prolonging mask lifetime is very effective in reducing the total mask cost. The factors shortening the mask lifetime principally damage by cleaning and by 193nm excimer laser irradiation during wafer exposure. In order to solve these issues, Advanced Binary Film (ABF) was developed that is more durable against 193nm irradiation during wafer exposure, and has superior cleaning durability. We confirmed the dry etching characteristics of the ABF, using 100nm thick Chemically Amplified Resist and exposure by 50keV EB tool. We obtained impressive results from the ABF evaluation, through cycle cleaning tests (simulating cleaning during pellicle re-mounting), ArF irradiation damage and the effects on Critical Dimension changes.

Mask topography is only one of the challenges for extending 193nm immersion lithography to 22nm and beyond. Migration to binary but thinner mask absorbers, from the previously employed attenuated phase-shift mask (attnPSM) technology, traded a tolerable loss in contrast for better mask making performance and reduced electromagnetic field (EMF) impact [1]. The relentless technological advances in 193nm lithography required to enable 22nm technology, however, continue to drive the dimensions of mask features deep into sub-wavelength scale. In this regime, residual mask EMF effects can still degrade the imaging performance of critical mask patterns, often in the form of featuredependent biasing and shifts of the plane of best focus that shrink the common process window and magnify the impact of mask errors. In this paper we investigate the potential benefits in EMF effects mitigation provided by further thinning the mask absorber to the minimum possible while retaining the required opacity. This study was motivated by the narrower process variability bands observed on a 22nm structure with high EMF sensitivity, when computed with rigorous EMF simulations using a thinner absorber. Resist measurements on wafers exposed with the same EMF sensitive structure built on either the standard binary mask or the thinner sample, confirmed the lower sensitivity to mask topography of the latter while also providing a significant process window improvement. We further observed that thinner topography allowed for a smaller topography induced bias, resulting in improved mask manufacturability with less risk for mask corrections to be limited by mask manufacturability rules such as small assist features and small corner to corner gaps. Thinning the absorber, however, is typically accompanied by an increase in reflectivity of the mask blank which may influence the nature of stray light in the imaging system. To understand the consequences of increasing the blank reflectivity, a double expose scheme was used to measure stray light and determine the relative contribution from the imaging system optics, the mask blank reflectivity, and pellicle thickness. Initial results show that the increased reflectivity of the thinner absorber film has minimal impact on stray light effects in the scanner and that the overall mask reflectivity at high angles is typically dominated by the pellicle thickness. The thin binary absorber should be used in conjunction with a thin pellicle. In this paper we will also explore other relevant characteristics of these novel mask blanks, such as diffraction efficiency, EMF-induced focus drift, changes in contrast, and the implications for increased reflectivity, smaller assist feature size and other lithographic considerations. These results will be demonstrated with rigorous electromagnetic simulations as well as AIMS and wafer measurements on a set of EMF sensitive structures for 22nm contact and metal layers, while simultaneously verifying that the imaging performance of the remaining patterns is unaffected. The use of thinner absorber film also improves the mask making process, contributing to better mask critical dimension (CD) uniformity and overall better lithographic performance as discussed in [2].

As mask dimensions continue to shrink to meet the ITRS roadmap and with the extension of 193 nm immersion lithography, the masks are affected by electromagnetic field at high NA. Absorber degradation is regularly reported under long term 193 nm exposures in the subwavelength diffraction regime. The damage mechanism known as Electric Field induced Migration of chrome (EFM) partly contributes to the lifetime reduction of advanced masks. The EFM results in a progressive alteration of the Critical Dimension (CD), CD uniformity (CDU) degradation and assist features. This study evaluates the impact and the rate of absorber degradation due to an intensive ArF irradiation on assist features and its influence on the through pitch process window for sub-45 nm technology nodes. Lithographic performance is characterized after cumulative reticle aging stages. The aging test exposures are carried out directly on 193 nm scanner to duplicate the production environment. The analysis of printed wafers is correlated to advanced mask inspection (AIMS^TM). This paper reports results on irradiation damage sensitivity on two types of reticles: conventional 6% attenuated PSM and new binary material OMOG (Opaque MoSi On Glass) reticle. Test patterns have been generated with and without a set of Optical Proximity Corrections (OPC) model calibration structures based on 45nm down to 28nm half-pitch design. The combination of metrology measurements used in this work between printed wafers and reticles enables to define accurately the impact of mask damage caused by EFM effects on various test patterns and CD evolution and highlight some trends about advances masks aging phenomenon.

The Jet and Flash Imprint Lithography (J-FIL^TM)^1-7 process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 10⁴ - 10⁵ imprints. This suggests that tens of thousands of templates/masks will be required. It is not feasible to employ electronbeam patterning directly to deliver these volumes. Instead, a "master" template - created by directly patterning with an electron-beam tool - will be replicated many times with an imprint lithography tool to produce the required supply of "working" templates/masks. In this paper, we review the development of the pattern transfer process for both template and mask replicas. Pattern transfer of resolutions down to 25nm has been demonstrated for bit patterned media replication. In addition, final resolution on a semiconductor mask of 28nm has been confirmed. The early results on both etch depth and CD uniformity are promising, but more extensive work is required to characterize the pattern transfer process.

Nanoimprint lithography (NIL) is one promising candidate for fabricating a patterned media to be used in the next generation of hard disk drives (HDD). It is expected that the pitch, characterizing the feature size of the media will become as small as about 40-50 nm for discrete-track recording (DTR) in 2011 or 2012. There are two major issues, one is fine groove formation and the other is long e-beam writing time. Writing time is estimated more than one week if we use ZEP520A-resist. To solve these problems, master template fabrication processes using combination of silicon substrate and new chemically amplified resist (CAR) were demonstrated by using a rotary stage e-beam writer and 50 nm pitch DTR patterns. Estimated writing speed is three times higher. Also it was demonstrated that silicon master template can be applicable for J-FIL quartz replica process.

We examined the potential of using a mirror-electron-microscope (MEM), which has higher sensitivity than optical inspection tools and faster throughput than scanning electron microscopes (SEMs), as a master template inspection tool. We observed line/space patterns with half pitches of 50-100 nm and in which the width of only one space was slightly changed, using the MEM to verify the detection sensitivity of the dimension error. The MEM was able to detect dimension errors larger than 3 nm in the line/space patterns. From observation of the MEM images at various magnifications, we determined that the sensitivity of MEM did not depend exclusively on the resolution power of the image, and that MEM was sufficient for detecting the defects under the resolution power. If we assume that the field of view (FOV) of the MEM image was 30x30 square μm, and the acquisition time per image was 10 ms, the inspection time for the entire 2.5-inch surface of the master template was estimated to be about 10 hours. MEM is therefore a promising candidate for inspecting nanoimprint master templates due to its high sensitivity and acceptable throughput.

In writing contacts at 32nm half-pitch with 193nm immersion lithography, circular main features and curvilinear subresolution assist features will be desirable on masks. Using conventional methods, the best depth of focus, exposure latitude, and critical dimension uniformity on wafer could only be achieved with unrealizable mask write times. Previous papers have described a gradual improvement over the past two years to avoid this trade-off. For example, Manhattanization of the shapes generated by inverse lithography techniques has reduced the required shot count while maintaining best process windows. Using the MB-MDP technique, total shot count required to print such Manhattanized assist features is further reduced significantly. This paper is the first to present test writing results of 32nm-hp patterns using a conventional variable shaped beam mask writer with the new MB-MDP technique. Using this new technique, best process window and improved critical dimension uniformity are achieved while demonstrating reduced shot count. SEM images of resist patterns written by a production mask writer will be shown.

As the feature sizes of LSI become smaller, the increase in mask manufacturing time (TAT) and cost is becoming critical and posing challenges to the mask industry and device manufacturers. In May 2006, ASET Mask D2I launched a 4-year program for the reduction in mask manufacturing TAT and cost, and the program was completed in March 2010. The focus of the program was on the design and implementation of a synergetic strategy involving concurrent optimization of MDP, mask writing, and mask inspection. The strategy was based upon four key elements: a) common data format, b) pattern prioritization based on design intent, c) an improved approach in the use of repeating patterns, and d) parallel processing. In the program, various software and hardware tools were developed to realize the concurrent optimization. After evaluating the effectiveness of each item, we estimated the reduction in mask manufacturing TAT and cost by the application of results obtained from the Mask D2I programs. We found that mask manufacturing TAT and cost can be reduced to 50% (or less) and to about 60% respectively.

We propose a new aperture stage for shaped e-beam exposure tools. This aperture stage is able to print an "L" shape in a single exposure shot. The aperture may be used in mask- and wafer-patterning e-beam tools. The physical and mechanical nature of the aperture appears to be fundamentally similar to existing apertures that form rectangular shapes, yet it reduces the required shot count for exposure by as much as half.

To reduce cost, implant levels usually use masks fabricated with older generation mask tools, such as laser writers, which are known to introduce significant mask errors. In fact, for the same implant photolithography process, Optical Proximity Correction (OPC) models have to be developed separately for the negative and positive mask tones to account for the resulting differences from the mask making process. However, in order to calibrate a physical resist model, it is ideal to use single resist model to predict the resist performance under the two mask polarities. In this study, we show our attempt to de-convolute mask error from the Correct Positive (CP) and Correct Negative (CN) tone CD data collected from bare Si wafer and derive a single resist model. Moreover, we also present the predictability of this resist model over a patterned substrate by comparing simulated CD/profiles against wafer data of various features.

A new method for predicting the reflection from an extreme ultraviolet (EUV) multilayer is described which when implemented into the new Defect Printability Simulator (DPS) can calculate the image produced by an EUV mask with a buried defect several orders of magnitude faster than the finite difference time domain (FDTD). A new buried defect compensation method is also demonstrated to correct the in focus image of a line space pattern containing a buried defect. The new multilayer model accounts for the disruption of the magnitude and phase of the reflected field from an EUV multilayer defect. It does this by sampling the multilayer on a non-uniform grid and calculating the analytic complex local reflection coefficient at each point. After this step, the effect of the optical path difference due to the surface defect profile is added to the total reflected field to accurately predict the reflected magnitude and phase at all points on the multilayer surface. The accuracy of the new multilayer model and the full DPS simulator is verified by comparisons to FDTD simulations. The largest difference between the two methods was 0.8nm for predicting the CD change due to a buried defect through focus. This small difference is within the margin of error for FDTD simulations of EUV multilayers. The runtime of DPS is compared to extrapolated FDTD runtimes for many simulation domain sizes and DPS is 4-5 orders of magnitude faster for all cases. For example, DPS can calculate the reflected image from a 1μm x 1μm mask area in less than 30 seconds on a single processor. FDTD would take a month on four processors. The new compensation strategy demonstrated in this work is able to remove all CD error in the simulated image due to a buried defect in a 22nm dense line space pattern. The method is iterative and a full DPS simulation is run for every iteration. After each simulation, the absorber pattern is adjusted based on the difference of the thresholded target image and thresholded defective image. This method is very simple and does not attempt to compensate for the defect through focus, but it does demonstrate the usefulness of a fast simulator for compensation.

A new method for simulating mask topography effects is described. A model comprising a set of functions is generated based on the results of test patterns simulated using rigorous mask simulation. The functions are combined with the thin mask diffraction pattern in order to create a modeled thick mask diffraction pattern. The mask diffraction pattern is subsequently used in the lithosim^TM simulation tool to generate the wafer image. Results are described for 1D and 2D test structures. The 1D test structures is a line and space test pattern where the line is set at 40nm width and the space is varied from 40nm to 1000nm. The illumination setting chosen was a TE polarized dipole illumination with a pole distance of 0.9 and a pole radius of 0.01. First the accuracy of the simulator itself was verified using thin mask calculation and comparing the data to another simulator. The intensity profiles are virtually identical. The RMS of the difference between the two plots is 8E-05. Next the model is compared to the rigorous calculation. The RMS of the difference between the two plots is 3E-03. The standard deviation of the CD difference between the model and the rigorous calculation, calculated for 5 thresholds (0.1, 0.11, 0.12, 0.13, and 0.14) and for all the structures, is 0.38nm. We also demonstrate that the mask model can be used with different optical settings by showing an example of two additional defocus values with an identical RMS of 3E-03. For the 2D test pattern made of a dense contact array, the mask fields are computed using rigorous calculation and compared to the model. The difference between the fields is within the error of the rigorous calculation. The resulting wafer images are almost identical. No re-scaling of the data was applied to either the mask fields or the wafer images.

A new modeling technique to accurately represent the mask and wafer process behavior is presented. The lithography simulation can be done in three steps: i) mask simulation, ii) latent image calculations and iii) resist process simulation. The leading edge designs, such as 32 nm and beyond, require higher-fidelity models to adequately represent each of these actual processes. Effects previously considered secondary, have become more pronounced with each new technology node. In this approach, we utilized separate physical models for both mask and wafer processes. We demonstrate that the residual errors can be further reduced when nonlinear mappers are used in addition. The advantage of the presented approach compared to standard curve-fitting or statistics-based models is its predictive power and adaptive nature. The physical model parameters were calibrated by a genetic algorithm whose details were outlined in [1]. The nonlinear mapper model parameters were identified by a gradient descent method. Given the computational requirements for a practical solution, our approach uses graphics processors as well as CPUs as computation hardware.

As the optical lithography advances into the sub-30nm technology node, the various candidates of lithography have been discussed. Double dipole lithography (DDL) has been a primary lithography candidate due to the advantages of a simpler process and a lower mask cost compared to the double patterning lithography (DPL). However, new DDL requirements have been also emerged to improve the process margin and to reduce the mask-enhanced error factor (MEEF), which is to maximize the resolution and image contrast. There are two approaches in DDL i.e. model basedand rule based-DDLs. Rule-based DDL, in which the patterns are decomposed by the simple rules such as x- and ydirectional rules, shows the low process margin in the 2-dimension (2D) patterns, i.e., line-end to line-end, line-end to bar and semi-isolated bars. In this paper, we first present various analyses of our new model-based DDL (MBDDL) method. Our goal is to maximize the process margin of the 2D patterns. Our main contributions are as follows. (1) We generate new 2D test patterns including various configurations of the metal layer. The new 2D patterns can be used to optimize the parameters of the MBDDL and to build the good design rules. The purpose of building the good design rules is improving the process margin of the certain 2D patterns with the low process margin in spite of optimizing the parameters of MBDDL. (2) We optimize the initial layout decomposition, which is the first step of MBDDL and affects the whole of MBDDL quality. In addition, the model-based decomposition is applied with the process-window OPC (PWOPC) in terms of the criteria of edge placement error (EPE) and mask rule checking (MRC) violation. Our new model-based approach including the newly designed test patterns and optimized decomposition parameters leads to the improved depth of focus (DOF) and enhanced the exposure latitude (EL). We achieve the 80nm DOF, which is the manufacturable margin for the metal 1 layer at the sub-30nm node.

This paper tries to clarify the requirements for Source-Mask co-Optimization (SMO) type complex masks for low k₁ technology nodes using a dedicated test mask. The current status of mask CD requirements and inspection capability for Free Form (FF) SRAFs which give wider process window are discussed by comparing with Rectangular Shape (RS) SRAFs. From CD deviation analysis with CD bias change at both main and SRAF patterns, the importance of CD control at entire SRAF is emphasized although the partial lack of SRAF seems to give less impact on the main pattern lithography performance. It is also suggested that SRAF printability of FF-SRAF needs to be carefully controlled with mask bias error consideration. To identify the defects which give impact on litho performance, simulation-based defect printability prediction (M-LMC) using inspection images is evaluated and found to be an important enabler for complex mask inspection. The simulation-image based defect analysis helps to reduce the nuisance defects, and greatly saves analysis time of measurement on Aerial Image Measurement System (AIMS^TM). To introduce the complex free form mask into production, mask-writing shot-count reduction is also evaluated. It is shown that fragmentation using Model- Based (MB) Mask Data Preparation (MDP) effectively reduces the mask writing shot counts with using overlapping of the patterns.

For semiconductor IC manufacturing at sub-30nm and beyond, aggressive SRAFs are necessary to ensure sufficient process window and yield. Models used for full chip Inverse Lithography Technology (ILT) or OPC with aggressive SRAFs must predict both CDs and sidelobes accurately. Empirical models are traditionally designed to fit SEMmeasured CDs, but may not extrapolate accurately enough for patterns not included in their calibration. This is particularly important when using aggressive SRAFs, because adjusting an empirical parameter to improve fit to CDSEM measurements of calibration patterns may worsen the model's ability to predict sidelobes reliably. Proper choice of the physical phenomena to include in the model can improve its ability to predict sidelobes as well as CDs of critical patterns on real design layouts. In the work presented here, we examine the effects of modeling certain chemical processes in resist. We compare how a model used for ILT fits SEM CD measurements and predicts sidelobes for patterns with aggressive SRAFs, with and without these physically-based modeling features. In addition to statistics from fits to the calibration data, the comparison includes hot-spot checks performed with independent OPC verification software, and SEM measurements of on-chip CD variation using masks created with ILT.

Source Mask Optimization (SMO) technique is an advanced RET with the goal of extending optical lithography lifetime by enabling low k1 imaging [1,2]. Most of the literature concerning SMO has so far focused on PV (process variation) band, MEEF and PW (process window) aspects to judge the performance of the optimization as in traditional OPC [3]. In analogy to MEEF impact for low k1 imaging we investigate the source error impact as SMO sources can have rather complicated forms depending on the degree of freedom allowed during optimization. For this study we use Tachyon SMO tool on a 22nm metal design test case. A free form and parametric source solutions are obtained using MEEF and PW requirements as main criteria. For each type of source, a source perturbation is introduced to study the impact on lithography performance. Based on the findings we conclude on the choice of freeform or parametric as a source and the importance of source error in the optimization process.

The current e-beam proximity effect correction equations are reviewed in the context of model-based fracturing where shots can overlap and the dose of each shot can be set individually. A new set of equations is proposed and verified. The formulation is shown to lift some restrictions imposed by the older formulation such as the minimum shot size dimension and the type of model used to describe forward scattering effects. The new model does not require the function to be Gaussian or the operation with the dose map to be a convolution. We also demonstrate that using current mask writing equipment, the correction of overlapping shots can be performed accurately if the correction of each shot is performed taking into account all the shots. Verification is done using two different approaches. The first solution consists of using directly the modified proximity effect equations to calculate the dose for each shot. The second solution makes the correction a part of the model-based fracturing process. The results obtained for both approaches are identical showing that the theory and the implementations are correct.

Designers always want maximum freedom in design, but they understand that chips have to yield and at a reasonable cost. The strong ecosystem support of restricted design rules to make 193i workable for sub-30nm nodes is evidence of this. In direct write e-beam, there are design insights that lead to a tangible improvement in throughout while minimizing the restrictions on the designer. It turns out that a smaller number of primitive cells in a standard cell methodology can enable data compression for multi-beam systems, and enable faster write times for character projection in VSB-based multiple column machines. This requires a co-design of the standard cell library with the stencil mask (either virtual or real) that goes into the machine. This co-design step is required only once per library and not on a design-by-design basis, thus minimizing the impact on designers. 10-20X speedups in e-beam throughput depending on layer are seen in typical layout examples for character projection machines.

Maskless pattern generation capability in combination with practically limitless resolution made probe-forming electron beam systems attractive tools in the semiconductor fabrication process. However, serial exposure of pattern elements with a scanning beam is a slow process and throughput presented a key challenge in electron beam lithography from the beginning. To meet this challenge imaging concepts with increasing exposure efficiency have been developed projecting ever larger number of pixels in parallel. This evolution started in the 1960s with the SEM-type Gaussian beam systems writing one pixel at a time directly on wafers. During the 1970s IBM pioneered the concept of shaped beams containing multiple pixels which led to higher throughput and an early success of e-beam direct write (EBDW) in large scale manufacturing of semiconductor chips. EBDW in a mix-and match approach with optical lithography provided unique flexibility in part number management and cycle time reduction and proved extremely cost effective in IBM's Quick-Turn-Around-Time (QTAT) facilities. But shaped beams did not keep pace with Moore's law because of limitations imposed by the physics of charged particles: Coulomb interactions between beam electrons cause image blur and consequently limit beam current and throughput. A new technology approach was needed. Physically separating beam electrons into multiple beamlets to reduce Coulomb interaction led to the development of massively parallel projection of pixels. Electron projection lithography (EPL) - a mask based imaging technique emulating optical steppers - was pursued during the 1990s by Bell Labs with SCALPEL and by IBM with PREVAIL in partnership with Nikon. In 2003 Nikon shipped the first NCR-EB1A e-beam stepper based on the PREVAIL technology to Selete. It exposed pattern segments containing 10 million pixels in single shot and represented the first successful demonstration of massively parallel pixel projection. However the window of opportunity for EPL had closed with the quick implementation of immersion lithography and the interest of the industry has since shifted back to maskless lithography (ML2). This historical overview of EBDW will highlight opportunities and limitation of the technology with particular focus on technical challenges facing the current ML2 development efforts in Europe and the US. A brief status report and risk assessment of the ML2 approaches will be provided.

Direct writing of patterns onto silicon wafers in production has been a goal of many in the semiconductor industry for over four decades, but the low throughput of available or projected maskless tools relative to available masked optical tools at any point in time has always led to the conclusion that maskless lithography is not cost competitive. However a complete assessment of cost versus benefit for maskless lithography is much more complex than a simple tool-level comparison of lithography cost for a given semiconductor technology node. There are many different maskless tool implementation manufacturing strategies, and in each one not only does the cost of wafer processing including masks need to be considered, but also the relative impact of maskless lithography on manufacturing methodology, yields, and cycle times, potential design rule improvements relative to maskless optical schemes at any given semiconductor generation node, and potential reduction in new product development time. In this paper a recently published economic model for maskless lithography implementation in production is extended to include these other issues in addition to comparative wafer manufacturing cost. While lack of maskless lithography production data limits the conclusions that can be drawn, the assessment does indicate that depending on its printing performance specifications maskless tools can be designed to be cost-effective in production for today's processes even if the maskless tool has throughputs much smaller than masked optical systems, perhaps even as low as a few wafers per hour.

193nm Optical lithography has powered the industry's growth for the last 10 years and multiple patterning is poised to extend 193nm even further. There is a growing trend in Logic design for manufacturing, with high-volume manufacturing (HVM) firms adopting a layout style using unidirectional single-pitch straight lines in poly and metal layers. These layouts lend themselves to a complementary lithography approach. First, unidirectional lines are patterned with Optical lithography. Second, these lines are "cut" to form the desired layout. In this paper, we present EBDW as a complement to optical lithography for line-cutting. We show how e-beam multiple-column architecture, optimized for line-cutting, is the best for patterning critical layers at advanced nodes as Complementary Lithography.

The e-beam lithography is faced with increasing challenges to achieve a satisfying patterning of structures with critical dimensions of about 32 nm or below. The reason for this issue is the unavoidable blurring of the deposited e-beam energy due to beam blur, electron scattering (forward and backward), and resist effects. The distribution of the finally deposited dose differs from the dose weighted geometry of the printed layout. In general, the finally deposited dose is described as convolution of the layout with a process specific proximity function being a model for the unavoidable blurring. This process proximity function (PPF) is often approximated by a superposition of two or more Gaussian functions. Thus, the electron forward scattering and resist effects, being most critical to the pattern fidelity, are often described altogether by the so called alpha-parameter of the PPF. Due to these physical reasons, when the desired critical dimension of a structure is near or below the alpha-parameter of the PPF, it may be just impossible to print the structure because of the vanishing image contrast due to the blurring. It was shown by means of the simulation feature of the ePLACE data prep package that in this situation a modification of both the geometry and the dose assignment of the shapes will significantly increase the contrast of the deposited energy and thus, even preserve the printability of critical structures. This geometrically induced dose correction (GIDC) method is implemented in the ePLACE package. The simulation results for test structures are now validated by exposures of test patterns and its results clearly establish the practical advantage of the new method. In this paper we will publish the results of the related exposures - done on Vistec SB3050 series shaped e-beam writers - demonstrating the practical importance of the GIDC method for layouts with critical dimensions of 32 nm and below.

The authors proposed a throughput enhancement of an e-beam direct writer by the combination of three key technologies; multi column cell, character projection, and high current density column technologies. They have finished proof-of-concept evaluations of multi column cell and character projection in the MASK-D2I project of ASET, including mix-and-match overlay results of better than 5nm. They found adequate conditions for the application of these three technologies to achieve the throughput above 5 wafers per hour in an e-beam direct writer.

The development of next-generation lithography (NGL) such as EUV, NIL and maskless lithography (ML2) are driven by the half pitch reduction and increasing integration density of integrated circuits down to the 22nm node and beyond. For electron beam direct write (EBDW) several revolutionary pixel based concepts have been under development since several years. By contrast an evolutionary and full package high throughput multi electron-beam approach called Multi Shaped Beam (MSB), which is based on proven Variable Shaped Beam (VSB) technology, will be presented in this paper. In the recent decade VSB has already been applied in EBDW for device learning, early prototyping and low volume fabrication in production environments for both silicon and compound semiconductor applications. Above all the high resolution and the high flexibility due to the avoidance of expensive masks for critical layers made it an attractive solution for advanced technology nodes down to 32nm half pitch. The limitation in throughput of VSB has been mitigated in a major extension of VSB by the qualification of the cell projection (CP) technology concurrently used with VSB. With CP more pixels in complex shapes can be projected in one shot, enabling a remarkable shot count reduction for repetitive pattern. The most advanced step to extend the mature VSB technology for higher throughput is its parallelization in one column applying MEMS based multi deflection arrays. With this Vistec MSB technology, multiple shaped beamlets are generated simultaneously, each controllable individually in shape size and beam on time. Compared to pixel based ML2 approaches the MSB technology enables the maskless, variable and parallel projection of a large number of pixels per beamlet times the number of beamlets. Basic concepts, exposure examples and performance results of each of the described throughput enhancement steps will be presented.

Extreme Ultraviolet Lithography (EUVL) offers the promise of dramatically improved resolution at the price of introducing a complex web of new lithographic challenges. The most conspicuous departure from DUV lithography is that exposure the wavelength is reduced from 193 to 13.5nm. Under exposure at this short EUV wavelength, all materials absorb. Consequently the scanner optics and masks must be reflective and wafer exposure occurs in vacuum without a pellicle to protect the mask. This represents a dramatic shift from the current DUV mask use case. For example, the mask will have to be cleaned after exposure to remove contamination accumulated instead of being protected for its lifetime by a transparent pellicle. The impact of cycling through the exposure tool and being cleaned multiple times will be studied using particle inspection, scatterometry, reflectometry and AFM measurements. The results will be used to identify contamination modes and to propose best practices for EUVL mask exposure.

We study the impact of mask topography effects on imaging with high NA. We show that with the current mask technology, it is possible to obtain reasonable imaging results up to 0.32 NA, however, for higher NA, the reticle design needs to be optimized in order to ensure proper imaging. We examine the influence of the multilayer and the effects of the finite absorber height on the imaging with high NA optics and devise measures which have to be taken into consideration in order to guarantee proper imaging at high NA.

EUVL requires the use of reflective optics including a reflective mask. The reticle blank contains a reflecting multilayer, tuned for 13.5nm, and an absorber which defines the dark areas. The EUV mask is a complex optical element with many more parameters than the CD uniformity of the patterned features that impact the final wafer CDU. Peak reflectivity, centroid wavelength and absorber stack height variations need to be tightly controlled for optimum performance. Furthermore the oblique incidence of light in combination with the small wavelength compared to the mask topography causes a number of effects which are unique to EUV, such as an H-V CD offset and an orientation dependent pattern placement error. These so-called shadowing effects can be corrected by means of OPC, but also need to be considered in the mask stack design. In this paper we will show that it is possible to improve the imaging performance significantly by reducing the sensitivity to mask making variations such as capping layer thickness and absorber stack height variations. The impact of absorber stack height variations on CD and proximity effects will be determined experimentally by changing the local absorber stack height using the novel e-beam based reticle repair tool MeRiT® HR 32 from Carl Zeiss in combination with exposures on ASML's alpha demo tool. The impact of absorber reflectivity will be shown experimentally and used to derive requirements for the reticle border around the image field, as well as possible correction techniques.

Reticle quality and the capability to qualify a reticle remain key issues for EUV Lithography. In this paper, we report on recent advancements that extend the capability of a 193 nm mask inspector to meet requirements for the 22 nm HP / 15 nm Logic node. This work builds upon previous work that was published earlier this year, by D. Wack¹, et. al. Meeting these requirements requires development of a number of novel capabilities for mask inspection, including the use of offaxis illumination, various polarization modes, and use of an optimized absorber stack for EUV masks. In addition, we discuss the challenges of inspecting EUV masks in die-to-database mode, and how tone inversion can be successfully modeled. Lastly, we show that this same 193 nm mask inspector, with the use of proprietary algorithms, can be extended to meet industry requirements for EUV phase defect blank inspection.

A combination of blank inspection (BI), patterned mask inspection (PMI) and wafer inspection (WI) is used to find as many as possible printing defects on two different EUV reticles. These multiple inspections result in a total population of known printing defects on each reticle. The printability of these defects is first confirmed by wafer review on wafers exposed on the full field ASML Alpha Demo Tool (ADT) at IMEC. Subsequently reticle review is performed on the corresponding locations with both SEM (Secondary Electron Microscope) and AFM (Atomic Force Microscope). This review methodology allows to separate absorber related mask defects and multi layer (ML) related mask defects. In this investigation the focus is on ML defects, because this type of reticle defects is EUV specific, and not as evolutionary as absorber defects which can be mitigated in more conventional ways. This work gives evidence of critical printing ML defects of natural origin, both pits as shallow as 3nm and bumps just 3nm high at the surface. Wafer inspection was the first inspection technique to detect these ML-defects with marginal surface height distortion, because both state-of-the-art PMI and especially standard BI on the Lasertec M1350 had failed to detect these defects. Compared to standard BI, the more advanced Lasertec M7360 is found to have much better sensitivity for printing MLdefects and our work so far shows no evidence of printing ML defects missed by this tool. Unfortunately it was also observed that this required sensitivity was only achieved at the cost of an unacceptable nuisance rate, i.e., with a too high number of detections of non-printing defects. Optical blank inspection is facing major challenges : It needs not only to find ML defects with height distortions of 3nm and less (and in theory maybe even 0nm), but also it must be able to disposition between such likely-printing and non-printing defects.

The key challenge before EUVL is to make defect-free masks hence it is important to identify the root cause of defects, and it is also necessary to establish suitable critical mask defect size for the production of ULSI devices. Selete has been developing EUV mask infrastructures such as a full-field actinic blank inspection tool and 199nm wavelength patterned mask inspection tool in order to support blank/mask supplier in reducing blank/mask defects which impact on wafer printing. In this paper, we evaluate the printability of multilayer defects and of absorber defects exposed by a full-field scanner EUV1, using full-field actinic/non-actinic blank inspection tool and 199nm wavelength patterned mask inspection tool. And based on the results of native defect analysis of blank/mask, we ascertain that blank inspection with actinic is necessary for mask fabrication in order to reduce the risk of missing phase defects, which hardly can be detected by patterned mask inspection tool.

We have developed an actinic full-field inspection system to detect multilayer phase defect with dark field imaging. A new CCD camera was installed onto the system with an objective of throughput and inspection sensitivity improvement. As the result, the throughput was improved from 14.25 to 4.75 hours per plate, and the detection probability for 1.2 nmhigh 40 nm-wide defect was found to be 95.7 %. This means that the system has a potential of its extendibility to beyond 22 nm HP inspection.

Achieving the specifications of resolution, sensitivity and line width roughness (LWR) of wafer resist is one of the top challenges of bringing extreme ultraviolet lithography (EUVL) into high volume manufacturing. Contributions to the resist LWR on wafer can be divided into two categories; chemical properties of the resist and aerial image. Chemical properties of the resist are complicated and many factors contribute to LWR, such as polymer size, sensitivity, surface reaction etc. Aerial image LWR is much simply determined by the optical properties of a mask and a scanner. Since very small LWR value of the resist is needed, EUV mask LWR is also set very severely from ITRS ^[1]. In our previous work ^[2], we demonstrated current mask LWR as comparing them with mask resist LWR and absorber LWR. As a result, we found that the absorber's LWR almost depends on resist patterning. In this paper, we will present the influence of resist patterning on absorber LWR comparing resist materials and EB tools. From the results, LWR has been reduced by 10-20% by improving EB tool. However, the LWR value at line and space pattern for 22nm-hp case have not met target of ITRS' roadmap while, by using Non-CAR, the LWR value has met the target. In particularly, the value at isolated line is dramatically improved using Non-CAR.

Station Controllers have existed in Wafer FABs for well over a decade now. Until recently, relatively low volume of masks produced did not justify the added cost of enabling SECS/GEM on the tools and implementing full automation. Starting with a drive to improve yield and the need for advanced capabilities such as Excursion Protection, a combination of recent factors has driven the need for greater automation. This paper will discuss key capabilities, architectural highlights and strategies in implementation. In addition we will discuss the challenges faced and key learning in development and validation of the station controllers in a full production environment with minimum impact or interruption to the processing of WIP.

Lean manufacturing is a systematic method of identifying and eliminating waste. Use of Lean manufacturing techniques at the IBM photomask manufacturing facility has increased efficiency and productivity of the photomask process. Tools, such as, value stream mapping, 5S and structured problem solving are widely used today. In this paper we describe a step-by-step Lean technique used to systematically decrease defects resulting in reduced material costs, inspection costs and cycle time. The method used consists of an 8-step approach commonly referred to as the 8D problem solving process. This process allowed us to identify both prominent issues as well as more subtle problems requiring in depth investigation. The methodology used is flexible and can be applied to numerous situations. Advantages to Lean methodology are also discussed.

For mask signature matching in the case of alternating phase-shifting mask it is shown that it is can be achieved using matching of aerial imaging. This is in contrast to the traditional approach of manufacturing an identical copy of the reference mask. Beside description of the method AIMS and wafer data are shown that proof its successful application on a product mask.

Contrary to the prior assumptions of its technical demise, deep UV (DUV) femtosecond pulsed laser repair of photomasks is continuing to mature and improve as a technology. Similar to the optical enhancements that allow for 193 nm wavelength light to continue being used down to the 32, or even in some cases 22 nm, node, the process regimes for this type of laser repair continue to expand as new processes are discovered. This work reviews the qualification of repair performance for production at a major wafer foundry site. In addition advances are shown in the area of through-pellicle repair (TRP) process development. These advances include the preferential (versus surrounding reference mask structures) removal of soft defects and the capability to remove or manipulate particles on top of a flat absorber region with no detectable removal of the absorber. These developments will further demonstrate the progressive decoupling of the laser repair spot size from the minimum technology node for laser repair.

The mask industry has recently witnessed an increasing number of new MoSi mask blank materials which are quickly replacing the older materials as the standard in high end mask shops. These new materials, including OMOG (opaque MoSi on glass) and high transmission (Hi-T) films, are driven foremost by the need to reduce feature size through resolution enhancement techniques (RET). The subject of this paper is a new low stress, Hi-T material which addresses the challenges presented by transitioning to smaller technology nodes including difficulties with pattern transfer, cleaning and repair. This material, based on currently employed MoSi films, eliminates process steps and utilizes a thinner overall substrate stack than currently used Hi-T schemes allowing an increase in critical dimension (CD) uniformity and feature resolution and more robustness due to a lower aspect ratio. While this new material is MoSi based the small compositional change requires, in some cases, a significant change in processing. Among the most impacted areas are the etch, clean and repair steps. Given the potential for defects to manifest on masks, repair is an invaluable step that can significantly impact the overall yield and lead to a reduction in cycle time¹. The Carl Zeiss MeRiT® electron beam mask repair line provides the most advanced repair capabilities allowing a wide range of repairs to be performed on a number of mask types². In a joint effort between MP Mask Technology Center LLC and Carl Zeiss SMT, this paper focuses on the benefits of the new Hi-T mask blank and the challenges it presents to the repair community. The differences between the new low stress, Hi-T material and current Hi-T technologies are presented and on site compositional analysis is performed with x-ray photoelectron spectroscopy (XPS) to illuminate the compositional differences. The development of a repair process for the new material utilizing the on-site Carl Zeiss MeRiT® MG 45 is presented along with several repairs and their AIMS^TM results.

Currently, repair machines used for advanced photomasks utilize principle method like as FIB, AFM, and EB. There are specific characteristic respectively, thus they have an opportunity to be used in suitable situation. But when it comes to EUV generation, pattern size is so small highly expected as under 80nm that higher image resolution and repair accuracy is needed for its machines. Because FIB machine has intrinsic damage problem induced by Ga ion and AFM machine has critical tip size issue, those machines are basically difficult to be applied for EUV generation. Consequently, we focused on EB repair tool for research work. EB repair tool has undergone practical milestone about MoSi based masks. We have applied same process which is used for MoSi to EUV blank and confirmed its reaction. Then we found some severe problems which show uncontrollable feature due to its enormously strong reaction between etching gas and absorber material. Though we could etch opaque defect with conventional method and get the edge shaped straight by top-down SEM viewing, there were problems like as sidewall undercut or local erosion depending on defect shape. In order to cope with these problems, the tool vender has developed a new process and reported it through an international conference [1]. We have evaluated the new process mentioned above in detail. In this paper, we will bring the results of those evaluations. Several experiments for repair accuracy, process stability, and other items have been done under estimation of practical condition assuming diversified size and shape defects. A series of actual printability tests will be also included. On the basis of these experiments, we consider the possibility of EB-repair application for 20nm pattern.

At the Photomask Japan 2010, we reported on the cleaning process durability and the EUV light shielding capability of FIB- and EB-CVD film based on carbon, tungsten and silicon containing precursors. The results were that the tungsten based FIB-CVD film showed no loss of film thickness after dry cleaning process, and the calculation showed that 56nm thick was sufficient for repairing clear defects on EUV mask with 51nm thick of absorber layer. On the other hand, carbon based FIB-CVD film suffered considerable loss in its film thickness and needed more than 180nm thick even if the 10nm thick of buffer layer between the CVD films and the capping layer supported the EUV light shield. In this paper, we will report on a newly developed repair method of clear defects on EUV mask using an FIB technique. The clear defects were repaired by removing or damaging the reflective ML (multi layer) underlying the clear defect area instead of applying the conventional FIB-CVD (Focused Ion Beam-Chemical Vapor Deposition) films. After removing the ML, the cross sectional pattern angle was approximately 83 degree and the sidewalls were covered with 15nm thick of Si and Mo mixing layer caused by Ga ions exposure. The performance of defect repair was evaluated by SFET (Small Field Exposure Tool) printability test. The exposure results showed that the ML etched area behaved as low reflection area and the printed CDs were proportional to the mask opening CDs. The study also revealed that the ML etched pattern was not sensitive to 50nm of focus error.

The exposure tools have been advanced for finer patterns and higher throughput. However, it causes the increase of accumulation of exposure dose on mask, which induces the mask CD growth. This issue has been reported as the radiation damage and brought the low yield of device chips [1, 2, 3]. As the solution, the radiation damage can be reduced by the ultra extreme dry air in exposure tool [4]. It is difficult to adopt dry air to all exposure tool due to cost. In this work, we tried to solve the radiation damage from photomask making approach. The attenuated phase-shift mask (att. PSM) was chosen for this evaluation because its damage is severest. The test plates of att. PSM were exposed by ArF laser, and the amount of CD degradation and the composition change in damage area were investigated. By the analyses of TEM and EDX, it was confirmed that the root cause of radiation damage is oxidation of MoSi film. Therefore, the approaches from mask process and material were tried to prevent MoSi film from oxidation. As a result, the approach from mask material, especially modification of MoSi film is effective. And the characteristics of new MoSi film, such as CD performances, cross section, and cleaning durability, were compared with conventional att. PSM. These results show the characteristics of two masks are equivalent. Att. PSM with new MoSi film is promising solution to improve radiation damage.

The fundamentals of droplet-based cleaning of photomasks are investigated and performance regimes that enable the use of binary spray technologies in advanced mask cleaning are identified. Using phase Doppler anemometry techniques, the effect of key performance parameters such as liquid and gas flow rates and temperature, nozzle design, and surface distance on droplet size, velocity, and distributions were studied. The data are correlated to particle removal efficiency (PRE) and feature damage results obtained on advanced photomasks for 193-nm immersion lithography.

Makers and users of advanced technology photomasks have seen increased difficulties with the removal of persistent, or stubborn, nano-particle contamination. Shrinking pattern geometries, and new mask clean technologies to minimize haze, have both increased the number of problems and loss of mask yield due to these non-removable nano-particles. A novel technique (BitClean^TM) has been developed using the Merlin^TM platform, a scanning probe microscope system originally designed for nanomachining photomask defect repair. Progress in the technical development of this approach into a manufacture-able solution is reviewed and its effectiveness is shown in selectively removing adherent particles without touching surrounding sensitive structures. Results will also be reviewed that were generated in the qualification and acceptance of this new technology in a photomask production environment. These results will be discussed in their relation to the minimum particle size allowed on a given design, particle removal efficiency per pass of the NanoBit^TM (PRE_PP), and the resultant average removal throughput of particles unaffected by any other available mask clean process.

In this test, we evaluated the carbon contamination removal capabilities of various kinds of cleaning methods. And we also evaluated the degradation of multilayer (with capping layer) caused by the cleaning process. In the contamination removal test, the contamination was formed by a synchrotron irradiation. And in the degradation test, we evaluated Ru-capping layer and Si-capping layer. In the contamination removal test, the reflectivity recovery was confirmed in all cleaning conditions that were evaluated. However, there were differences among the reflectivity recoveries. In particular, plasma cleaning showed high removal capability. In VUV/O3 cleaning, the oxygen concentration influenced the contamination removal capability. In Si-capping layer, none of the cleaning conditions exhibited any significant reflectance change. On the other hand, in Ru-capping layer, a decrease in reflectance was noticed in VUV/O3 cleaning with an oxygen concentration of 500ppm. In a comparison between Ru-capping layer and Si-capping layer, no significant difference was noticed in SPM cleaning, VUV/O3 with oxygen concentration 45ppm, and in plasma with N2/H2 gas condition.

The study of the airborne SO₂ and NH₃ contamination on Cr, MoSi and Quartz photomask surfaces was addressed by the intentional exposure to controlled contaminated air. Experimentally, mask-like layers (representative Cr, MoSi and SiO₂ layers) deposited on wafers were used and then characterized by LPE-IC. Results showed that Cr surfaces clearly present a higher ability to be contaminated than MoSi and even more than Quartz, both for SO₂ and NH₃ (Cr >> MoSi > Quartz). For each mask surface, the NH3 contamination occurred more rapidly than the SO₂ deposition. The contamination of Cr and MoSi surfaces respectively for the 2 contaminants and for SO₂, are governed by Langmuir-type adsorption models allowing then the forecasting of the deposited contaminant amounts depending on the time and the airborne concentration. A very slow and low adsorption process of SO₂ on Quartz is observed whereas the NH3 deposition on MoSi and quartz appear very rapid at ambient concentrations such as a way saturation levels are likely reached in few minutes. Furthermore, a significant enhancement of the SO₂ and NH3 deposition is characterized in clean room humidity versus drier conditions, this effect being extremely drastic for SO₂ on Cr. The knowledge of the contamination behavior of the SO₂ and NH₃ on photomask surfaces is very relevant for the control of the crystal growth /haze occurrence on reticles. Their application led to recommend SO₂ and NH₃ threshold levels lower than 10 pptv in the mask environment to avoid haze beyond one year.

While EUV lithography is approaching the pre-production stage, improving mask defectivity is recognized as a top challenge. The accepted strategy for EUV reticle qualification is to use a combination of a dedicated blank inspection (BI) to visualize EUV-specific multi-layer (ML) defects and patterned-mask inspection (PMI) that must be capable to meet the resolution requirements of the pattern. Actinic inspection is considered the strongest option for the blank inspection because of the limitation of optical light to visualize the nm-high distortions within the ML. Earlier publications showed that wafer inspection (WI) can potentially reveal such mask defects, This is, however, too late within the process. In addition, existing PMI and wafer inspection approaches exhibit limitations in detection capability and gaps are observed between detection of printed defects and defects detected on the mask (and the blank). We compare existing inspection solutions for detection of EUV mask defects (193nm based mask inspection and repeater analysis in a DUV wafer inspection) and present a feasibility study for use of a fast e-beam technology for mask inspection. Finally, we discuss the prospects of existing DUV tools and future e-beam technology to support EUV reticle inspection for current and future nodes.

Fabrication of defect free EUV mask is one of the most critical roadblocks for implementing EUV lithography into semiconductor high volume manufacturing for 22nm half-pitch (HP) node and beyond. At the same time, development of quality assurance process for the defect free EUV mask is also another critical challenge we need to address before the mass production. Inspection tools act important role in quality assurance process to ensure the defect free EUV mask. We are currently evaluating two types of inspection system: optical inspection (OPI) system and electron beam inspection (EBI) system [1, 2]. While OPI system is sophisticated technology and has an advantage in throughput, EBI system is superior in sensitivity and extendability to even small pattern. We evaluated sensitivity of EBI system and found it could detect 25 nm defects on 88nm L/S pattern which is as small as target defect size for 23 nm Flash HP pattern in 2013 in 2009 ITRS lithography roadmap [2, 3]. EBI system is effective inspection tool even at this moment to detect such small defects on 88nm HP pattern, though there are still some challenges such as the slow throughput and the reliability. Therefore, EBI system can be used as bridge tool to compensate insufficient sensitivity of current inspection tools and improve EUV mask fabrication process to achieve the defect free EUV mask. In this paper, we will present the results of native pattern defects founded on large field 88nm HP pattern using advance EBI system. We will also classify those defects and propose some ideas to mitigate them and realize the defect free EUV mask, demonstrating the capability of EBI as bridge tool.

We are developing new electron beam inspection system, named EBeyeM, which features high speed and high resolution inspection for EUV mask. Because EBeyeM has the projection electron microscope technique, the scan time of EBeyeM is much faster than that of conventional SEM inspection system. We developed prototype of EBeyeM. The aim of prototype system is to prove the concept of EBeyeM and to estimate the specification of system for 2Xnm and 1Xnm EUV mask. In this paper, we describe outline of EBeyeM and performance results of the prototype system. This system has two inspection mode. One is particle inspection and the other is pattern defect inspection. As to the sensitivity of EBeyeM prototype system, the development target is 30nm for the particle inspection mode and 50nm for pattern defect inspection mode. The performance of this system was evaluated. We confirmed the particle inspection mode of the prototype system could detect 30nm PSL(Polystyrene Latex) and the sensitivity was much higher than conventional optical blank inspection system. And we confirmed that the pattern defect sensitivity of the prototype system was around 45nm. It was recognized that both particle inspection mode and pattern defect inspection mode met the development target. It was estimated by the performance results of the prototype system that the specification of EBeyeM would be able to achieve for 2Xnm EUV mask. As to 1Xnm EUV mask, we are considering tool concept to meet the specification.

We have developed a highly integrated method of mask and silicon metrology. The aim of this integration is evaluating the performance of the silicon corresponding to Hotspot on a mask. It can use the mask shape of a large field, besides. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used in mask CD-SEM and silicon CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and mask manufacture, and this has a big impact on the semiconductor market that centers on the mask business. As an optimal solution to these issues, we provide a DFM solution that extracts 2-dimensional data for a more realistic and error-free simulation by reproducing accurately the contour of the actual mask, in addition to the simulation results from the mask data. On the other hand, there is roughness in the silicon form made from a mass-production line. Moreover, there is variation in the silicon form. For this reason, quantification of silicon form is important, in order to estimate the performance of a pattern. In order to quantify, the same form is equalized in two dimensions. And the method of evaluating based on the form is popular. In this study, we conducted experiments for averaging method of the pattern (Measurement Based Contouring) as two-dimensional mask and silicon evaluation technique. That is, observation of the identical position of a mask and a silicon was considered. The result proved its detection accuracy and reliability of variability on two-dimensional pattern (mask and silicon) and is adaptable to following fields of mask quality management. •Discrimination of nuisance defects for fine pattern. •Determination of two-dimensional variability of pattern. •Verification of the performance of the pattern of various kinds of Hotspots. In this report, we introduce the experimental results and the application. We expect that the mask measurement and the shape control on mask production will make a huge contribution to mask yield-enhancement and that the DFM solution for mask quality control process will become much more important technology than ever. It is very important to observe the form of the same location of Design, Mask, and Silicon in such a viewpoint. And we report it about algorithm of the image composition in Large Field.

We report inspection results of early 22-nm logic reticles designed with both conventional and computational lithography methods. Inspection is performed using a state-of-the-art 193-nm reticle inspection system in the reticleplane inspection mode (RPI) where both rule-based sensitivity control (RSC) and a newer modelbased sensitivity control (MSC) method are tested. The evaluation includes defect detection performance using several special test reticles designed with both conventional and computational lithography methods; the reticles contain a variety of programmed critical defects which are measured based on wafer print impact. Also included are inspection results from several full-field product reticles designed with both conventional and computational lithography methods to determine if low nuisance-defect counts can be achieved. These early reticles are largely single-die and all inspections are performed in the die-to-database inspection mode only.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns under mask inspection optical conditions continues to diminish. Furthermore, as mask complexity and MEEF has also increased, it requires detecting even smaller defects in the already narrower pitch mask patterns. This leaves the mask inspection engineer with the option to either purchase a higher resolution mask inspection tool or increase the detector sensitivity on the existing inspection system or maybe even both. In order to meet defect sensitivity requirements in critical features of sub-32nm node designs, increasing sensitivity typically results in increased nuisance (i.e., small sub-specification) defect detection by 5-20X defects making post-inspection defect review non-manufacturable. As a solution for automatically dispositioning the increased number of nuisance and real defects detected at higher inspection sensitivity, Luminescent has successfully extended Inverse Lithography Technology (ILT) and its patented level-set methods to reconstruct the defective mask from its inspection image, and then perform simulated AIMS dispositioning on the reconstructed mask. In this technique, named Lithographic Plane Review (LPR), inspection transmitted and reflected light images of the test (i.e. defect) and reference (i.e., corresponding defect-free) regions are provided to the "inversion" engine which then computes the corresponding test and reference mask patterns. An essential input to this engine is a well calibrated model incorporating inspection tool optics, mask processing and 3D effects, and also the subsequent AIMS tool optics to be able to then simulate the aerial image impact of the defects. This flow is equivalent to doing an actual AIMS tool measurement of every defect detected during mask inspection, while at the same time maintaining inspection at high enough resolution. What makes this product usable in mask volume production is the high degree of accuracy of mask defect reconstruction, predicting actual AIMS measurements to within ±4% CD error for > 95% of defects while not missing any OOS (out-of-specification) defect and maintaining high simulation throughput of ≥250 defects/min on Luminescent's distributed computing platform. This technique enables inspection recipes to be setup based on the sensitivity required to detect small but lithographically-significant defects, even if in the process a large number of nuisance defects are detected. LPR is being implemented as an integral part of defect classification for high-volume sub-32nm technology nodes and higher. Furthermore, this technique will be essential to the lithographic disposition of defects detected on EUV masks inspected under non-actinic conditions.

At the most advanced technology nodes, such as 32nm, 22nm, and beyond, aggressive OPC and Sub-Resolution Assist Features (SRAFs) on the mask are essential for accurate on-wafer imaging; mask patterns generated by Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO) may also be necessary for production. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. Computational Lithography and Inspection (CLI) have broad applications in mask inspection, metrology, review, and repair, and provide additional information to assist the operator in making accurate and efficient decisions on defect disposition. In this paper these applications of CLI in mask inspection, off-line review, metrology, and repair are presented and discussed.

Shrinking structures, advanced optical proximity correction (OPC) and complex measurement strategies continually challenge critical dimension (CD) metrology tools and recipe creation processes. One important quality ensuring task is the control of measurement outlier behavior. Outliers could trigger false positive alarm for specification violations impacting cycle time or potentially yield. Constant high level of outliers not only deteriorates cycle time but also puts unnecessary stress on tool operators leading eventually to human errors. At tool level the sources of outliers are natural variations (e.g. beam current etc.), drifts, contrast conditions, focus determination or pattern recognition issues, etc. Some of these can result from suboptimal or even wrong recipe settings, like focus position or measurement box size. Such outliers, created by an automatic recipe creation process faced with more complicated structures, would manifest itself rather as systematic variation of measurements than the one caused by 'pure' tool variation. I analyzed several statistical methods to detect outliers. These range from classical outlier tests for extrema, robust metrics like interquartile range (IQR) to methods evaluating the distribution of different populations of measurement sites, like the Cochran test. The latter suits especially the detection of systematic effects. The next level of outlier detection entwines additional information about the mask and the manufacturing process with the measurement results. The methods were reviewed for measured variations assumed to be normally distributed with zero mean but also for the presence of a statistically significant spatial process signature. I arrive at the conclusion that intelligent outlier detection can influence the efficiency and cycle time of CD metrology greatly. In combination with process information like target, typical platform variation and signature, one can tailor the detection to the needs of the photomask at hand. By monitoring the outlier behavior carefully, weaknesses of the automatic recipe creation process can be spotted.

In this study, the method to achieve the precise CD MTT (critical dimension mean to target) correction in manufacturing attenuated PSM (phase-shift mask) is investigated. There has been a growing demand for more precise Mask CD MTT control in recent years. The CD correction method has been developed and applied to meet the tighter CD MTT specification [1]. However, the efficiency of the CD correction is greatly affected by the repeatability of the CD measurement. The factors, which can have an influence on the CD measurement, are the fluctuations of the pattern profile and the electron current of the SEM. The conventional CD MTT correction method is basically to correct MoSi CD MTT by applying the additional dry etch for MoSi based on Cr CD value. Therefore, the repeatability of the Cr CD MTT is the crucial point for the accuracy of the final CD MTT correction. Although the Cr CD MTT is the crucial factor for the successful CD MTT correction, it has the fluctuation due to the Cr pattern profile. If the Cr pattern profile has low patterned angle after MoSi etch process, it can cause the focusing error in the CD measurement using CD SEM. Therefore, a method to improve the reliability of the Cr CD MTT should be developed. The IS and the normalized Delta CD concepts are adopted to obtain more reliable Cr CD MTT. The IS refer the variation of the Cr CD MTT according to the difference in CD values with CD measuring thresholds. The normalized Delta CD is obtained from the correlation of IS and Delta CD. Finally, the normalized Delta CD is applied to correct the MoSi CD MTT by dry etch process. The reduction of the Cr CD MTT fluctuation range is achieved by using the new CD correlation process including IS and the normalized Delta CD. Consequently, the final MoSi CD MTT is improved 60% of range by using the new CD correlation process.

Currently all LMS IPRO pattern placement metrology tools are calibrated using a 1D length standard provided by a national standards institute (e.g. NIST or PTB), however there are no 2-D standards available with an uncertainty matching the requirements of mask manufacturing for the 22nm HP node and beyond. Therefore, the 2D stage coordinate system of the LMS IPRO systems is calibrated using KLA Tencor's proprietary combined correction technique. With introduction of the LMS IPRO4 into high volume mask production at the AMTC, AMTC and KLA-Tencor MIE have demonstrated the capability to match IPRO3 and IPRO4 grids within 1.2 nm uncertainty [1]. Using the Golden Tool approach, we achieved a significant improvement in pattern placement measurement capability of previous generation measurement tools of up to 30%. This in turn leads to improved pattern placement metrology fleet capability and extended useful lifetime of capital equipment. The use of multiple high end registration measurement tools enables the creation of a 2D coordinate system standard, which could be used for improved fleet matching and would help improve the capability of older generation pattern placement metrology tools by matching to this standard. Within this paper Golden Tool and Round Robin worldwide fleet matching approaches are compared and discussed.

Critical Dimension uniformity (CDU) is one of the most critical parameters for the characterization of photomasks. Lately it has been shown that advanced CD (critical dimension) SEM tools and mask processes can distinguish the random short-range CD variation from the global CD signature, which is driven by process and design characteristics. Current electron beam writers can utilize this global CD signature information and correct the CDU of photomasks accordingly. Therefore a detailed knowledge of the signature will benefit strongly photomask CDU. Electron beam writer based signature compensation relies primarily on CD signatures derived from CD SEMs. Here higher spatial resolutions of the signature are achieved only by high cycle times at metrology. The trade off between cycle time and resolution leads to a CD resolution somewhere around one cm. Even then the photomask will have to stay a substantially percentage of the total cycle time at a non-value added process step. In this paper we argue that the solution for this dilemma can be found at a completely different process area - at inspection. We present data showing that the novel CD map feature of the NPI inspection tools enables CD maps in unparalleled resolution in the mm region. This far exceeds CD SEMs by a factor of 100. Also utilization of a tuneable spectrum of different features are not limited to selected CD measurement sites. The CD map is generated in parallel to the traditional defect inspection and works for pre- and post pellicle inspections equally well. To evaluate the method we used a single die layout of a current logic design and referenced all data only to database. Nevertheless, the data presented will demonstrate the excellent repeatability of the CD map measurement and the good matching to CD SEM measurements.

Double Patterning Lithography (DPL) for next generation wafer exposure is placing greater demands on the requirements for pattern placement accuracy on photomasks. Recent studies have shown that pattern placement accuracy can be one of the largest components of systematic wafer overlay error. Since LELE or LFLE DPL technologies tighten intra-field-wafer overlay requirements by as much as a factor of 2 (to 2 - 3nm for critical layers), minimizing all sources of systematic overlay error has become critical. In addition to its impact on overlay performance, any significant pattern displacement between the two exposures in a double patterning scheme will have a significant impact on CD uniformity, another major area of concern for next-generation devices. In the past, mask registration has been referenced to design data using relatively large, specially designed targets. However, as shown in many previous papers [2], the true registration error of a next-generation reticle cannot be sufficiently described by using today's sampling plans. In order to address this issue, it is mandatory to have In-Die registration capability for next generation reticle registration. On this path to In-Die pattern placement metrology many challenges have to be solved. One is the data preparation necessary to get the targets placed and marked within the design, preparing for the later metrology step. This paper demonstrates an automated way of performing In-Die registration metrology. This new approach allows more flexible and higher density metrology so that pattern placement error is sufficiently well characterized.

The increased industry requirements for pattern registration tools in terms of resolution and in-die measurement capability lead to the development of the new photomask registration and overlay metrology system PROVE^TM at Carl Zeiss. Performance measures of the tool are actually driven by double exposure/ double patterning approaches which will help to extend the 193nm lithography platforms while keeping the semiconductor industry conform to ITRS roadmap requirements. To achieve the challenging specifications, PROVE^TM features beside a highly stable hardware system new image analysis methods which are designed to meet the requirements both for standard markers as for in-die features. For that, in addition to conventional threshold-based image analysis, PROVE^TM will provide a more accurate correlation analysis to measure pattern placement errors with respect to design images. This correlation is based on an aerial image simulation of the corresponding reference design patterns. Since reproducibility and accuracy specifications at camera level are far below the pixel size of the CCD, sophisticated algorithms have to be used to avoid super-pixelling effects. It will be shown that super-pixelling effects of discretized design images will either lead to placement errors or to unrealistic small design pixel dimensions, connected with huge image sizes. The solution is an alias-free forward transform that performs the discretization in Fourier space and will not disturb the pattern placement. It is indicated by simulations that this allows the detection of an arbitrary sub-pixel placement error with high accuracy. Furthermore, it is demonstrated that correlation methods reduce the impact of camera noise compared to threshold methods, in particular for small in-die features as contact holes.

Reticle critical dimension (CD) errors must be minimized in order for photomask manufacturers to meet tight CD uniformity (CDU) requirements. Determining the source of reticle CD errors and reducing or eliminating their CDU contributions are some of the most relevant tasks facing process engineers. The AMTC has applied principal component analysis (PCA) to reticle resist CD measurements in order to examine variations in the data. PCA provided the major components of resist CD variation which were rescaled into reticle CD signatures. The dominant component of CD signature variation is very similar in shape and magnitude between two different chemically amplified resist (CAR) processes, most likely indicating the variation source is a common process or tool. CD variational signatures from PCA were used as a basis for launching investigations into potential reticle CD error sources. PCA was further applied to resist CD measurements from alternate process tools to assist efforts in judging the effectiveness of resist CD signature matching.

Wafer overlay requirement for the 32nm DRAM HP node volume production is targeted at 6.4nm (single exposure) in 2013. Consequently, this is placing a significantly tighter demand on the pattern placement accuracy on photomasks at or below 4nm (3sigma). In case Double Patterning Lithography (DPL) becomes the manufacturing technique for 32nm and 22nm node devices, the pattern placement specification of dependent layers is less than 3nm, according to the ITRS roadmap. In addition to photomask lithography pattern placement instability, the distortion influence of the pellicle on plate bending is also an error contributor especially when the pellicle distortions are not repeatable substrate to substrate. The combination of increased demand for greater accuracy and the influence of pellicle distortions are key factors in the need for high resolution through pellicle in-die measurements using actual device features. A new registration metrology tool dedicated for the 32nm HP node and beyond is under final development. Actual status and performance data of the beta evaluation system is provided to verify registration metrology capability for DPL reticle manufacturing to characterize the reticle contribution to total wafer overlay within the required tolerances.

As the magnetic storage industry roadmap calls for aggressive terabit/in² densities over the next few years, the shift from the current planar media to patterned media; grooved surfaces (discrete track media / DTM) and/or individually defined magnetic dots (bit patterned media / BPM), will be necessary. Both types of patterned media require lithography to produce the pattern on the disk and the most promising lithography candidate today is nano-imprint lithography (NIL). During the imprinting process a thin, round, transparent template made of quartz is functioned as a mold to inversely transfer the features from its surface to the patterning medium on the disks by direct contact. One issue with this technique is the high probability of defects due to repeated contact of the template with the resist before, during, and after UV radiation. Defect management through template cleaning, inspection and defect characterization is critical to preserve integrity of the process. In this paper, advanced acid-free cleaning combined with MegaSonic treatment for defect elimination is investigated for effectiveness on discrete track recording (DTR) and BPM patterned templates. For the experiments, templates containing 250KTPI (100nm track pitch) full surface DTR pattern, 450 KTPI (56nm track pitch) with narrow band DTR pattern, and 250Gdpsi (50nm track pitch) with narrow band BPM pattern are used. The effect of MegaSonic cleaning on the pattern integrity of fragile features is studied. General characterization of defect attributes is made feasible through a series of imprinting and template cleaning cycles focused on resist residues and contaminant removal. Imprinted disks are analyzed using Candela disk inspection and SEM imaging of the pattern. Template cleaning is performed using HamaTech MaskTrack TeraPure automated template cleaning system.

Bit patterned media (BPM) is one of the promising technologies for ultra-high density storage in future hard disk drives. However, there are many challenges in fabricating BPM. In particular, applications with area density much greater than 1 Tbit/in² require magnetic bits to be at sub-10 nm dimensions. Etching at these scales is difficult to achieve with conventional ion milling techniques. Instead, reactive ion etching (RIE) techniques must be developed to meet the challenge. In this work, research is presented on the development of a methanol based RIE scheme for fabricating BPM at ultra-high area densities. The paper will discuss the ability of methanol RIE to etch magnetic and nonmagnetic films in both the parallel plate and inductively coupled plasma (ICP) RIE configurations, as well as the advantages of both configurations over Ar ion milling, including enhanced selectivity, minimal redeposition, and less etch induced damage or erosion. We demonstrate the ability to etch sub-20 nm features in commercially available CoCrPt based perpendicular recording media and NiFe with selectivity greater than 10:1 relative to mask materials, such as Ta, TaN_x, Ti, and SiN_x. These results, the promises of such a technique, and the feasibility of sub-10 nm scale etching are discussed in detail.

A new photomask technology with the Advanced Binary Film (ABF) by HOYA has been established. The film of relatively low thickness is expected to show the best lithography performance. The simple film structure of thin film of chemically amplified resist, as a mask layer for etching, on the thin ABF film enables us to obtain sub-50nm small features in a photomask. The thinness of the film also helps to avoid pattern collapse in cleaning steps. The photomask with ABF expecting the best currently available lithography performance shows the best achievable durability for use in ArF lithography process steps and the best attainable feasibility in the fabrication process steps for leading edge photomasks.

High PRE (Particle removal efficiency) and damage free cleaning became main cleaning challenges over haze prevention in photomask industry, nowadays. SRAF (Sub-resolution assist feature) size became small down below 0.1um as pattern size become small. Acoustic frequency and power is the main parameter to increase PRE in photomask cleaning. 1 MHz of acoustic frequency was good enough to remove particles and soft defects until recently. But it has shown pattern damages for SB (Scattering bar) size of below 0.1um unfortunately. In this paper, we optimized photomask cleaning process to achieve high PRE and low pattern damage. Its haze prevention capability and cycle cleaning durability was verified with in-house-built HATB and AIMS, respectively.

There is a dire need for the removal of all printable defects on lithography masks. As the technology node advances, smaller particles need to be efficiently removed from smaller features without any damage or adders. CO₂ cryogenic aerosol cleaning is a dry, residue-free and chemically inert technique that doesn't suffer from disadvantages of conventional wet cleaning methods such as transmission/reflectivity loss, phase change, CD change, haze/progressive defects, and/or limitation on number of cleaning cycles. Ultra-pure liquid CO₂ when dispensed through an optimally designed nozzle results in CO₂ clusters that impart the required momentum for defect removal. Historically nanomachining debris removal has been established with this technique. Several improvements have been incorporated for cleaning of advanced node masks, which has enabled Full Mask Final Clean, a new capability that has been successfully demonstrated. The properties of the CO₂ clusters can be captured utilizing the Phase Doppler Anemometry (PDA) and effect of varying process and design parameters can be verified. New nozzles have been designed to widen the cleaning process window for advanced node optical masks, without any damage to the weak primary features and/or sub-resolution assist features (SRAFs). This capability has been experimentally proven for high aspect ratio SRAFs e.g. 2.79 (52nm wide by 145 nm tall) as well as SRAFs 45nm wide by 73 nm tall. In this paper, 100% removal of soft defects that would have printed on advanced node masks is demonstrated. No printed defects larger than 50nm is observed after the CO₂ cleaning. Stability of the cleaning and handling mechanisms has been demonstrated over the last 4.5 months in a production environment. The CO₂ cleaning technique is expected to be effective for more advanced masks and Extreme Ultra-Violet (EUV) lithography.

The adaption of EUVL requires the development of new cleaning method for the removal of new contaminant without surface damage. One of the harsh contaminants is the carbon contamination generated during EUV exposure. This highly dense organic contaminant is hardly removed by conventional SPM solution on Ru capped Mo/Si multilayer. The hopeful candidate for this removal is ozonated water (DIO₃), which is not only well-known strong oxidizer but also environmentally friendly solution. However, this solution might cause some damage to the Ru capping layer mostly depending on its concentration. For these reasons, DIO₃ cleaning solutions, which are generated with various additive gases, were characterized to understand the correlation between DIO₃ concentration and damages on 2.5 nm thick ruthenium (Ru) surface. An optimized DIO₃ generation method and cleaning condition were developed with reduced surface damage. These phenomena were explained by electrochemical reaction.

In electron beam writing on EUV mask, it has been reported that CD linearity does not show simple signatures as observed with conventional COG (Cr on Glass) masks because they are caused by scattered electrons form EUV mask itself which comprises stacked heavy metals and thick multi-layers. To resolve this issue, Mask Process Correction (MPC) will be ideally applicable. Every pattern is reshaped in MPC. Therefore, the number of shots would not increase and writing time will be kept within reasonable range. In this paper, MPC is extended to modeling for correction of CD linearity errors on EUV mask. And its effectiveness is verified with simulations and experiments through actual writing test.

As the design rule of wafer has been shrinking, the patterns on the mask also need to be getting smaller and even smaller for some sub-resolution assist features, which makes mask inspection process need a high resolution (HR) inspection systems. For this HR mask inspection, most mask inspector makers adopt a TDI(Time Delay & Integration) sensor to enhance acquired image quality with the acceptable scan speed, thus, to minimize the inspection cost. However, even TDI sensor may not get a sufficient gray level of pattern image for the most advanced mask patterns. Furthermore, it might generate some false defects depending on the pattern shape and scan direction (in combination with pattern direction). We manufactured two programmed defect masks (PDM); one is a ArF EPSM and another is a EUV mask. By inspecting these masks with perpendicular scan directions, respectively, we evaluated the correlation between scan direction and defect size/shape experimentally. We found that the inspection with the parallel direction to pattern direction can increase the inspectability for the patterns and the defect sensitivity since this helps to enhance signal to noise ratio from the TDI sensor. Our analysis can increase sensitivity of TDI sensor effectively without any additional hardware modification.

Extreme Ultra Violet Lithography (EUVL) is a major patterning solution candidate being considered for the ITRS (International Technology Roadmap for Semiconductors) advanced technology nodes commencing with the 22nm Half Pitch (HP) nodes. Achieving defect free EUVL masks is a critical issue in the wafer manufacturing process and thus the importance for mask inspection technology to be ready to support pilot line development. EUV mask inspection presents additional challenges with smaller line width, multilayer defects and no pellicle to protect the mask. In addition, Line Edge Roughness on the mask can limit the detection sensitivity. Configurable inspection illumination conditions were considered to enhance the contrast of the mask image and improve the detection sensitivity. Here we present experimental results of evaluating the defects detecting capability on several EUVL masks of different technology nodes. EUVL mask inspections were done using Material's Aera3^TM DUV (193nm) reflected illumination optical inspection system employing configurable inspection illumination conditions and magnifications.

Most leading-edge IC fabs continue to use direct reticle inspection for "early warning" detection of haze defects before they print on wafers. This inspection strategy enables fabs to cost-effectively maintain the highest product yields possible. As design rules advance from 45/40 nm nodes to 32/28 nm, mask pattern sizes continue to shrink while increasing in pattern density. More layers are exposed on 193nm immersion scanners, and as a result, reticle requal inspection requirements become more challenging in order to meet sensitivity and inspectibility performance. In this paper, we examine some of the inspection challenges 32/28 nm logic mask designs present. New reticle requal requirements created by aggressive SRAF and higher MEEF mask designs used at these nodes are first examined. A new and improved inspection technology to support requal requirements at this level is introduced and tested. These data are analyzed to evaluate the overall inspection capability and sensitivity of this new product designed to meet 32/28 nm foundry reticle requal needs for high-volume production in IC fabs.

EUV lithography is expected to be not only for hp 2Xnm node device production method but also for hp 1X nm node. We have already developed the mask inspection system using 199nm wavelength with simultaneous transmitted and reflected illumination optics, which utilize p-polarized and s-polarized illumination for high defect detection sensitivity, and we developed a new image contrast enhancement method which changes the digitizing rate of imaging sensor depending on the signal level. Also, we evaluate the mask structure which improve the image contrast and defect detection sensitivity. EUVL-mask has different configuration from transmitted type optical-mask. A captured image simulator has been developed to study the polarized illumination performance theoretically of our inspection system. Preferable mask structure for defect detection and possibility of miss defect detection are considered.

Data volume is getting larger every day in Mask Data Preparation (MDP). In the meantime, faster data handling is always required. MDP flow typically introduces Distributed Processing (DP) system to realize the demand because using hundreds of CPU is a reasonable solution. However, even if the number of CPU were increased, the throughput might be saturated because hard disk I/O and network speeds could be bottlenecks. So, MDP needs to invest a lot of money to not only hundreds of CPU but also storage and a network device which make the throughput faster. NCS would like to introduce new distributed processing system which is called "NDE". NDE could be a distributed disk system which makes the throughput faster without investing a lot of money because it is designed to use multiple conventional hard drives appropriately over network. NCS studies I/O performance with OASIS® data format on NDE which contributes to realize the high throughput in this paper.

The Proximity Effect is a critical problem in EB Lithography which is used in Photomask writing. Proximity Effect means that an electron shot by gun scatters by collided with resist molecule or substrate atom causes CD variation depending on pattern density [1]. Scattering by collision with resist molecule is called as "forward scattering", that affects in dozens of nanometer range, and with substrate atom is called as "backward scattering, that affects approximately 10 micrometer in 50keV acceleration voltage respectively. In conventional Proximity Effect Correction (PEC) for mask writing, we don't need to think forward scattering effect. However we should think about forward scattering because of smaller feature size. We have proposed a PEC software product named "PATACON PC-Cluster"[2], which can concern forward scattering and calculate optimum dose modulation. In this communication, we explain the PEC processing throughput when the that takes forward scattering into account. The key technique is to use different processing field size for forward scattering calculation. Additionally, the possibility is shown that effective PEC may be available by connecting forward scattering and backward scattering.

In the process of optical proximity correction, layout edge or fragment is migrating to proper position in order to minimize edge placement error (EPE). During this fragment migration, several factors other than EPE can be also taken into account as a part of cost function for optimal fragment displacement. Several factors are devised in favor of OPC stability, which can accommodate room for high mask error enhancement factor (MEEF), lack of process window, catastrophic pattern failure such as pinch/bridge and improper fragmentation. As technology node becomes finer, there happens conflict between OPC accuracy and stability. Especially for metal layers, OPC has focused on the stability by loss of accurate OPC results. On this purpose, several techniques have been introduced, which are target smoothing, process window aware OPC, model-based retargeting and adaptive OPC. By utilizing those techniques, OPC enables more stabilized patterning, instead of realizing design target exactly on wafer. Inevitably, post-OPC layouts become more complicated because those techniques invoke additional edge, or fragments prior to correction or during OPC iteration. As a result, jogs of post OPC layer can be dramatically increased, which results in huge number of shot count after data fracturing. In other words, there is trade-off relationship between data complexity and various methods for OPC stability. In this paper, those relationships have been investigated with respect to several technology nodes. The mask shot count reduction is achieved by reducing the number of jogs with which EPE difference are within pre-specified value. The effect of jog smoothing on OPC output - in view of OPC performance and mask data preparation - was studied quantitatively for respective technology nodes.

Thin film hardmasks with 10nm or less are used in double patterning techniques to generate fine patterns for 32nm-node and beyond. Using a conventional Mask CDSEM for ultra accurate measurement of patterns on these thin film hardmasks is difficult due to weakness of the edge profiles generated by a scanning electron beam. Additionally, the tones of a SEM image can be reversed due to a charging phenomenon, which causes false recognition of lines and spaces. This paper addresses ultra accurate measurement of thin film hardmasks using a new measurement algorithm that is applied to profiles obtained from multiple detectors.

The allowable wafer Critical Dimension Uniformity (CDU) budget of the 2x node poses stringent requirements on mask induced errors at wafer level. The total CDU budget of 2 nm which is partially consumed by across wafer and field process and imaging variations, leaves little room for additional mask errors to still comply to the overall CDU budget. The trend of higher mask error enhancement factor (MEEF) for advanced technology nodes aggravates this situation further. Traditionally, the assessment of these variations is based on separate critical dimension and phase/transmission measurements. Metrology measurement tools are typically based on different techniques to independently measure each source of non-uniformity and produce the required uniformity maps. Each technique concentrates on a single physical property (e.g., line-width, phase, transmission, etc.) and requires special calibration for the required accuracy, precision and its transformation from mask to the wafer nanometer domain. An alternative to all these separate measurements is proposed by using the IntenCD^TM application based on the aerial image of the mask. This alternative approach provides a map of mask-induced, printed CD variations across the photomask. In this paper, a study is presented to estimate mask-induced printed CDU at wafer level from the aerial image and results are compared to mask- and phase-CD measurements. The work shows that a single aerial IntenCD map can replace the two sets of data based on mask-CD and mask-phase measurements and allows for prediction of the mask contribution to overall printed CDU.

With the continued shrinks in production structures to 38 nm and below for hyper-NA lithographic tools, there is an opportunity to further optimize these reticle alignment structures to reduce overlay numbers and improve yield. This opportunity is especially relevant for Dual Patterning applications where pattern shifts under different imaging conditions become critical. In this paper, we will present a proposal for improved reticle alignment structures to minimize the sensitivities for lens aberrations and thereby to minimize the contribution of reticle alignment to pattern shifts. Some alternatives will also be addressed. Full compatibility of the proposed alignment structures with older machines as well as continued compatibility of older reticles on the new lithographic tools will be discussed.

Duplicated templates from a patterned silicon master were studied. The pattern was fabricated on a silicon wafer by rotary electron beam (EB) writer and reactive ion etching (RIE). 2.5-inch full surface discrete track media (DTM) templates of TP70nm supporting skewed servo patterns and discrete tracks were fabricated. The pattern on the silicon master was successfully transferred to quartz templates by UV nanoimprint lithography (NIL) and RIE using a specially prepared UV-NIL resist. TP60nm pattern fabrication was also accomplished by this same hard mask-less method. Servo pattern printing (SPP) was used to investigate the repeatable run-out (RRO) of servo patterns. Nickel molds and quartz templates were duplicated from the same silicon master by their respective processes and their RROs compared. It was found that the duplication process (quartz or nickel) influenced the RRO profile and that the quartz NIL process did not significantly degrade RRO.

With the design rule shrinks rapidly, full chip robust Optical Proximity Correction (OPC) will definitely need longer time due to the increasing pattern density. Furthermore, to achieve a perfect OPC control recipe becomes more difficult. For, the critical dimension of the design features is deeply sub exposure wavelength, and there is only limited room for the OPC correction. Usually very complicated scripts need to be developed to handle the shrinking designs, which can be infinitely complicated. So when you are defining a parameter value in your OPC control recipe, one problem is how to find the optimum setting. And usually there are a bund of parameters in the script, some of which may have impact on others performance. We here demonstrate an approach of how to find the optimized setting of the critical parameters with cost function. And this will be helpful to reduce the difficulty for OPC recipe development.

One of the major problems in the RET flow is OPC recipe creation. The existence of numerous parameters to tune and the interdependence between them complicates the process of recipe optimization and makes it very tedious. There is usually no standard methodology to choose the initial values for the recipe settings or to determine stable regions of operation. In fact, parameters are usually optimized independently or chosen to resolve a certain issue for a specific design without quantifying its effect on the quality of the recipe or how it might affect other designs. Another problem arises when a quick fix is needed for an old recipe to build new design masks, and this causes the stacking of many customization statements in the OPC recipe, which in turns increases its complexity. Consequently, the experience of the developer is highly required to build a good as well as a stable recipe. In this context, simulated annealing is proposed to optimize OPC recipes. It will be shown how many parameters can be optimized simultaneously and how we can get insight about the stability of the recipe.

Double patterning (DP) is a necessity for at and below 32nm half pitch production. The two top contending DP technologies are litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP). While both LELE and SADP are actively researched and optimized on the process side [1] [2] [3] [4], CAD support for them has been very different. When cut candidates can be explicitly specified, the problem of LELE mask assignment transforms into the familiar 2-colorability problem and benefits from the extensive research ranging from what originally was conducted for alt-PSM lithography [5], to more recently proposed new techniques for LELE [6], and proof of the inherent computational limitation imposed by hierarchy [7]. CAD support for SADP, on the other hand, is almost non-existent. Such lack of CAD support for SADP is not coincidental. For a layout, LELE solutions tend to look similar while SADP solutions can be vastly different in style. Due to the flexibility offered by trim mask, SADP inherently has a much larger solution space than LELE. In this paper, we take the first step in investigating the CAD implications of the positive line-by-fill SADP process by proving that the problem of SADP manufacturability is NP-complete.

A fast model-based technique for SRAF placements is proposed in this paper. This technique first constructed an image pixel map with values presenting the sensitivity of improving process window on the desired pattern. The sensitivity value was derived based on contrast improvement with a defocus model. Then high value pixels were selected and constructed to form SRAF with MRC regulations. This technique does not require iterations to produce SRAF and achieves very fast runtime with simple mask shapes, thus can be used in full-chip productions. We called this technique the SRAF guidance map, SGM

The steady march of Moore's law demands ever smaller feature sizes to be printed and Optical Proximity Correction to correct to ever tighter dimensional tolerances. Recently pitch doubling techniques has relieved the pressure on CD reduction, which instead of being achieved lithographically are reduced by subsequent etching or chemical interaction with spin-on layers. CD tolerance reductions, however, still need to match the overall design rule shrinkage. The move to immersion lithography, where effective Numerical Apertures now reach 1.35, has been accompanied by a significantly reduction in depth of focus, especially on isolated contacts. To remedy this, RET techniques such as assist feature placement, have been implemented. Certain local placements of assist features and neighboring contacts are observed to result in highly elliptical contacts being printed. In some layouts small changes in the aspect ratio of the contact on the mask leads to strong changes in the aspect ratio of the printed contact, whereas in other layouts the response is very weak. This effect can be described as an aspect ratio MEEF. The latter type of contact can pose a significant challenge to the OPC recipe which is driven by the need to place the printed contour within a small range of distance from target points placed on the midpoint of edges of a nominally square contact. The OPC challenge naturally will be compounded when the target layout is rectangular in the opposite sense to the natural elliptical shape of the printed contact. Approaches to solving this can vary from intervening at the assist feature placement stage, at the possible loss of depth of focus, to accepting a certain degree of ellipticity in the final contour and making the OPC recipe concentrate on minimizing any residual errors. This paper investigates which contact layouts are most challenging, discusses the compromises associated with achieving the correction target and results are shown from a few different approaches to resolving these issues.

To enable Inverse Lithography Technology (ILT) for production as one of the leading candidates for low-k₁ lithography at 32nm and below, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications[1,2], it has been shown that the Inverse Synthesizer (IS^TM) produces ILT full chip mask of contact layer with comparable mask write time with conventional OPC while maintaining the significant litho gains of ILT mask. To fully integrate ILT masks into production for all layers including line and space layers such as poly layer, a number of areas were investigated to further reduce ILT mask complexity and total e-beam shot count. These areas include flexible controls of SRAF placements with respect to local feature sizes, improved Manhattan algorithm, topology based variable Manhattan segmentation, jog alignment and mask data fracture optimization. The impact of these approaches on e-beam shot count and lithography performance of ILT masks is presented in the paper.

Implant level photolithography processes are becoming more challenging each node due to everdecreasing CD and resist edge placement requirements, and the technical challenge is exacerbated by the business need to develop and maintain low-cost processes. Optical Proximity Correction (OPC) using models created based on data from plain silicon substrate is not able to accommodate the various real device/design scenarios due to substrate pattern effects. In this paper, we show our systematic study on substrate effect (RX/STI) on implant level lithography CD printing. We also explain the CD variation mechanism and validate by simulation using well calibrated physical resist model. Based on the results, we propose an approach to generate substrate-aware OPC rules to correct for such substrate effects.

In modern photolithography, ever smaller critical dimension (CD) budgets require tighter control over the entire process, demanding more accurate practice of optical proximity correction (OPC). In last decade, the model based OPC (MBOPC) has outpaced the rule based OPC (RBOPC) and become widely adopted in semiconductor industry. During the MBOPC process, the physical models are called to compute the signal values at the evaluation points and the design patterns are perturbed such that the final model contours are as close to the targets as possible. It has been demonstrated that in addition to simulating the optics and resist effects, the physical models must accommodate the pattern distortion due to etch process as well. While the etch process may be lumped with optics and resist processes into one model for the 65nm and above nodes, it can no longer be treated as small perturbations on photolithographic effects for more advanced nodes and it is highly desired to build a physics-based etch model formulations that differ from the conventional convolution-based process models used to simulate the optical and resist effect. Our previous studies proposed a novel non-linear etch modeling object in combination with conventional convolution kernels, which simulates the non-optics and non-resist proximity effect successfully. This study examines further the non-linear etch modeling method by checking the different behaviors of N and p doped layers which physically have different etching rates and should be represented differently in etch modeling. The experimental results indicate that the fitting accuracy is significantly improved when the data points are split into N and P groups and calibrated separately. The N and P layer etch models are used in staged MBOPCs and the results are compared with single-layer model as well.

A new method for simultaneous Source-Mask Optimization (SMO) is presented. In order to produce optimum imaging fidelity with respect to exposure lattitude, depth of focus (DoF) and mask error enhancement factor (MEEF) the presented method aims to leverage both, the available degrees of freedom of a pixelated source and those available for the mask layout. The approach described in this paper is designed as to work with dissected mask polygons. The dissection of the mask patterns is to be performed in advance (before SMO) with the Synopsys Proteus OPC engine, providing the available degrees of freedom for mask pattern optimization. This is similar to mask optimization done for optical proximity correction (OPC). Additionally, however, the illumination source will be simultaneously optimized. The SMO approach borrows many of the performance enhancement methods of OPC software for mask correction, but is especially designed as to simultaneously optimize a pixelated source shape as nowadays available in production environments. Designed as a numerical optimization approach the method is able to assess in acceptable times several hundreds of thousands source-mask combinations for small, critical layout snippets. This allows a global optimization scheme to be applied to the SMO problem which is expected to better explore the optimization space and thus to yield an improved solution quality compared to local optimizations methods. The method is applied to an example system for investigating the impact of source constraints on the SMO results. Also, it is investigated how well possibly conflicting goals of low MEEF and large DoF can be balanced.

In double patterning technology (DPT), two adjacent features must be assigned opposite colors, corresponding to different exposures if their pitch is less than a predefined minimum coloring pitch. However, certain design orientations for which pattern features separated by more than the minimum coloring pitch cannot be imaged with either of the two exposures. In such cases, there are no aerial images formed because in these directions there are no constructive interferences between diffractive orders in the pupil plane. The 22nm and 16nm nodes require the use of pixelized sources that will be generated using SMO (source mask co-optimization). Such pixelized sources while helpful in improving the contrast for selected configurations can lead to degraded contrast for configurations which have not been set during the SMO process. Therefore, we analyze the diffractive orders interactions in the pupil plane in order to detect limited orientations in the design and thus propose a decomposition to overcome the problem.

One of the challenges of EUVL is to bring EUV mask blank defect levels to zero. With uncertainty on when defect free masks may be routinely available, we explore a possibility for effectively using defective EUV mask blanks in production with a defect avoidance strategy. The key idea is to position the pattern/layout on the blank where the defects do not impact the final wafer image. Assuming that layout designs contain some non-critical areas in which defects can be safely positioned, it may be possible to align these regions with a given, small set of defect positions mapped from an imperfect mask blank. Using a few representative assortment of current-node, full-chip layout patterns we run multiple trials against real blank defect maps with various defect counts successfully. Our goal is to assess the probabilities that defect avoidance will work as a function of mask blank defect count, and by lithography layer.

This paper presents a novel mask corner rounding (MCR) modeling approach based on Synopsys' Integrated Mask and Optics (IMO) modeling framework. The point spread functions of single, double, and elliptical Gaussians are applied to the IMO mask kernels to simulate MCR effects. The simulation results on two dimensional patterns indicate that the aerial image intensity variation is proportional to the MCR induced effective area variations for single type corners. The relationship may be reversed when multiple types of corners exist, where the corners close to the maximum intensity region have a greater influence than others. The CD variations due to MCR can be estimated by the effective area variation ratio and the image slope around the threshold. The good fitting results on line-end patterns indicate that the ΔCD is the quadratic function of the Gaussian standard deviations. OPC modeling on 28nm-node contacts shows that MCR has significant impact on model fitting results and process window controls. By considering the real mask geometry effects and allowing in-line calibration of model parameters, the IMO simulation framework significantly improves the OPC model accuracy, and maintains the calibration speed at a good level.