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- Front Matter: Volume 7274
- Invited Session
- Resolution Enhancement
- Source and Mask Optimization
- Spacer-based Processes
- Double Patterning I
- Double Patterning II
- Tools Related Process Control I
- Tools Related Process Control II
- Optical Proximity Corrections I
- Optical Proximity Corrections II
- Optical Proximity Corrections III
- Resolution Enhancement
- Process
- Tools I
- Tools II
- Poster Session: Double Patterning
- Poster Session: High Index Lithography
- Poster Session: Masks
- Poster Session: Optical Proximity Corrections
- Poster Session: Process
- Poster Session: Process Control
- Poster Session: Resolution Enhancement
- Poster Session: Simulation
- Poster Session: Source and Mask Optimization
- Poster Session: Spacer-based Processes
- Poster Session: Tools
Front Matter: Volume 7274
Front Matter: Volume 7274
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This PDF file contains the front matter associated with SPIE
Proceedings Volume 7274, including the Title Page, Copyright
information, Table of Contents, and the Conference Committee listing.
Invited Session
Alternative optical technologies: more than curiosities?
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As optical lithography reaches it physical limits, alternative technologies become interesting. There have been
several such alternatives that are still optical, but have some departure from conventional projection methods. This
papers presents some of these alternative optical technologies, namely the use of surface plasmons and plasmonic
lithography, metamaterials and superlenses, evanescent wave lithography, solid immersion lithography, and stimulated
transmission depletion (StED) lithography. Additionally, the viability of interferometric lithography (IL) is addressed
for application to sub-32nm generations by using an information content metric and comparing results to 193nm
lithography, double patterning, and EUV.
Resolution Enhancement
Overcoming the challenges of 22-nm node patterning through litho-design co-optimization
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Historically, lithographic scaling was driven by both improvements in wavelength and numerical aperture. Recently,
the semiconductor industry completed the transition to 1.35NA immersion lithography. The industry
is now focusing on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh
diffraction. Here, the IBM Alliance demonstrates the extendibility of several double patterning solutions that
enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through
innovative processes. This paper details a set of solutions that have enabled early 22 nm learning through careful
lithography-design optimization.
Improved model predictability by machine data in computational lithography and application to laser bandwidth tuning
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Computational lithography (CL) is becoming more and more of a fundamental enabler of advanced semiconductor
processing technology, and new requirements for CL models are arising from new applications such as model-based
process tuning. In this paper we study the impact of realistic machine parameters that can be incorporated in a modern
CL model, and provide an experimental assessment of model improvements with respect to prediction of scanner tuning
effects. The data demonstrates improved model accuracy and prediction by inclusion of scanner-type specific modeling
capabilities and machine data in the CL model building process. In addition to scanner effects, we study laser bandwidth
tuning effects and the accuracy of corresponding model predictions by comparison against experimental data. The data
demonstrate that the models predict well wafer CD variations resulting from laser BW tuning. We also find that using
realistic spectral density distribution of the laser can provide more accurate results than the commonly assumed modified
Lorentzian line shape.
Contact mask optimization and SRAF design
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Contact hole patterning and especially sub resolution assist feature (SRAF) insertion and optical proximity
correction (OPC) have become an extremely critical element of enabling continued shrink of CMOS
technology. These elements of mask generation are fundamental to the success of technology execution. As
off-axis illumination modes have been introduced to resolve smaller pitches, forbidden pitches emerge that
need to be considered in random logic layouts. Optimized placement of assist features for these pitches is
extremely important for overall process window and tolerance budget considerations. Several techniques
have recently been developed for model based SRAF optimization. These typically focus only on optimizing
the aerial image through focus, but may not include sensitivity to mask error as well. These approaches will
be evaluated and discussed. Total CD uniformity is presented as a metric for evaluation of mask solutions.
This includes the impact of dose and focus, but also masks error in estimating the total CD variation of a
contact patterning process. The SRAF solution with the lowest overall variation is the winner. This
methodology is presented for parametric through pitch features, and logic patterns.
Source and Mask Optimization
A study of source and mask optimization for ArF scanners
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The k1 factor continues to be driven downwards, in order to enable the 32 nm feature generation and beyond. Due to the
extremely small process window that will be available for such demanding imaging challenges, it is necessary not only
for each unit contributing to the imaging system to be driven to its ultimate performance capability, but also that active
techniques that can expand the process window and robustness of the imaging against various kinds of imaging
parameter be implemented. One such technique is a Source & Mask Optimization1 (SMO). In this paper we are going to
study the effect of SMO and discuss its application to ArF exposure tools. Free form optimization example and
constrained optimization will be compared with conventional illumination setting. Furthermore realization of the SMO
with sPURE, which is optical element to generate customized illumination discussed.
Intensive optimization of masks and sources for 22nm lithography
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Traditional OPC is essentially an iterated feedback process, in which the position of each target edge is corrected by
adjusting a controlling mask edge. However, true optimization adjusts the mask variables collectively, and in so-called
SMO approaches (for Source Mask Optimization) the source variables are adjusted as well. Optimized masks often have
high edge density if synthesis methods are used in an effort to obtain a more global solution, and the correspondence
between individual mask edges and printed target edges becomes less clearcut than in traditionally OPC'd masks.
Restrictions on phase shift and MEEF tend to reduce this departure from traditional solutions, but they trade off the
theoretical performance advantage in dose and focus latitude that phase shift provides for a reduced sensitivity to thick
mask topography and to manufacturing error. Mask variables couple across long distances only in the indirect sense of
stitched connection across chains of neighbor-to-neighbor interactions, but source variables interact directly across entire
masks. Source+mask optimization of large areas therefore involves long-range communication across the parts of the
calculation, though the number of source variables involved is small. Tradeoffs between source structure, pattern
diversity, and design regularity are illustrated, taking into account the limited (but unknown) number of binding features
in a large layout. SMO's exploitation of complex source designs is shown to provide superior solutions to those obtained
by mask optimization alone.
Moreover, in development work the
ability to adjust the source opens up
new options in process engineering,
and these will become particularly
valuable when future exposure tools
provide greater flexibility in
programmable source control. Such
capabilities can be explored in a
preliminary way by using
programmed multi-scans to compose
optimized compound sources with
e.g. multiple poles or annular
elements.
Experimental result and simulation analysis for the use of pixelated illumination from source mask optimization for 22nm logic lithography process
Show abstract
We demonstrate experimentally for the first time the feasibility of applying SMO technology using pixelated illumination. Wafer images of SRAM contact holes were obtained to confirm the feasibility of using SMO for 22nm node lithography. There are still challenges in other areas of SMO integration such as mask build, mask inspection and repair, process modeling, full chip design issues and pixelated illumination, which is the emphasis in this paper. In this first attempt we successfully designed a manufacturable pixelated source and had it fabricated and installed in an exposure tool. The printing result is satisfactory, although there are still some deviations of the wafer image from simulation prediction. Further experiment and modeling of the impact of errors in source design and manufacturing will proceed in more detail. We believe that by tightening all kind of specification and optimizing all procedures will make pixelated illumination a viable technology for 22nm or beyond.
Publisher's Note: The author listing for this paper has been updated to include Carsten Russ. The PDF has been updated to reflect this change.
Enabling process window improvement at 45nm and 32nm with free-form DOE illumination
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We present a method for optimizing a free-form illuminator implemented using a diffractive optical element (DOE). The
method, which co-optimizes the source and mask taking entire images of circuit clips into account, improves the
common process-window and 2-D image fidelity. We compare process-windows for optimized standard and free-form
DOE illuminations for arrays and random placements of contact holes at the 45 nm and 32 nm nodes. Source-mask cooptimization
leads to a better-performing source compared to source-only optimization. We quantify the effect of typical
DOE manufacturing defects on lithography performance in terms of NILS and common process-window.
Benefits and trade-offs of global source optimization in optical lithography
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Source optimization in optical lithography has been the subject of increased exploration in recent years [1-4], resulting in
the development of multiple techniques including global optimization of process window [4]. The performance
advantages of source optimization have been demonstrated through theory, simulation, and experiment. This paper will
emphasize global optimization of sources over multiple patterns, e.g. co-optimization of critical SRAM cells and the
critical pitches of random logic, and implement global source optimization into current resolution enhancement
techniques (RETs). The effect on optimal source due to considering multiple patterns is investigated. We demonstrate
that optimal source for limited patterns does work for a large clip of layout. Through theoretical analysis and
simulations, we explain that only critical patterns and/or critical combinations of patterns determine the final optimal
source; for example those patterns that contain constraints which are active in the solution. Furthermore, we illustrate,
through theory and simulation, that pixelated sources have better performance than generic sources and that in general it
is impossible for generic sources to construct a truly optimal solution. Sensitivity, tool matching, and lens heating issues
for pixelated sources are also discussed in this paper. Finally, we use a RETs example with wafer data to demonstrate the
benefits of global source optimization.
Spacer-based Processes
Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning
Show abstract
Self-Aligned Double patterning (SADP) technology has been identified as the main stream patterning technique for
NAND FLASH manufacturers for 3xnm and beyond. This paper demonstrates the successful fabrication of 32nm halfpitch
electrical testable NAND FLASH wordline structures using a 3-mask flow. This 3-mask flow includes one critical
lithography step and two non-critical lithography steps. It uses a positive tone (spacer as mask) approach to create 32nm
doped poly wordlines. Electrical measurements of line resistance are performed on these doped poly wordlines to
demonstrate the capability of this patterning technique. Detailed results and critical process considerations, including
lithography, deposition and etch, will be discussed in this paper.
Advanced self-aligned double patterning development for sub-30-nm DRAM manufacturing
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Although the Numerical Aperture (NA) has been greatly improved from 0.93 (dry) to 1.35 (wet) by the introduction of
modern water immersion 193nm scanner since 2001, the realistic single exposure photolithography printing for mass
production is still limited to ~40nm, even with the help of a variety of Resolution Enhancement Techniques (RETs).
Theoretically, the 193nm immersion scanner with high index fluid or Extreme UV (EUV) scanner with a significantly
shorter wavelength of 13.5nm would be the logical successors to water immersion 193nm scanner. However, considering
tremendous technical difficulties to work with high index fluids and relatively immature and very low productivity of
EUV at the moment, it's likely that both candidates have little chance to entering production prior to 2012. Additionally,
the production schedule can be further pushed out due to formidable initial investment for the costly equipment and
consumables associated with EUV given the present worldwide economic recession. Nano-imprint may be attractive for
its low cost and versatile nature, however, long-term stability and logistics under production stress yet to be established.
The hope to continue the thrust of Moore's Law into the sub-40nm regime before EUV era heavily counts on the success
of the so-called Double Patterning Techniques (DPT).
A variety of integration schemes have been developed or are still under development to harness the full capacity of DPT.
Among them the spacer double patterning approach stands out because of the self-aligned characteristics and a
cumulative great deal of experience on the handling of the spacer-related processes in traditional CMOS process
integration. The final goal of most research works around Self-Aligned Double Patterning (SADP) focuses on achieving
minimal added cost and high quality printing at the same time. However, most of the time the quality and the cost are
compromised by applying non-production proven new material/new hardware and/or fancy integration approaches. In
our study we purposely apply a more "classical" and relatively conservative integration scheme, with all unit process
steps long proven in previous volume production. By carefully optimizing the relative CMP, films deposition, etch and
cleaning processes, we are able to demonstrate 30nm line/space patterns by an NA 0.93 dry 193nm scanner with optimal
CDU better than 3nm and high frequency line edge roughness (LER) close to 2nm/side. Additionally, by analyzing
wafer quality for alignment and alignment residual in various alignment & overlay mark designs, projected residual
overlay as little as 4nm can be readily obtained.
Process step reduction at negative tone spacer patterning technique using developer soluble bottom ARC
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While spacer is essential to separate the second lines from the first lines at negative tone spacer patterning technique,
Spacer brings side effects such as increase in process step as well as CD budget induced by spacer. To eliminate these
side effects, we have chosen the combination of photo resist as the first lines and developer soluble bottom ARC as the
second lines at negative tone spacer patterning technique. This process scheme consists of only two mask steps; one is
critical mask for the first lines in cell and peripheral cell, and another is non-critical mask for recess of the second lines
in cell area and removal of the second lines in peripheral area. By the diffusion of acid from photo resist into developer
soluble bottom ARC, developer soluble bottom ARC adjacent to photo resist of the first line is transformed into the
substance, which can be easily removed by developer dispensed after the second mask exposure. With the adoption of
developer soluble bottom ARC, we can expect to make progress in cost reduction at negative tone spacer patterning
technique.
Gridded design rule scaling: taking the CPU toward the 16nm node
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The Intel 45nm PenrynTM CPU was a landmark design, not only for its implementation of high-K metal gate
materials1, but also for the adoption of a nearly gridded design rule (GDR) layout architecture for the poly silicon
gate layer2. One key advantage of using gridded design rules is reduction of design rules and ease of 1-
dimensional scaling compared to complex random 2-dimensinal layouts. In this paper, we demonstrate the scaling
capability of GDR to 16nm and 22nm logic nodes. Copying the design of published images for the Intel 45nm
PenrynTM poly-silicon layer2, we created a mask set designed to duplicate those patterns targeting a final pitch of
64nm and 52nm using Sidewall Spacer Double Patterning for the extreme pitch shrinking and performed
exploratory work at final pitch of 44nm. Mask sets were made in both tones to enable demonstration of both
damascene (dark field) patterning and poly-silicon gate layer (clear field) GDR layouts, although the results
discussed focus primarily on poly-silicon gate layer scaling.
The paper discusses the line-and-cut double patterning technique for generating GDR structures, the use of
sidewall spacer double patterning for scaling parallel lines and the lithographic process window (CD and
alignment) for applying cut masks. Through the demonstration, we highlight process margin issues and suggest
corrective actions to be implemented in future demonstrations and more advanced studies. Overall, the process
window is quite large and the technique has strong manufacturing possibilities.
Double Patterning I
Split, overlap/stitching, and process design for double patterning considering local reflectivity variation by using rigorous 3D wafer-topography/lithography simulation
Show abstract
Double patterning (DP) was investigated for logic layout by using rigorous 3D wafer-topography/
lithography simulator with water immersion lithography. With increasing complexity of DP process,
3D wafer-topography effect of stack structure must be considered, because of its impact to
lithography.
The main purpose of this paper is to present how to optimize both process and design to ensure
overlap and connectivity of split pattern, by solving electro-magnetic field distribution in wafer
substrate as well as resist region.
Process window was analyzed varying not only focus, dose and split masking layers, but also
considering topography of substrate stack structures, which cause local reflectivity variations.
Arbitrary 45nm logic layout including L-shape pattern was analyzed. Process window of second
Litho step was analyzed. Due to reflection from Hard Mask, HM (the first Litho step) the process
window was restricted and became smaller. The other option, swapping first and second Litho
masks is a better choice with respect to impact of wafer topography.
The optimization of stack process condition was analyzed by using contour plot of reflectivity, as
functions of n, k and thickness of materials inside BARC. The concept of Extended NILS
considering local reflectivity variation from wafer process is able to explain the variation of resist
sidewall slope and Exposure Latitude. Therefore, it is useful to analyze connectivity at stitching
point by using 3D wafer-topography/ lithography simulator and to optimize the combination of DP
process and layout stitching design. Furthermore as design of advanced process, LLE
(Litho-Litho-Etch), with resist freezing was simulated.
Advances and challenges in dual-tone development process optimization
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The ever-shrinking circuit device dimensions challenge lithographers to explore viable patterning for the 32 nm halfpitch
node and beyond. Significant improvements in immersion lithography have allowed extension of optical
lithography down to 45 nm node and likely into early 32 nm node development. In the absence of single-exposure
patterning solutions, double patterning techniques are likely to extend immersion lithography for 32 nm node
manufacturing. While several double patterning techniques have been proposed as viable manufacturing solutions, cost,
along with technical capability, will dictate which candidate is adopted by the industry.
Dual-tone development (DTD) has been proposed as a potential cost-effective double patterning technique.1 Dual-tone
development was reported as early as in the late 1990's by Asano.2 The basic principle of dual-tone imaging involves
processing exposed resist latent images in both positive tone (aqueous base) and negative tone (organic solvent)
developers. Conceptually, DTD has attractive cost benefits since it enables pitch doubling without the need for multiple
etch steps of patterned resist layers. While the concept for DTD technique is simple to understand, there are many
challenges that must be overcome and understood in order to make it a manufacturing solution.
This work presents recent advances and challenges associated with DTD. Experimental results in conjunction with
simulations are used to understand and advance learning for DTD. Experimental results suggest that clever processing
on the wafer track can be used to enable DTD beyond 45 nm half-pitch dimensions for a given resist process. Recent
experimental results also show that DTD is capable of printing <0.25 k1-factor features with an ArF immersion scanner.
Simulation results showing co-optimization of process variables, illumination conditions, and mask properties are
presented.
New process proximity correction using neural network in spacer patterning technology
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A neural network (NN)-based approach with a lumped model is found to be much more promising to predict process
proximity effects (PPEs) caused through space patterning processes than a conventional tandem-based approach with a
consecutive physical model. The NN-based lumped approach can improve PPE prediction accuracy by 25% compared to
the conventional tandem-based approach, subject to the same workload of experimental data acquisition, and reach the
specification of PPE residual in 3x nm node with smaller amounts of data volume than any other approach. Process
proximity correction scheme using the NN-based lumped model built for 3x nm node can achieve the expected
correction accuracy for various kinds of one-dimensional patterns. It is anticipated that the NN-based lumped PPE
prediction model will greatly improve the prediction and/or correction accuracy in the space patterning technology
process for 3x nm node and beyond.
32nm and below logic patterning using optimized illumination and double patterning
Show abstract
Line/space dimensions for 32nm generation logic are expected to be ~45-50nm at ~90-100nm pitch. It is likely that the
node will begin at the upper end of the range, and then shrink by ~10% to a "28nm" node. For the lower end of the
range, even with immersion scanners, the Rayleigh k1 factor is below 0.32. The 22nm logic node should begin with
minimum pitches of approximately 70nm, requiring some form of double patterning to maintain k1 above 0.25.
Logic patterning has been more difficult than NAND Flash patterning because random logic was designed with complete
"freedom" compared to the very regular patterns used in memory. The logic layouts with bends and multiple pitches
resulted in larger rules, un-optimized illumination, and a poorly understood process windows with little control of
context-dependent "hot spots."[1]
The introduction of logic design styles which use strictly one-directional lines for the critical levels now gives the
opportunity for illumination optimization. Gridded Design Rules (GDR) have been demonstrated to give areacompetitive
layouts at existing 90, 65, and 45nm logic nodes while reducing CD variability.[2] These benefits can be
extended to ≤32nm logic using selective double pass patterning.
Double Patterning II
Analysis of topography effects on lithographic performance in double patterning applications
Show abstract
Double Patterning (DP) is considered the most viable solution for printing features of the 32nm technology node using
193nm immersion lithography. Independent of the approach of the DP implementation (be it Litho-Etch-Litho-Etch or
Litho-Process-Litho-Etch), the second lithography step is influenced by the underlying topography on the wafer. Given
the tight constraints on the process, an accurate prediction of the impact of the embedded topography on critical features
is inevitable to meet the design requirements of the corresponding device layer. In this paper we use rigorous simulations
of the electro-magnetic field distribution to quantify the effect of wafer topography on the second lithography step. In
particular, we investigate the impact of the topography on CD control and corresponding process windows for typical 1D
patterns. The influence of non-flat BARC, non-flat resist surfaces, hard mask material and process variations in the first
litho step is simulated for dual line as well as dual trench processes. A metric to quantify standing waves in resist is
introduced and used to optimize BARC thickness. Further, we investigate typical 2D clips of decomposed mask layouts
relevant for the 32nm node. The simulation methodology and algorithm performance are presented, in particular with
respect to its distributed computing capabilities.
Ultimate contact hole resolution using immersion lithography with line/space imaging
Show abstract
Contact Hole (CH) resolution is limited by the low aerial image contrast using dark field masks. Moreover the 2-
Dimensional character of CH is a limiting factor in the use of extreme Resolution Enhancement Techniques for reaching
the smallest pitch. These limitations can be overcome if one deconvolves the 2D CH into two exposures of 1D structures
(i.e. lines). These 1D structures can indeed be printed at the ultimate resolution limit of the scanner using dipole
exposures.
Recently, several materials have become available to pattern CH from such a double exposure of line patterns. It is
shown in this paper how this concept of deconvolution can be used in different techniques:
Two 1D aerial images can be recomposed in order to obtain 2D images which will subsequently be reversed into
CH. We can distinguish, on the one hand, a reversal based on the positive development of line crossings into resist pillar
patterns, on which are deposited or coated a gap-fill material layer. The pillars are then removed, leaving a masking
material layer with holes. On the other hand, negative tone development can be used to reverse directly the recomposed
2D aerial image: while the classical positive development creates pillars, the negative tone development inverses
immediately this image to create contact holes in the resist layer.
In this paper, we demonstrate the potential of the double exposure method. We characterise three reversal
techniques using a NA=1.35 immersion scanner for patterning 40nm or lower CH at pitch 80nm. We also show etch
performance of these processes and address the complexity of each solution.
Efficient simulation and optimization of wafer topographies in double patterning
Show abstract
As the technology marches towards the 32nm node and beyond in semiconductor manufacturing, double patterning and
double exposure techniques are currently regarded as the potential candidates to produce lines and spaces (L&S) and
contact holes (C/H), respectively. In this paper, the Waveguide method, a rigorous electromagnetic field (EMF) solver,
is employed to investigate the impact of wafer topographies on two specific double patterning techniques. At first, the
topography effects induced by the first patterning on the second lithography process in a lithography-etch-lithographyetch
(LELE) process are demonstrated. A new methodology of the bottom anti-reflective coating (BARC) optimization
is proposed to reduce the impact of wafer topography on resist profiles. Additionally, an optical proximity correction
(OPC) of the second lithography mask is demonstrated to compensate the wafer topography induced asymmetric
deformations of line ends. Rigorous EMF simulations of lithographic exposures are also applied to investigate wafer
topography effects in a freezing process. The difference between the optical properties of the frozen (first) resist and the
second resist potentially causes linewidth variations. Quantitative criteria for tolerable refractive index and extinction
differences between the two resist materials are given. The described studies can be used for the optimizations of
topographic waferstacks, the OPC of the second litho mask, and for the development of resist materials with appropriate
optical properties.
Investigating the impact of topography on pitch splitting double patterning using rigorous physical simulation
Show abstract
Simulation work centered on double patterning processes often assumes that the problem can be
approximated by considering the summation of two simple planar simulations which exhibit no interaction.
Although previous work has shown that this assumption seems reasonable for interleaved line or trench patterns, it is
less clear how valid it is for stitching areas where features in the two passes deliberately overlap and impinge upon
each other. This work uses rigorous optical and physical resist models to study the validity of the planar summation
approximation for stitching areas in a representative LELE (Litho-Etch-Litho-Etch) double line-based front end
poly-silicon level process and a LELE double trench based back-end metal level process. The results suggest that the
approximation holds well for back-end processes employing metal nitride type hardmask materials (which typically
exhibit BARC-like optical properties). However significant deviations in behavior are observed for the poly-silicon
level process suggesting that the approximation should be used with more caution on front-end processes utilizing
transparent or reflective hardmask materials. It is apparent that the optical constants of both the hardmask and
BARC , in addition to the tone of the double patterned feature, contribute to deviations from the approximation.
Thus it is important to determine the approximation's validity on a process by process basis.
Tools Related Process Control I
Scanner OPC signatures: automatic vendor-to-vendor OPE matching
Show abstract
As 193nm lithography continues to be stretched and the k1 factor decreases, optical proximity correction (OPC) has
become a vital part of the lithographer's tool kit. Unfortunately, as is now well known, the design variations of
lithographic scanners from different vendors cause them to have slightly different optical-proximity effect (OPE)
behavior, meaning that they print features through pitch in distinct ways. This in turn means that their response to OPC
is not the same, and that an OPC solution designed for a scanner from Company 1 may or may not work properly on a
scanner from Company 2. Since OPC is not inexpensive, that causes trouble for chipmakers using more than one brand
of scanner.
Clearly a scanner-matching procedure is needed to meet this challenge. Previously, automatic matching has only been
reported for scanners of different tool generations from the same manufacturer. In contrast, scanners from different
companies have been matched using expert tuning and adjustment techniques, frequently requiring laborious test
exposures. Automatic matching between scanners from Company 1 and Company 2 has remained an unsettled problem.
We have recently solved this problem and introduce a novel method to perform the automatic matching. The success in
meeting this challenge required three enabling factors. First, we recognized the strongest drivers of OPE mismatch and
are thereby able to reduce the information needed about a tool from another supplier to that information readily
available from all modern scanners. Second, we developed a means of reliably identifying the scanners' optical
signatures, minimizing dependence on process parameters that can cloud the issue. Third, we carefully employed
standard statistical techniques, checking for robustness of the algorithms used and maximizing efficiency. The result is
an automatic software system that can predict an OPC matching solution for scanners from different suppliers without
requiring expert intervention.
Dense lines created by spacer DPT scheme: process control by local dose adjustment using advanced scanner control
Show abstract
In this paper we present a methodology to investigate and optimize the CD balance between the four
features of a final 32nm lines and space pattern created by spacer pitch doubling.
Metrology (SEM and scatterometry) was optimized to measure and separate the two lines and the
two spaces of the 32nm features. In case a space unbalance emerged during the various processing
steps such as etch and deposition, this was compensated by calculating and feed-back local dose
offsets to the scanner. For the spacer process used in this study we observe 20..40% improvement in
space CDU and space balance, when applying the dose corrections.
Focus and dose characterization of immersion photoclusters
Show abstract
The process window for state of the art chip manufacturing continues to decrease, driven by higher NA exposure tools
and lower k1 values. The benefits of immersion lithography for Depth of Focus (DoF) are well known. Yet even with
this immersion boost, NA=1.35 tools can push DoF into sub-100nm territory. In addition, immersion processes are
subject to new sources of dose and focus variation. In order to realize the full potential of immersion lithography, it is
necessary to characterize, understand and attack all sources of process variation.
Previous work has established our dose/focus metrology capability1, in which we expose Process Monitor Grating
(PMG) targets with high sensitivity to focus, measure the PMGs using scatterometry, and use the Ausschnitt dose/focus
deconvolution approach to determine focus errors to within a few nm and dose errors to within 0.1%. In this paper, we
concentrate on applying this capability to the detailed measurements of immersion photoclusters utilizing ASML
exposure tools. Results will include:
• comparison of Twinscan 1700i and 1900i focus capability
• effectiveness of the Reticle Shape Correction (RSC) for non-flat reticles
• visualization of non-flat wafer chucks, tilted image planes, and other systematic focus error components
• tracking of tool trends over time, using automated monitor wafer flows
The highly systematic nature of the observed focus errors suggest potential for future improvements in focus capability.
Model-based scanner tuning in a manufacturing environment
Show abstract
Given the decrease in k1 factor for 65nm-node lithography technology and beyond, it is increasingly important to
understand and control the variables which impact scanner imaging behavior in the lithography process. In this work, we
explore using model simulations to characterize and predict imaging effects of these variables, and then based on such
information to fine-tune the scanner settings to obtain printing results optimally matched to a reference scanner. The
scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for accurate model
construction. To identify critically mismatched patterns on a production layout, we employ the fast full-chip simulation
capability provided by Brion's Tachyon servers. Tachyon simulations are also used to predict wafer impacts of changes
in tunable scanner parameters. A set of optimized scanner variable offsets, called a "scanner tuning recipe", is generated
to minimize overall imaging mismatch between two scanners. As a proof-of-concept, we have carried out scanner tuning
procedures on selected ASML scanners. The results show improvements more than 20% on CD offset RMS values for
2D line-end patterns, production layout patterns, and the mismatched patterns identified with the full-chip simulation.
Improvements on wafer-acceptance-test results and production yield on the to-be-tuned scanner are also observed.
Scanner-dependent optical proximity effects
Show abstract
Optical imaging of IC critical designs is impacted by optical proximity effects, OPEs,
originating from finite numerical aperture of projection lenses used in modern projectors. The
OPE's are caused by filtering of pattern diffraction orders falling outside of the lens band pass.
Controlling OPEs is so critical to IC performance, that IC design community implemented optical
proximity correction, OPC, modifying the IC mask patterns to provide wafer images matching the
IC design intent. The mainstream OPC uses optical models representing fundamental imaging
setup and it does not capture the impacts of engineering scanner tool constraints.
The OPEs are impacted by scanner lens and illuminator signatures causing CD excursions
large in comparison to the CD error budgets(1). The magnitude of the scanner impacts on OPEs
necessitated new optical modeling paradigm involving imaging models imbedding scanner
signatures representing population of scanners of a given type. These scanner-type based models
represent quantum leap in accuracy of lithography simulation technology, resulting in OPE and
OPC representing a broad range of realistic scanner characteristics(2).
In this context, a relevant question is: to what degree, the signatures of individual scanners
impact the accuracy of imaging models and OPE predictions? To answer this question, we
analyzed optical proximity responses of hyper-NA scanners represented by their signatures. We
first studied a set of OPEs impacted by the scanner-type signatures. We then generated a set of
corresponding OPEs impacted by the signatures of individual scanners. We compared the two
kinds of OPEs and highlighted the scanner-specific image formation responses.
Tools Related Process Control II
Challenges and solutions in the calibration of projection lens pupil-image metrology tools
Show abstract
As imaging requirements and limits continue to be pushed tighter and lower, it has become imperative that accurate and
repeatable measurement of the projection lens (PL) pupil be readily available. These are important for setup and
adjustment of the illumination distribution, measurement and optimization of the lens aberrations, and verification of
lens NA and transmission. Accurate testing of these items is critical during initial installation and setup of a
photolithography tool, but it continues to prove useful each time any projection lens pupil-image measurement is made.
The basic raw data from any such measurement is in the form of a pixelized 'image' captured by a projection lens pupil
microscope. Such images have typically been referred to as pupilgrams1, and many prior works have reported on their
application and analysis1,2,3.
Each of these measurements can be affected by errors in the measurement tool used. The error modes can be broadly
divided into two distinct groups: uncompensated transmission loss, and uncompensated distortion (or remapping) error.
For instance, in illuminator measurements, the first will yield intensity error and the second will yield image shape
mapping error.
These errors may or may not lie exclusively in the optics of the measurement tool. But, regardless of their source, they
will propagate through the analysis of the pupilgram images. For this reason, at minimum they must be measured and
judged for relative impact, if only to confirm that the errors do not change the conclusions or results.
In this paper, we will discuss and present methods for measuring the image distortion present in a PL pupil-image
microscope. These data are used to build a 'map' of errors vs. position in the lens pupil. The maps then serve as the
basis for image-processing-based compensation that can be applied to all subsequent microscope images.
A novel vitally important feature of the technique presented is that it calibrates the distortion of the microscope image
field using fundamental optical physics. This is achieved by imaging, capturing, and analyzing the diffraction pattern of
reticle gratings. Several different reticle pattern pitches are imaged and their diffraction patterns are captured by the
microscope. The image field of the microscope is then calibrated to the spacing of the diffraction orders, meaning that
the calibration is traceable through fundamental optics to the very precise reticle patterns. Details of this procedure,
including an example, will be presented.
Impact of CD and overlay errors on double-patterning processes
Show abstract
Double patterning (DP) is today the main solution to extend immersion lithography to the 32 nm node and beyond. Pitch
splitting process with hardmask transfer and spacer process have been developed at CEA-LETI-Minatec. This paper
focuses on experimental data using dry ArF lithography with a k1 factor of 0.20 ; the relative impact of each DP step on
overlay and CD uniformity budgets is analyzed. In addition, topography issues related to the presence of the patterned
hard mask layer during the second imaging step is also investigated. Tool-to-itself overlay, image placement on the
reticle and wafer deformation induced by this DP process are evaluated experimentally and resulting errors on CD
budget have been determined. CD uniformity error model developed by Nikon describing the relationship between CD
and overlay in different DP processes is validated experimentally.
Achieving overlay budgets for double patterning
Show abstract
The problem of the alignment tree for double patterning (DP) is presented. When the 2nd DP exposure is aligned to the
underlying zero layer, the space CD uniformity is shown to be well outside the budget for the 32 nm HP node. Aligning
the 2nd DP layer to the zero layer gives better overlay results, but aligning the 2nd DP pattern to the 1st DP pattern gives
results well within the overlay requirements for the 32 nm HP. Aligning the 2nd DP layer to the 1st DP layer is
recommended to give the best CD uniformity and overlay results. Experimental results show, qualitatively, the CD
uniformity is significantly worse when the 2nd pattern is aligned to the zero layer, but the overlay for both alignment trees
could be corrected to roughly the same levels. The raw overlay data shows a significantly different signature for the two
alignment trees, possibly caused by alignment mark signal differences between the marks on the zero and 1st layers, or
distortion of the zero layer after the first etch. The requirements for a DP exposure tool were reviewed and can be
summarized as improved dose control, improved overlay performance, and significantly higher throughput.
Innovative pattern matching method considering process margin and scanner design information
Show abstract
Methods to improve accuracy of pattern matching are investigated with our software tool (k1 TUNE). Since pattern
matching handles experimental data, resist simulation accuracy, SEM measurement accuracy, and identification of
illumination situations used in the software and set in actual scanners are crucial. The methods to reduce their error are
proposed. In addition to reducing them, a subtracting method is used to compensate them for better pattern matching.
The effectiveness is certificated experimentally with accuracy of 0.010 sigma of illumination and 1~2nm of CD.
Furthermore an illumination that keeps CDs constant under defocus is optimized, and the characteristics are confirmed
experimentally.
By using the software tool under the proposed ways, real pattern matching at fabrication lines has been possible with
good accuracy, few retry, and consideration of defocus characteristics.
Optical Proximity Corrections I
A new method for post-etch OPC modeling to compensate for underlayer effects from integrated wafers
Show abstract
In this paper, we demonstrate a new methodology for post-etch OPC modeling to compensate for effects of
underlayer seen on product wafers. Current resist-only OPC models based on data from flopdown wafers
are not always accurate enough to deliver patterning solutions with stringent critical dimension
requirements in 45/32nm technology node. Therefore it is necessary to include an etch model into the OPC
correction. Both litho and etch model were built using flopdown and integrated wafers to compensate for
topography, differential etch due to different underlayer substrate based on local geometry and local
loading. The wafer data based on such OPC keyword show significant decrease of critical dimensions
offsets of device macros from long poly-line nested structures for gate level. We will compare wafer data
from two different OPC model versions built from flopdown and integrated wafer. We will also discuss
modeling options in terms of two layer test masks for future technologies.
Optimal setting strategy for kernel-based OPC simulation engines
Show abstract
We have studied the parameter setting dependence on the OPC TAT and OPC accuracy. We have found that we can
save OPC TAT with sufficient accuracy by optimizing the optical diameter, fringe length, and the kernel counts in
optical simulations of OPC. The optical diameter should be set to the optimal value depending on its mask design
regularity. In the kernel-based optical simulations, the residual error is found to drop suddenly at the critical kernel count.
This critical kernel count is found to be almost independent of the optical diameter, aberrations, and resist stack
structures. On the other hand, it is clarified that the critical kernel count is strongly correlated with the coherence factor
of the illuminations. Using this critical kernel count, we can obtain the image intensities with sufficient accuracy. We
propose a method to determine fringe length by analyzing the characteristics of the optical kernels that are independent
of the mask layouts.
Improving yield through the application of process window OPC
Show abstract
As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process
windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC
verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust
solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively
impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and
verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process
robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable
first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by
identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not
catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable
of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while
maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented
for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC.
Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen
the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process
variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement.
Etch aware optical proximity correction: a first step toward integrated pattern engineering
Show abstract
We present an etch-aware optical proximity correction (OPC) flow that is intended to optimize post-etch patterns
on wafer. We take advantage of resource efficient empirical etch models and a model based retargeting scheme
to determine post-develop in-plane resist targets required to achieve post-etch critical dimensions. The goal of
this flow is to optimize final patterns on wafer rather than two independent patterns from lithography and etch.
As part of this flow, we cover important aspects of etch process variability implications for etch aware OPC.
Metrics for total pattern transfer are developed and explored with an eye toward optimizing pattern transfer.
We present results from a 45 nm poly-silicon and 32 nm shallow trench isolation levels where etch aware OPC
has been applied and compare these results with conventional resist based OPC schemes.
Finally, implications of this flow for unit process developers in lithography and reactive ion etch are explored.
We present a process optimization flow that incorporates model based retargeting into resolution enhancement
technology selection, materials selection as well as lithographic and reactive ion etch process development.
Integrating assist feature print fixing with OPC
Show abstract
A challenge in model-based assist feature placement is to find optimal placements while satisfying
mask rules and preventing AF printing. There are numerous strategies for achieving this ranging
from fully rule-based methods to pixel-based inversion. Our proposed solution is to identify the
optimal locations of assist features using modeling information based strictly on optics and resist
stack optical characteristics. Once these positions have been found, preliminary AFs can be placed.
At this point suggested sizes and shapes can be identified, although these can later be modified. In a
later step, MRC cleanup, printability fixing, and main-pattern OPC can be performed simultaneously.
This has the advantage of allowing the use of the full process model to predict the location of OPC
edges accurately, and use calibrated or 3d mask models to determine assist feature printing behavior.
This correction is done while maintaining MRC constraints. In this flow, an AF placement field,
generated from the pre-OPC target patterns, can be used to provide accurate guidance on how to
move assist features to get the most benefit while keeping other constraints in mind. Using this
method, a range of printability fixing strategies, guided by placement benefits, is available. We
present data showing that the benefit of AF placements can be determined from optical parameters,
on target (non-OPC) data, and that this method leads to beneficial yet compliant masks.
Double-patterning-friendly OPC
Show abstract
Double patterning technology (DPT) is one of the main options for printing critical layers at
32nm half-pitch and beyond. To enable DPT, a layout decomposition tool is first used to split the
original design into two separate decomposed-design layouts. Each decomposed-design layout
may then receive optical proximity correction (OPC) and RETs to produce a mask layout. The
requirements for OPC to enable individual layer DPT patterning are generally the same as
current single exposure OPC requirements, meaning that the success criteria will be similar to
previous node specifications. However, there are several new challenges for OPC with DPT.
These include large litho-etch biases, two sets of process variables associated with each
patterning layer and the relative pattern placement between them. The order of patterning may be
important as there may be process interactions between the two patterns especially at overlap
regions. Corners which were rounded in single patterning layers may now become sharp,
potentially increasing reliability concerns due to electromigration. In this study, we address many
of these issues by proposing several new techniques that can be used in OPC with DPT. They
are specifically designed for the Litho-Etch-Litho-Etch process, but some of the ideas may be
extended to develop OPC methods for other DPT processes. We applied the new OPC method to
several circuit and test patterns and demonstrated how OPC results were improved compared to
regular OPC methods.
Optical Proximity Corrections II
Calibrating OPC model with full CD profile data for 2D and 3D patterns using scatterometry
Show abstract
The ability to manage critical dimensions (CDs) of structures on IC devices is vital to improving product yield
and performance. It is challenging to achieve accurate metrology data as the geometries shrink beyond 40 nm features.
At this technology node CDSEM noise and resist LER are of significant concerns1.
This paper examines the extendibility of scatterometry techniques to characterize structures that are close to limits of
lithographic printing and to extract full profile information for 2D and 3D features for OPC model calibration2. The resist
LER concerns are diminished because of the automatic averaging that scatterometry provides over the measurement pad;
this represents a significant added value for proper OPC model calibration and verification. This work develops a
comparison matrix to determine the impact of scatterometry data on OPC model calibration with conventional CDSEM
measurements. The paper will report test results for the OPC model through process data for accuracy and predictability.
Impact of modelisation pixel size on OPC consistency
Show abstract
In advanced technology nodes, due to accuracy and computing time constraint, OPC has shifted from discrete simulation
to pixel based simulation. The simulation is grid based and then interpolation occurs between grid points. Even if the
sampling is done below Nyquist rate, interpolation can cause some variations for same polygon placed at different
location in the layout. Any variation is rounded during OPC treatment, because of discrete numbers used in OPC output
file. The end result is inconsistency in post-OPC layout, where the same input polygon will give different outputs,
depending on its position and orientation relative to the grid. This can have a major impact in CD control, in structures
like SRAM for example, where mismatching between gates can cause major issue.
There are some workarounds to minimize this effect, but most of them are post-treatment fix. In this paper, we will try to
identify and solve the root cause of the problem. We will study the relationship between the pixel size and the
consistency of post OPC results. The pixel size is often set based on optical parameters, but it might be possible to
optimize it around this value to avoid inconsistency. One can say that the optimization will highly depend on design and
not be possible for a real layout. As the range of pitch used in a design tends to decrease, thanks to fix pitch layouts, we
may optimize pixel size for a full layout.
OPC simplification and mask cost reduction using regular design fabrics
Show abstract
Cost and complexity associated with OPC and masks are rapidly increasing to the point that they could limit technology
scaling in the future. This paper focuses on demonstrating the advantages of regular design fabrics for OPC
simplification to enable scaling and minimize costs for technologies currently in volume production. The application of
such a simplified OPC flow results in much smaller mask data volumes due to significantly fewer edges compared to the
conventional designs and OPC flows. Moreover, the proposed approach enables reduced mask write times, hence lower
mask costs.
We compare OPC performance and complexity on standard cell designs to that of layouts on a regular design fabric. We
first demonstrate advantages and limitations within an industrial model-based OPC solution. Then, a simplified rulebased
OPC solution is discussed for the Metal 1 layer. This simplified OPC solution demonstrates a 70X run time
improvement and an order of magnitude reduction in both the output edge count per unit shape and shot count per unit
shape while maintaining the printabalility advantages of regular design fabrics. The simplified OPC also demonstrates a
50% reduction in mask-write time. Finally, the benefit of regular design fabrics for OPC simplification and mask cost
reduction at a 32nm node is discussed.
Resist development modeling for OPC accuracy improvement
Show abstract
A precise lithographic model has always been a critical component for the technique of Optical Proximity Correction
(OPC) since it was introduced a decade ago [1]. As semiconductor manufacturing moves to 32nm and 22nm technology
nodes with 193nm wafer immersion lithography, the demand for more accurate models is unprecedented to predict
complex imaging phenomena at high numerical aperture (NA) with aggressive illumination conditions necessary for
these nodes. An OPC model may comprise all the physical processing components from mask e-beam writing steps to
final CDSEM measurement of the feature dimensions. In order to provide a precise model, it is desired that every
component involved in the processing physics be accurately modeled using minimum metrology data. In the past years,
much attention has been paid to studying mask 3-D effects, mask writing limitations, laser spectrum profile, lens pupil
polarization/apodization, source shape characterization, stage vibration, and so on. However, relatively fewer studies
have been devoted to modeling of the development process of resist film though it is an essential processing step that
cannot be neglected. Instead, threshold models are commonly used to approximate resist development behavior. While
resist models capable of simulating development path are widely used in many commercial lithography simulators, the
lack of this component in current OPC modeling lies in the fact that direct adoption of those development models into
OPC modeling compromises its capability of full chip simulation. In this work, we have successfully incorporated a
photoresist development model into production OPC modeling software without sacrificing its full chip capability. The
resist film development behavior is simulated in the model to incorporate observed complex resist phenomena such as
surface inhibition, developer mass transport, HMDS poisoning, development contrast, etc. The necessary parameters are
calibrated using metrology data in the same way that current model calibration is done. The method is validated with a
rigorous lithography process simulation tool which is based on physical models to simulate and predict effects during the
resist PEB and development process. Furthermore, an experimental lithographic process was modeled using this new
methodology, showing significant improvement in modeling accuracy in compassion to a traditional model. Layout
correction test has shown that the new model form is equivalent to traditional model forms in terms of correction
convergence and speed.
Optical Proximity Corrections III
OPC for reduced process sensitivity in the double patterning flow
Show abstract
The pitch-splitting of patterns using the litho-etch-litho-etch double patterning technique (DPT) may be
required at the 22nm node. By splitting the layout into 2 masks, DPT introduces some new potential failure
mechanisms. These new failure mechanisms can occur if the layer decomposition and subsequent OPC fail
to account for interlayer misalignment and corner rounding of the decomposed masks. This paper will
suggest novel solutions which can be taken during the OPC step to account of interlayer misalignment and
corner rounding at decomposed edges. These methods will be shown to produce improved process window
and reduced sensitivity to misalignment compared to a conventional OPC without interlayer awareness.
Through-focus pattern matching applied to double patterning
Show abstract
A fast-CAD method for evaluating through-focus interaction among features is developed based on dual layout
convolution kernels derived and tested for accuracy in predicting intensity changes. The model is derived by extending
the Taylor series expansion for OPD to include a quadratic term, resulting in not only the usual pattern match factor Z3
for defocus, but also match factors for Z0 and Z8. The model is tested through-focus on a logic layout and the predicted
intensity change versus the actual intensity change through-focus is graphed. Results for basic case near coherent
illumination show an R2 of 0.92. Generalization to use only two patterns instead of three is shown to work well for line
ends, with an R2 of 0.96.
Resolution Enhancement
A novel methodology for hybrid mask AF generation for 22 and 15nm technology
Show abstract
Mask AF (AF), both printable (PRAF) and non-printable - or sub-resolution - AF (SRAF) have been part of the
established lithography and RET/OPC toolkit for achieving a manufacturable process window, for several technology
generations. Deployment of AF onto a mask for a full product or test-chip layout has been traditionally rule-driven, i.e.
based on look-up tables of critical feature sizes and corresponding AF, with specified dimensions and at specified
distances. The number of AF per given layout main feature, the set of AF dimensions (widths, heights, etc.) and the
distances (placements) from the main features are collectively referred to as the AF Rules Set. The identification of the
optimal parameters values in an AF Rules Set (or the optimal AF Rules, for short) is a fundamental problem in process
technology development for semiconductor manufacturing, which is typically being addressed by a mixture of heuristic
parametric searches and lithographic simulations. This approach produces a limited number of usable AF rules (mainly
for 1D layout configurations) and often results in insufficient coverage for 2D cases. This paper introduces a novel
methodology for the determination of an optimal AF Rules set, which results in a greatly superior coverage of layout
configurations (both 1D and 2D) and quantitatively verifiable larger common process window. The methodology utilizes
an inverse lithography simulation step, followed by computational geometry analysis and filtering and finally automated
rules extraction. The computational flow, which has been implemented for 22nm process development, delivers an order
of magnitude more rules (i.e. from few tens to several hundred), and often generates non-intuitive 2D rules which could
not have been discovered by heuristic search alone. The presented results illustrate the superior performance of this
technique particularly in the case of contact and metal layers at 22nm. Potential extendibility of this approach for the
15nm node is also discussed.
Pushing the limits of RET with different illumination optimization methods
Show abstract
As we proceed to 22 nm technology node without any advancement from the front of numerical aperture or EUV, it has
become really challenging to come up with a robust solution to confront resolution and process window. At this stage
along with litho friendly design and new advent in lithographic processes, it has become vital to acquire highly
optimized resolution enhancement technology (RET). In this paper, we review different realm of illumination
optimization techniques with combination of currently available source shapes along with pixilated source optimization.
Different source shapes are tested over various technology designs such as 32 nm and 22 nm designs for better fidelity
and process window. We optimize different source shapes manually and also evaluate fidelity with optimized pixilated
source. The results demonstrate how we can achieve better resolution for some layout patterns with different illumination
optimization methods.
A computational technique to optimally design in-situ diffractive elements: applications to projection lithography at the resist resolution limit
Show abstract
Near-field interference lithography is a promising variant of multiple patterning in semiconductor device fabrication
that can potentially extend lithographic resolution beyond the current materials-based restrictions on the
Rayleigh resolution of projection systems. With H2O as the immersion medium, non-evanescent propagation
and optical design margins limit achievable pitch to approximately 0.53λ/nH2O = 0.37λ. Non-evanescent images
are constrained only by the comparatively large resist indices (typically1.7) to a pitch resolution of 0.5/nresist
(typically 0.29). Near-field patterning can potentially exploit evanescent waves and thus achieve higher spatial
resolutions. Customized near-field images can be achieved through the modulation of an incoming wavefront
by what is essentially an in-situ hologram that has been formed in an upper layer during an initial patterned
exposure. Contrast Enhancement Layer (CEL) techniques and Talbot near-field interferometry can be considered
special cases of this approach.
Since the technique relies on near-field interference effects to produce the required pattern on the resist, the
shape of the grating and the design of the film stack play a significant role on the outcome. As a result, it is
necessary to resort to full diffraction computations to properly simulate and optimize this process.
The next logical advance for this technology is to systematically design the hologram and the incident wavefront
which is generated from a reduction mask. This task is naturally posed as an optimization problem, where
the goal is to find the set of geometric and incident wavefront parameters that yields the closest fit to a desired
pattern in the resist. As the pattern becomes more complex, the number of design parameters grows, and the
computational problem becomes intractable (particularly in three-dimensions) without the use of advanced numerical
techniques. To treat this problem effectively, specialized numerical methods have been developed. First,
gradient-based optimization techniques are used to accelerate convergence to an optimal design. To compute
derivatives of the parameters, an adjoint-based method was developed. Using the adjoint technique, only two
electromagnetic problems need to be solved per iteration to evaluate the cost function and all the components
of the gradient vector, independent of the number of parameters in the design.
Feasibility of ultra-low k1 lithography for 28nm CMOS node
Show abstract
We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the
28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask
topography effect and the oblique-incidence. Using the rigorous lithography simulation considering
the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum
pitch required in 28nm node. The optimum mask plate and illumination conditions have been
decided by simulation. The experimental results for 28nm node show that the minimum pitch
patterns and minimum SRAM cell are clearly resolved by single exposure.
Process
Defectivity improvement by modified wafer edge treatment in immersion lithography
Show abstract
ArF immersion lithography has reached mass production stage for 55-40 nm node devices. Especially, defectivity
performance at wafer edge in immersion lithography has been recently discussed in detail, because its controllability is a
key factor to obtain high yield. We have already reported that defectivity was strongly affected by the wafer edge shape
and long edge wafer showed better defectivity performance than short one. We also found remaining flakes or particles
at wafer edge after coating were easy to be peeled off on short edge wafer during exposure and these peeled flakes or
particles were most suspected candidate which induces bridging defects. Therefore it is important to prevent generating
such peeled flakes or particles for good defectivity in immersion lithography. In this paper, we will show the defectivity
results of various kinds of wafers which have different wafer edge shapes (long,short and full-round) and diameters to
investigate the effect of wafer edge geometry on defectivity performance in detail. Furthermore, we investigated the
relation of an edge removal method and the defectivity with referring bevel inspection results at each coating step. We
confirmed that the modified edge removal method well improved the defectivity performance. We will discuss them
based on the latest data and propose the most suitable technique to remove the wafer edge particles before immersion
exposure.
Design of resist stacks with antireflection coatings from the viewpoint of focus budget
Show abstract
Liquid immersion lithography tools with NA=1.3 are being applied for hp4x node device and beyond. As the typical
DOF has been reduced to 100 nm or less for this hyper-NA exposure, precise consideration of the error factors that lead
to DOF reduction is required. The BFD (Best Focus Difference between pattern kinds) induced by resist stack is one of
the error factors yet to be solved. In this work, the BFD induced by resist stack was studied through simulation and
experiment by decomposing it into the following three components: One induced by the "refraction" effect, one induced
by the "reflection" effect and one induced by the "process" effect. Each BFD was evaluated by simulation to make a
BFD budget. Experimental verification was also performed, which confirmed BFD of 25 nm and it was found that over
30 % of the observed BFD was induced owing to resist stack. Based on this result, we discuss a method for controlling
the BFD by utilizing projection lens aberration and review the design flow of resist stacks with antireflection coatings.
Tools I
An innovative platform for high-throughput high-accuracy lithography using a single wafer stage
Show abstract
For 32 nm half-pitch node, double patterning is recognized as the most promising technology since some significant
obstacles still remain in EUV in terms of technology and cost. This means much higher productivity and overlay
performance will be required for lithography tools. This paper shows the technical features of Nikon's new immersion
tool, NSR-S620 based on newly developed platform "StreamlignTM" designed for 2nm overlay, 200wph throughput and
2week setup time.
The S620 is built basically upon Nikon's Tandem Stage and Local Fill Nozzle technology, but has several additional
features. For excellent overlay, laser encoders with short optical path are applied for wafer stage measurement in
addition to interferometers. By using this hybrid metrology, the non-linearity of the encoder scale can be easily
calibrated, while eliminating the air fluctuation error of interferometer. For high throughput, a method with a new
alignment microscope system and a new auto focus mapping, called Stream Alignment is introduced. It makes it possible
to reduce the overhead time between the exposures remarkably. The target productivity is 4,000 wafer outs per day.
Accuracy is also improved because many more alignment points and a continuous wafer height map without stitching are
available. Higher acceleration and faster scan velocity of the stages are also achieved by optimal vibration dynamics
design and new control system. The main body, including the projection lens, is isolated by Sky Hook Technology used
already on the NSR-SF150 and SF155 steppers, and also the reticle stage is mechanically isolated from the main body.
With this new platform, the imaging performance can be maximized.
Novel approaches to meet the requirements for double patterning
Show abstract
In addition to hardware performance enhancement of exposure tool, new functions are needed to be developed to meet
the required performance for realizing double patterning. New functions to improve overlay accuracy are advanced
distortion control and stage control. We have developed a real-time lens magnification control system to enhance
distortion control, which can make peel type, barrel type and trapezoid type of distortion shape, resulting in improving
intra-shot overlay accuracy. Wafer stage grid control function can compensate for shot shift, shot rotation and
magnification for each single shot, realizing drastic advancement in overlay accuracy. As for CD performance
improvement, dose optimization is effective to compenste for CD uniformity according to CD metrology data from
processed wafers. On the other hand, process window enhancement is performed by optimizing illumination mode with
Canon's solution software k1 TUNE. In this paper, we will introduce these new functions.
Extending single-exposure patterning towards 38-nm half-pitch using 1.35 NA immersion
Show abstract
Immersion lithography started to become the main workhorse for volume production of 45-nm devices, and while
waiting for EUV lithography, immersion will continue to be the main technology for further shrinks. In a first step
single exposure can be stretched towards the 0.25 k1 limit, after which various double patterning methods are lining up
to print 32-nm and even 22-nm devices. The immersion exposure system plays a key role here, and continuous
improvement steps are required to support tighter CD and overlay budgets. Additionally cost of ownership (COO) needs
to be reduced and one important way to achieve this is to increase the wafer productivity. In this paper we discuss the
design and performance of a new improved immersion exposure system XT:1950i. This system will extend immersion
towards 38-nm half pitch resolution using a 1.35 NA lens and extreme off axis illumination (e.g. dipole). The system
improvements result in better CDU, more accurate overlay towards 4-nm and higher wafer productivity towards 148-
wph. Last but not least a next step in immersion technology is implemented. A novel immersion hood is introduced
giving more robust low and stable defects performance.
Advanced aberration control in projection optics for double patterning
Show abstract
Wavefront aberrations of the projection optics induce unignorable focus and overlay errors dependent on the shape of the
device pattern and illumination settings. Thus, the 32nm node and the subsequent double patterning lithographic
generation require ever more stringent control of aberrations. For the most recent exposure tools with polarized
illumination and high throughput capabilities in particular, due attention needs to be paid to the influences of aberrations
caused by polarization and exposure load. A system for measuring and correcting polarization aberrations and lens
heating aberrations has been developed, and its technical details and application examples are presented in this paper.
Furthermore, improvement in aberration control on the next generation exposure tool compatible with double patterning
is stated as well.
Polarization aberration control for ArF projection lenses
Show abstract
High NA imaging or/and polarization illumination imaging for exposure tool requires not only scalar aberration
performance but also vectorial aberration (so called polarization aberration) control. There are several methods to
explain vectorial aberrations such as, Jones Matrix Pupil, Pauli spin matrix, etc. Pauli spin matrix may be intuitively
easier to understand and suitable to show scalar wavefront. However, direct use of Pauli spin matrix method may not
express physical meaning of vectorial aberration exactly, especially when the amount of polarization aberration is large.
In this paper we would like to propose a new explanation method, which is natural expansion of scalar aberration
explanation to vectorial aberration explanation and physically mostly exact form.
Furthermore useful approximation of the form makes it possible to make vectorial aberration sum-operant from productoperant.
Using this method, it is possible to use scalar aberration control technique, such as wavefront control, Zernike
sensitivity analysis, Zernike linear combination method, etc. to vectorial aberration control.
Tools II
Modeling laser bandwidth for OPC applications
Show abstract
With the push toward 32 nm half-pitch, OPC models will need to account for a wider range of sources of imaging
variability in order to meet the CD budget requirements. The effects of chromatic aberration on imaging have been a
recent area of interest but little work has been done to include this effect in OPC models. Chromatic aberrations in the
optical system give rise to a blurring of the intensity distribution in the imaging plane even for highly line-narrowed
immersion laser sources. The resulting focus blur can introduce a feature-dependent CD bias of several nanometers.
Usually, the empirical components of the resist model can reduce or completely compensate for this imaging effect.
However, it is not well known if including a more physical image model over a large range of laser bandwidth conditions
will improve the OPC accuracy or process-variability robustness.
This study demonstrates the correlation of physical laser bandwidth perturbations with perturbations of the optical model
in Calibre. The laser bandwidth is experimentally perturbed to obtain several sets of CD measurements for different
bandwidths. These are then used in model calibration with the corresponding perturbation in the optical model. Finally,
we quantify the improvement in model accuracy obtained when including an input of laser bandwidth.
Control and reduction of immersion defectivity for yield enhancement at high volume production
Show abstract
Volume device manufacturing using immersion lithography is widely accepted as the solution for patterning IC features
below 40 nm half pitch. In order to ensure high yield and steady productivity tight control of defectivity is essential. A
major source of defects and tool contamination is the particles introduced by incoming wafers. Particles can be
categorized in two groups: particles attached to wafer surface or residues on the wafer edge. Surface or edge peeling of
topcoats can also be a source of particle. Adhesion force between topcoat or topcoat-less (TC-less) resist and wafer is
one of the most important parameter for particle reduction. Peeling test results proved that TC-less resist has better
adhesion performance than topcoat. One of the most commonly used adhesion promoting material is
hexamethyldisilazane (HMDS). Application condition of this material is an important factor in preventing wafer edge
and surface topcoat peeling. Studies have shown lower temperature and longer application of HMDS shows better
adhesion result. Maintaining a clean wafer surface is also a very important factor for particle reduction. Pre-rinse, which
can rinse off particles before exposure, was evaluated and the efficiency was confirmed. Edge particles are more
effectively reduced by pre-rinse, because weakly attached topcoat and wafer edge residues were effectively removed by
pre-rinse. For further particle reduction, edge residue reduction and cut line roughness improvement were evaluated and
their effectiveness was confirmed. Lower cut position achieved improved particle counts on both topcoat and TC-less
resist; more frequent contact between water and cut-line can weaken the adhesion and consequently peel off topcoat or
TC-less resist. Finally the relationship between defectivity and hydrophobicity is analyzed, high Receding Contact Angle
(RCA) showed better defectivity result. Topcoat and TC-less process is compared for each defectivity reduction
methodology and for each category TC-less process always showed lower defectivity level and less sensitivity to process
conditions, indicating that TC-less process is safer and more robust than topcoat process.
Imaging solutions for the 22nm node using 1.35NA
Show abstract
The practical limit of NA using water as immersion liquid has been reached. As a consequence, the k1 in production for
the coming technology nodes will decrease rapidly, even below k1=0.25.This means that new imaging solutions are
required. Double patterning and spacer techniques in combination with design for manufacturing are developed to
support the 22nm node. However, from an imaging point of view the main challenge is to extend and improve single
exposures at k1 of 0.26 to 0.31. In this paper we will present ingredients to support single exposure (as a part of a double
patterning solution).
The following ingredients to extend single exposure are presented in this paper: 1) Extreme Dipole illumination (pole
width = 20° and ring width = 0.08σ) to demonstrate tight CD control of 1.5nm across the wafer for a flash gate layer with
a half pitch of 38nm. 2) The benefits of complex freeform illumination pupils for process window, pattern fidelity and
MEEF using a DRAM active area pattern, and 3) the advantage of TE polarization for rotated structures while
maintaining intensity in preferred polarization state.
Speckle in optical lithography and the influence on line width roughness
Show abstract
In recent years the topic of speckle in optical projection microlithography received increasing interest because of its
potential contribution to line width roughness (LWR). Speckle is a light interference effect that causes the dose delivered
to the reticle to be not uniform. This will cause a line width variation of the patterns imaged in the resist. The contrast of
the speckle pattern is shown to be caused by a combination of temporal and spatial coherence effects of the light. The
temporal part, determined by the bandwidth of the laser light and the duration of the laser pulse, is found to be the
dominant contributor to speckle in today's ArF optical lithography. The spatial distribution of the speckle pattern
depends on the intensity distribution of the light in the pupil. Consequently the spatial frequencies of the LWR induced
by speckle will depend on the illumination condition, which is confirmed experimentally by exposing wafers with
different amounts of speckle contrast. The experiments demonstrate that the amplitude of the LWR induced by speckle is
consistent with theory and simulations. Its amplitude is small compared to other sources of LWR, but it is clearly present
and should not be ignored when extending ArF optical lithography into future technology nodes.
Enabling the lithography roadmap: an immersion tool based on a novel stage positioning system
Show abstract
The lithography roadmap demands overlay reduction along with increased productivity. New applications are proposed
as lithography solution for the 32-nm node and possibly beyond. Most of them require very tight overlay and multiple
exposures. Major contributors in the overlay budget are coming from the exposure system, like thermal stability, lens
aberrations stability, stage positioning and alignment. An additional complexity is the interaction with the actual process
and the pattern on the reticle. To keep the lithography roadmap affordable, the cost per wafer needs to be tamed by
boosting the productivity of the exposure tool.
To enable new applications in a production environment a new generation lithographic exposure tools was developed,
with improved overlay and increased productivity. The optical column contains an improved 1.35 NA immersion lens.
Compared to the former generation the combination of overlay and productivity requirements are met by a high
acceleration wafer stage along with a new stage position measurement system, introducing new technologies paving the
way to meet the future roadmap requirements. The increased disturbances caused by the higher accelerations are
countered by a short-beam interferometer system thus ensuring optimal positioning performance. Further productivity
enhancements are reached by reducing non-exposure time.
The latest performance results will be presented; this will include overlay results as well as other critical system
performance data.
Poster Session: Double Patterning
A CDU comparison of double patterning process options using Monte Carlo simulation
Show abstract
Determination of the optimal double patterning scheme depends on cost, integration complexity, and performance. This
paper will compare the overall CDU performance of litho-etch-litho-etch (LELE) versus a spacer approach. The authors
use Monte Carlo simulation as a way to rigorously account for the effect of each contributor to the overall CD variation
of the double patterning process. Monte Carlo simulation has been applied to determine CD variations in previous
studies1-2, but this paper will extend the methodology into double patterning using a calibrated resist model with
topography.
Exploration of linear and non-linear double exposure techniques by simulation
Show abstract
In this work, a framework for the assessment of different double exposure techniques is laid out. Both the simulation environment and the utilized models, derived from well-established resist models, are discussed. Numerous simulation results are evaluated to investigate strengths and weaknesses of different double exposure approaches. Non-linear superposition techniques are examined in respect of their process performance for both standard and sub 0.25 k1 values. In addition to a study of these effects in the scope of basic layouts, an application to interference-assisted lithography (IAL) is proposed and discussed.
Integration of dry etching steps for double patterning and spacer patterning processes
Show abstract
Double patterning (DP) is today the accepted solution to extend immersion lithography to the 32 nm node and beyond.
Pitch splitting process and spacer process have been developed at CEA-LETI-Minatec. This paper will focus on the
optimization of dry etching process to achieve these two patterning techniques. For each approach, we first discuss the
choices of the starting integration flows based on the requirements to etch the final devices. Then, we develop how the
etching steps were optimized to get a good step by step CD control for 45nm/45nm features.
Analysis of higher order pitch division for sub-32nm lithography
Show abstract
The three knobs of optical lithography, namely process factor k1, wavelength (λ) and numerical aperture (NA) have been
constantly pushed to print smaller features. To get an equivalent k1 value below the fundamental limit of 0.25, double
patterning (DP) has recently emerged as a viable solution for the 32nm lithography node. Various DP techniques exist
such as litho-etch-litho-etch (LELE), litho-freeze-litho-freeze (LFLF) and self-aligned sidewall spacer. In this paper, the
potential of higher order pitch division (pitch/N, N>2) for sub-32nm lithography is analyzed. Compared to double
patterning, higher order pitch division lithography offers higher resolution but also faces significant challenges such as
added cost and tighter process control. Several process schemes are proposed and compared in terms of complexity,
susceptibility to alignment error and CD uniformity control. It is shown that the overlay budget does not necessarily
decrease compared to double patterning. The main challenge in higher order pitch division comes from controlling the
key processing steps that directly form lines or spaces. In addition, line CD control is easier than space (gap) control in
all four "positive-tone" processes studied, similar to the double patterning case. Among the proposed processes, a
freezing assisted double spacer (FADS) process that is simpler than the common sidewall spacer approach shows
promise for balanced process control.
Poster Session: High Index Lithography
32 nm half pitch formation with high numerical aperture single exposure
Show abstract
According to the ITRS roadmap, DRAM half pitch (hp) will reach to 32 and 20 nm in 2012 and 2017
respectively. However, it is difficult to make sub-40 nm node by single exposure technology with currently
available 1.35 numerical aperture (NA) ArF immersion lithography. Although it is expected to enable 32 nm hp
with either double patterning technology or extreme ultra-violet lithography, there are many problems to be
solved with cost reduction. Thus, the study of high-index fluid immersion technology should be pursued
simultaneously. ArF water immersion systems with 1.35 NA have already introduced for 40 nm hp production.
ArF immersion lithography using high-index materials is being researched for the next generation lithography.
Currently, many studies are undergoing in order to increase NA with higher index fluid and lens in immersion
technology. The combination of LuAG (n=2.14) and third-generation fluid could be used to make 1.55 NA. This
combination with 0.25 k1, 32 nm hp can be obtained by single exposure technology. In order to check the
realization of this process and to check the possible process hurdles for this high NA single exposure technology,
32 nm hp with 1:1 line and space patterning is tried. Various illumination conditions are tried to make 1:1 32 nm
hp and the exposure and develop conditions are varied to check whether this single exposure can give
processible window. As a result, 32 nm hp can be obtained by single exposure technology with 1.55 NA.
High index 193 nm immersion lithography: the beginning or the end of the road
Show abstract
For several years, SEMATECH has invested significant effort into extending 193 nm immersion lithography by
developing a set of high index materials. For high index immersion lithography (HIL) to enable 1.70NA imaging, a
high index lens element with an absorbance < 0.005/cm, a fluid with an index of ≥ 1.80, and a resist with an index >1.9
are needed. This paper reviews the success or failure of various HIL components and presents the top final material
prospects and properties in each category.
Since this abstract was submitted, the industry has decided to cease any effort in HIL, not because of fundamental
showstoppers but because of timing. This choice was made even though the only currently available technology the can
enable 32 nm and 22 nm manufacturing is double patterning. This may represent a paradigm shift for the semiconductor
industry and lithography. It may very well be that using lithography as the main driver for scaling is now past. Due to
economic forces in the industry, opportunity costs will force performance scaling using alternative technology.
Birefringence issues with uniaxial crystals as last lens elements for high-index immersion lithography
Show abstract
We discuss the birefringence issues associated with use of crystalline sapphire, with uniaxial crystal structure, as a last
lens element for high-index 193 nm immersion lithography. Sapphire is a credible high-index lens material candidate
because with appropriate orientation and TE polarization the ordinary ray exhibits the required isotropic optical
properties. Also, its material properties may give it higher potential to meet the stringent optical requirements compared
to the potential of the principal candidate materials, cubic-symmetry LuAG and ceramic spinel. The TE polarization
restriction is required anyway for hyper-NA imaging, due to TM-polarization contrast degradation effects. Further, the
high uniaxial-structure birefringence of sapphire may offer the advantage that any residual TM polarization results in a
relatively-uniform flare instead of contrast degradation. One issue with this concept is that spatial-dispersion-induced
effects should cause some index anisotropy of the ordinary rays, in a way similar to the intrinsic birefringence (IBR)
effects in cubic crystals, except that there is no ray splitting. We present the theory of this effect for the trigonal crystal
structure of sapphire and discuss its implications for lithography optics. For this material the spatial-dispersion-induced
effects are characterized by eight material parameters, of which three contribute to index anisotropy of the ordinary
rays. Only one gives rise to azimuthal distortions, and may present challenges for correction. To assess the
consequences of using sapphire as a last element, neglecting any IBR effects, we use lithography simulations to
characterize the lithographic performance for a 1.7 NA design, and compare to that for LuAG.
Poster Session: Masks
Multiple layer CD control treatment
Show abstract
Tight control of intra-field CD variations becomes more and more important as the pattern sizes on wafer shrink. For
intra-field CD uniformity improvement several techniques have been developed. A very effective method is changing the
local mask blank transmittance according to measured Intra Field (IF) CD variations using Pixer's CDCTM technique.
This process is irreversible. For various practical reasons it would be helpful to have the opportunity for a second or
more mask blank treatments. A first application could be to improve an unsatisfying CDU post first treatment. A second
application can be the switch of the mask usage to another tool group. Furthermore, the opportunity to use multiple CDC
treatments would allow the splitting of the correction process for the mask and the tool separately, whereas in a first
correction only the mask CDU errors will be corrected and after the mask is supplied to the customer another correction
may be required to reduce the exposure tool contributions to the CDU budget.
Therefore the intention of the paper is to evaluate the opportunities of a Multiple CDC (MCDC) correction process, to
determine its accuracy and the corresponding limits.
To do this two CDC tool projection lenses have been characterized, which have been developed for different focus
positions. We will characterize their transmittance transfer performance, stability and sensitivities. The required multiple
layer distances will be determined. The linearity of the multiple CDC treatment will be analyzed using AIMSTM
measurements and wafer prints. We will present results of successful multiple CDC corrections for production masks.
Smart data filtering for enhancement of model accuracy
Show abstract
As integrated circuit technology advances and features shrink, the scale of critical dimension (CD) variations induced by
lithography effects become comparable with the critical dimension of the design itself. At the same time, each
technology node requires tighter margins for errors introduced in the lithography process. Optical and process models --
the black boxes that simulate the pattern transfer onto silicon -- are becoming more and more concerned with those
different process errors. As a consequence, an optical proximity correction (OPC) model consists mainly of two parts; a
physical part dealing with the physics of light and its behavior through the lithographical patterning process, and an
empirical part to account for any process errors that might be introduced between writing the mask and sampling
measurements of patterns on wafer. Understanding how such errors can affect a model's stability and predictability, and
taking such errors into consideration while building a model, could actually help convergence, stability, and
predictability of the model when it comes to design patterns other than those used during model calibration and
verification. This paper explores one method to quickly enhance model accuracy and stability.
Analysis and modeling of photomask edge effects for 3D geometries and the effect on process window
Show abstract
Simulation was used to explore boundary layer models for 1D and 2D patterns that would be appropriate for
fast CAD modeling of physical effects during design. FDTD simulation was used to compare rigorous thick mask
modeling to a thin mask approximation (TMA). When features are large, edges can be viewed as independent and
modeled as separate from one another, but for small mask features, edges experience cross-talk. For attenuating
phase-shift masks, interaction distances as large as 150nm were observed. Polarization effects are important
for accurate EMF models. Due to polarization effects, the edge perturbations in line ends become different
compared to a perpendicular edge. For a mask designed to be real, the 90o transmission created at edges
produces an asymmetry through focus, which is also polarization dependent. Thick mask fields are calculated
using TEMPEST and Panoramic Technologies software. Fields are then analyzed in the near field and on wafer
CDs to examine deviations from TMA.
Poster Session: Optical Proximity Corrections
Transformation procedure from sparse OPC model to grid-based model
Show abstract
Now it comes to the sub 65nm technology node, which should be the first generation of the immersion microlithography.
And the brand-new lithography tool makes many optical effects, which can be ignored at 90nm and
65nm nodes, now have significant impact on the pattern transmission process from design to silicon. And this will
result in big challenge to the optical proximity effect correction. For, with the shrinkage of the critical dimension of
IC design, the error budget for the CD variation becomes much tighter. And to meet the requirement of the tight CD
control, more optical effects need to be taken into account while using some calibrated process model to represent the
real lithography process. In the whole industry, it is thought that, instead of sparse optical proximity correction, grid
based model for optical proximity correction should be started to employ for sub 65nm technology node. Considering
that sparse model and grid-based model adopting different algorithm, OPC engineers sometimes maybe need to do
some translation work between the two kinds of model forms. This paper will demonstrate a procedure for the model
form translation purpose.
Image-assistant OPC model calibration on 65nm node contact layer
Show abstract
This work compared the CD-based and image-assistant approaches for calibrating the OPC models. OPC models were
first developed for 65nm-node memory contact layer and calibrated by contact test patterns with various ellipticities. The
image-assistant model is a hybrid one calibrated by SEM contours and 1D measurement results, while the CD-based
model calibration uses 1D measurement results as the sole data source. The fitting errors, model prediction ability and
OPCed results were compared between these two models. Besides, the challenges on calibrating the edge-detection
algorithm of the CD SEM images to the extracted contours of OPC tool were also discussed. Finally, the layouts
corrected by CD-based and image-assistant models were written on a test mask for wafer-level comparison.
The results displayed that the CD-based model showed smaller error on fitting and interpolation, but image-assistant
model got improvement on extrapolation prediction of array-edge contact, unknown contact pattern and long contacts.
The wafer-level comparison also revealed the image-assistant model outperformed to the CD-based model by smaller
correction error on unexpected patterns.
Design driven test patterns for OPC models calibration
Show abstract
In the modern photolithography process for manufacturing integrated circuits, geometry dimensions need to
be realized on silicon which are much smaller than the exposure wavelength. Thus Resolution
Enhancement Techniques have an indispensable role towards the implementation of a successful
technology process node. Finding an appropriate RET recipe, that answers the needs of a certain
fabrication process, usually involves intensive computational simulations. These simulations have to reflect
how different elements in the lithography process under study will behave. In order to achieve this,
accurate models are needed that truly represent the transmission of patterns from mask to silicon.
A common practice in calibrating lithography models is to collect data for the dimensions of some test
structures created on the exposure mask along with the corresponding dimensions of these test structures on
silicon after exposure. This data is used to tune the models for good predictions.
The models will be guaranteed to accurately predict the test structures that has been used in its tuning.
However, real designs might have a much greater variety of structures that might not have been included in
the test structures.
This paper explores a method for compiling the test structures to be used in the model calibration process
using design layouts as an input. The method relies on reducing structures in the design layout to the
essential unique structure from the lithography models point of view, and thus ensuring that the test
structures represent what the model would actually have to predict during the simulations.
Model-based retarget for 45nm node and beyond
Show abstract
In the past several years, DFM (design for manufacturability) is widely used in semiconductor process. DFM is
to make layout design optimized for manufacturability's sake. Lithography friendly design (LFD) is one branch of DFM.
To enhance process margin of photolithography, layout designers typically modify their layout design with the
application of DFM or LFD tools. Despites those application, it is still not enough to realize enough process window as
technology node goes to beyond 45nm. For these reasons, OPC (Optical proximity correction) engineers apply
additional layout treatment prior to applying OPC. That is called as table-driven retarget, which is typically conducted by
rule-based table. Similar to rule-based OPC, table-driven retarget also has limitations in its application.
In this paper, we presented a model-based retargeting method to overcome the limitation of table-driven retarget.
Once the criteria of process window has been set, we let OPC tool simulate the process window of each layout of design
firstly. Then, if the output value of the simulated result cannot meet the preset criteria, OPC tool resizes the layout
dimension automatically. OPC tool will do retarget-OPC-retarget iterations until process windows of all of designs
become within the criteria. After all, the model-based retarget can guarantee accurate retarget and avoid over or under
retarget in order to improve process window of full chip design.
Pattern matching assisted modeling test pattern generation
Show abstract
Generating test patterns with sufficient parameter space coverage has always been one of the critical steps towards
building good OPC models. The advancement in technology node requires continues updates to OPC modeling test
patterns. The traditional approach relies heavily on experiences gathered from older technology nodes. It often requires
rounds of costly test tape out. Here we propose an automated flow for test pattern generation utilizing a fast full chip
pattern matching algorithm. We describe the implementation of the flow. We also present experimental results and
discuss the benefit and challenges of the proposed flow.
Model based mask process correction and verification for advanced process nodes
Show abstract
The extension of optical lithography at 193nm wavelength to the 32nm node and beyond drives advanced resolution
enhancement techniques that impose even tighter tolerance requirements on wafer lithography and etch as well as on
mask manufacturing. The presence of residual errors in photomasks and the limitations of capturing those in process
models for the wafer lithography have triggered development work for separately describing and correcting mask
manufacturing effects. Long range effects - uniformity and pattern loading driven - and short range effects - proximity
and linearity - contribute to the observed signatures. The dominating source of the short range errors is the etch process
and hence it was captured with a variable etch bias model in the past [1]. The paper will discuss limitations and possible
extensions to the approach for improved accuracy. The insertion of mask process correction into a post tapeout flow
imposes strict requirements for runtime and data integrity. The paper describes a comprehensive approach for mask
process correction including calibration and model building, model verification, mask data correction and mask data
verification. Experimental data on runtime performance is presented.
Flow scenarios as well as other applications of mask process correction for gaining operational efficiency in both tapeout
and mask manufacturing are discussed.
Novel OPC method to create sub 45nm contact hole using design based metrology
Show abstract
During the past few years, new technology brought about new problems we face today due to
shrinkage of the feature size. Some of the problems such as Mask Error Enhancement Factor (MEEF), overlay
control, and so on are crucial because large MEEF can make it difficult to satisfy CD target, and bring about
large CD variation. Moreover, it can also lead to degraded CD uniformity which would have an undesired
influence on device properties. Recently, 2-D random contact hole is getting crucial because it normally has
very large MEEF and cause asymmetric proximity effect which can cause large CD variation, and
misalignment of layer-to-layer. In other words, the method of optical proximity correction and building
accurate OPC model for 2-D random contact hole pattern could be key factor obtaining better CD uniformity
with enhanced overlay margin. Furthermore, in order to get very tangible performance, design based
metrology system (DBM) is used to evaluate process performance. Design based metrology systems are able
to extract information of whole chip CD variation. On top of that, OPC abnormality can be identified and
design feedback can be also disclosed.
In this paper, we will investigate novel method for sub 45nm 2-D random contact hole printing.
First, optical proximity effect (OPE) for two dimensional layout will be investigated. Second, the results of
Variable Threshold Modeling (VTM) for various slit contact hole patterns will be analyzed. Third, model
based verification will be done and analyzed through full-chip before creating full-chip mask. Finally, sub
45nm 2-D random contact hole printing performance will be presented by DBM.
Abbe-PCA (Abbe-Hopkins): microlithography aerial image analytical compact kernel generation based on principle component analysis
Show abstract
In the year of 1873, Professor E. Abbe, cooperating
with Carl Zeiss Inc, summarized his
discovery of the microscope imaging principle
which states that the final image is the superposition
result of all the diffracted images entering
at different angles oblique to the pupil.
This discovery forms the foundation analytical
methods to analyze optics resolving power.
Later, in 1951, the Hopkin's equations, derived
by Professor H. H Hopkins, clarified the correlation
relationship in the image from both
spatial and frequency domain. Based on Hopkin's
theory, many microlithography aerial image
simulation tools have been developed. In
this paper, we claimed that by combing Abbe's
theory with the Principle Component Analysis
(PCA) method, which is specific to the
covariance eigen-decomposition method rather
than the SVD (Singular Value Decomposition)
method, we can achieve an extremely efficient
computational algorithm to generate the essential
kernels for aerial image simulation. The
major reason for this speed up is from our discovery
that the covariance matrix of Abbe's
kernels, which is in the dimension of number
of discretized condenser sources, can be easily
constructed analytically as well as decomposed
to a basis set. As a result, an analytical
form of compact decorrelated Abbe's kernels can be obtained even without explicit formation
of the kernel images. Furthermore, the
asymptotic eigenvalues and eigenvectors of the
covariance matrix can also be obtained without
much computational effort. This discovery
also creates a new way to analyze the relationship
between sources and final images which
can be easily utilized to optimize source shape
for lithography process development. Several
imaging phenomenon have been readily explained
by this method. Extensive experimental
results demonstrate that Abbe-PCA is 10X-
40X faster than the state-of-the-art algorithm
Abbe-SVD.
Automatic SRAF size optimization during OPC
Show abstract
Sub-resolution assist features (SRAFs) are a common addition to low-k1 masks to improve process window for isolated
features. Traditional SRAF placement, which has been widely adopted by the industry, is governed by generation of
rules which have been experimentally derived based on exposure and measurement of test patterns. The placement rules
must generate SRAFs large enough to improve the process window, but small enough not to print at any point within that
process window. This has resulted in tremendous challenges to meet the cost and process window requirements for the
advanced technology nodes. Specifically, in the logic products, due to the complex two-dimensional patterns, the
placement rules will be quite challenging in order to ensure maximum sizing and no printing. SRAF generation is also
plagued by over clean-up due to mask rule checks (MRC) specified. The challenge is to derive the best rules which
generate SRAFs without printing through the process window.
This paper will explore the possibility of an alternate SRAF placement methodology where the SRAF placement rules
can be greatly simplified, and SRAF printability through the required process window conditions will automatically be
accounted for during a subsequent Optical Proximity Correction (OPC) step. This methodology has the advantages of
simplifying the placement rules while simultaneously ensuring maximum possible SRAF size with no printing within the
process window. The SRAF size optimization is performed concurrently with OPC thereby saving valuable time on
trying to optimize the rule deck. In this method the side-lobes are automatically suppressed well under the imaging
threshold. Experimental verification of the SRAF dependence on its sizing and placement along with printability and
main-feature process window will be demonstrated.
OPC segmentation: dilemma between degree-of-freedom and stability with some relieves
Show abstract
It is believed that smaller correction segments could achieve better pattern fidelity, however, some unstable OPC results
which are beyond the capability of common OPC correction schemes were found once the segment length is less than a
certain threshold. The dilemma between offering more degree-of-freedom by decreasing the correction segment length at
the cost of longer correction time and the instability induced by the reduced segment length challenges every OPC
engineer.
In this paper, 2 indices are introduced; the segmentation index is proposed to determine a reasonable minimum segment
length while the stability index can be used to examine whether the correction system is a stiff convergence problem. A
compromised correction algorithm is also proposed to consider the OPC accuracy, stability and runtime simultaneously.
The correction results and the runtime are analyzed.
Efficient hardware usage in the mask tapeout flow
Show abstract
With each new technology node there is an increase in the number of layers requiring Optical Proximity Correction
(OPC) and verification. This increases the time spent on the mask tapeout flow which is already a lengthy portion of the
production flow. New technology nodes not only have additional layers that require OPC but most critical layers also
end up with more complex OPC requirements relative to previous generations slowing the tapeout flow even further. In
an effort to maintain acceptable turnaround time (TAT) more hardware resources are added at each node and electronic
design automation (EDA) suppliers are pushed to improve the software performance. The more we can parallelize
operations within the tapeout flow the more efficient we can be with the use of the CPU resources and drive down the
overall TAT. Traditional flows go through several cycles where data is broken up into templates, the templates are
distributed to compute farms for processing, pieced back together, and sometimes written to disk before starting the next
operation in the tapeout flow. During each of these cycles there are ramp up, ramp down, and input/output (I/O) times
that are incurred affecting the efficient use of hardware resources. This paper will explore the advantages of pipelining
the templates from one operation to the next in order to minimize these effects.
Pre-OPC layout decomposition for improved image fidelity
Show abstract
In microelectronics manufacturing, photolithography is the art of transferring pattern shapes printed on a mask to silicon
wafers by the use of special imaging systems. These imaging systems stopped reducing exposure wavelength at 193nm.
However, the industry demand for tighter design shapes and smaller structures on wafer has not stopped. To overcome
some of the restrictions associated with the photographic process, new methods for Resolution Enhancement Techniques
(RET) are being constantly explored and applied. An essential step in any RET method is Optical Proximity Correction
(OPC). In this process the edges of the target desired shapes are manipulated to compensate for light diffraction effects
and result in shapes on wafer as close as possible to the desired shapes. Manipulation of the shapes is always restricted
by Mask Rules Checks (MRCs). The MRCs are the rules that assure that the pattern coming out of OPC can be printed
on the mask without any catastrophic faults. Essential as they are, MRCs also place constrains on the solutions explored
by the OPC algorithms.
In this paper, an automated algorithm has been implemented to overcome MRC limitations to RET by decomposing the
original layout at the places where regular RET hit the MRC during OPC.This algorithm has been applied to test cases
where simulation results showed much better printability than the normal conventional solutions. This solution has also
been tested and verified on silicon.
Poster Session: Process
Next generation siloxane-based Bottom Anti-Reflective Coating (BARC) formulations with selective strip rates and required optical properties
Show abstract
Bottom Anti Reflective Coating (BARC) materials are generally used to minimize reflection of incident light from the
substrate (Rsub). As IC manufactures move to high NA systems to meet the patterning requirements for next generation
technology as well as the use of new lower dielectric constant materials in the back-end-of-line dielectric, the
requirements for developing BARC materials with new properties such as faster strip rate and properly tuned optical
properties (n = refractive index and k=extinction coefficient) are essential. Some photoresist patterning schemes may
also require a dual BARC system such as tri-layer patterning (TLP), which is undergoing extensive evaluation in
academia and industries. This work focuses on Honeywell's next generation DUO193 material (DUO193FS), which is a
siloxane-based polymer with an organic 193 nm chromophore attached to it. The effects of additives for adjusting strip
rate in a wet chemical stripper, while maintaining chemical resistance to a photoresist developer, 2.38% TMAH in water
are discussed. Different spectroscopic studies are performed to elucidate the mechanism of faster strip rate. Solvation of
silanol groups and their orientation in the presence of additives are found to be secondary mechanism. The primary
reason for enhanced strip rate is attributed to the addition of additives A and B, which lower bulk density of the solid
film. DUO193FS can be stand alone BARC or used with another BARC as part of a dual BARC system to further
minimize Rsub, maintaining resistance to 2.38% TMAH, planarizing any underlying topography and keeping the final
film strip rate high.
Thin hardmask patterning stacks for the 22-nm node
Show abstract
This paper presents robust trilayer lithography technology for cutting-edge IC fabrication and double-patterning
applications. The goal is to reduce the thickness of a silicon hardmask so that the minimum thickness of the
photoresist is not limited by the etch budget and can be optimized for lithography performance. Successful results
of pattern etching through a 300-nm carbon layer are presented to prove that a 13.5-nm silicon hardmask is thick
enough to transfer the line pattern. Another highlight of this work is the use of a simulation tool to design the stack
so that UV light is concentrated at the bottom of the trenches. This design helps to clear the resist in the trenches
and prevent resist top loss. An experiment was designed to validate the assumption with 45-nm dense lines at
various exposure doses, using an Exitech MS-193i immersion microstepper (NA = 1.3) at the SEMATECH Resist
Test Center. Results show that such a stack design obtains very wide CD processing window and is robust for 1:3
line patterning at the diffraction limit, as well as for patterning small contact holes.
Arbitrary three-dimensional micro-fabrication by polymer grayscale lithography
Show abstract
We report on the continuing development of a grayscale lithography technique based on the use of a polymeric grayscale
photomask. Arbitrary three-dimensional (3D) microstructures can be realized in positive and negative photoresist
materials by the use of the polymeric grayscale photomask with standard ultra-violet (UV) lithography. The fabrication
of such 3D structures depends on the differential absorption of in photo-absorbing material. The photomask is made of
patterned polydimethylsiloxane (PDMS) polymer doped with a UV absorbing laser dye. The PDMS photomask contains
micro-patterns made by micro-molding the PDMS on a complementary silicon master mold. By adjusting the thickness
of the patterns on the polymer photomask, the dopant dye concentration in the photomask and UV exposure dose, a
multitude of unique 3D microstructures can be fabricated on the substrate with desired geometries and dimensions.
While the feasibility of grayscale lithography with such a polymeric mask has been reported by us earlier, this paper
describes the fabrication of master mold and polymeric grayscale photomask.
0.13µm BiCMOS emitter window lithography with KrF scanners
Show abstract
Defining the emitter window is one of the most critical lithographic steps in a BiCMOS process. Step-and-scan exposure
tools are typically the largest component of fixed capital expense so the industry is constantly trying to push the
resolution limit without purchasing new equipment. As the industry extends KrF scanner to 0.13μm BiCMOS process,
the lithography process window of shallow trenches patterns which are typical for emitter windows will be challenged.
Generally speaking, printing these patterns with conventional single exposure methods will suffer from lack of sufficient
process window and severe line-end shortening. In this paper, we present a method that uses KrF scanners and several
resolution enhancement techniques including attenuated phase shift masks (att-PSM), model-based optical proximity
correction (MbOPC), and a multi-focal exposure technique, to improve the process window of 0.13μm emitter window
features.
Characterization results are shown for the process window, side lobe printability margin, and line-end shortening.
Comparisons are made to a traditional exposure method. The results demonstrate a significant increase in depth of focus
as well as improvements in line-end shortening and intra-wafer CD uniformity.
Patterning of SU-8 resist with digital micromirror device (DMD) maskless lithography
Show abstract
Digital micromirror device (DMD) based maskless lithography has a number of advantages including process
flexibility, no physical photomask requirement, fast turnaround time, cost effectiveness. It can be particularly
useful in the development stage of microfluidic and bioMEMS applications. In this report, we describe the initial
results of thick resist SU-8 patterning, soft lithography with polydimethylsiloxane (PDMS) and lift-off of Cr
features using a modified DMD maskless system. Exposures of various patterns and microfluidic channels reveal
that the system is well capable of printing 60 μm thick resist at a resolution as small as a single pixel (less
than 13 μm) with an aspect ratio about 5:1. Both negatively and positively tapered sidewalls are achieved by
projecting the UV light from front side of the SU-8 coated Si wafer and from the back side of the coated glass,
respectively. The positive sidewall has an angle 88o which is ideal to serve as a mold for subsequent PDMS
soft lithography. Both SU-8 and PDMS microfluidic devices for biomolecular synthesis were fabricated with this
maskless system. In addition, a lift-off process was also developed with the intention to create built-in metal
features such as electrodes and heaters.
Poster Session: Process Control
Process transfer strategies between ASML immersion scanners
Show abstract
A top challenge for Photolithographers during a process transfer involving multiple-generation scanners is tool
matching. In a more general sense, the task is to ensure that the wafer printing results in the receiving fab will match or
even exceed those of the originating fab. In this paper we report on two strategies that we developed to perform a photo
process transfer that is tailored to the scanner's capabilities. The first strategy presented describes a method to match the
CD performance of the product features on the transferred scanner. A second strategy is then presented which considers
also the down-stream process tools and seeks to optimize the process for yield. Results presented include: ASML
TWINSCANTM XT:1700i and XT:1900i scanners 1D printing results from a line-space test reticle, parametric sensitivity
calculations for the two scanners on 1D patterns, simulation predictions for a process-optimized scanner-matching
procedure, and final wafer results on 2D production patterns. Effectiveness of the optimization strategies was then
concluded.
32nm node device laser-bandwidth OPE sensitivity and process matching
Show abstract
For 32 nm Node Logic Device, we studied the effect of laser bandwidth variation on Optical Proximity Effect (OPE) by
investigating through-pitch critical dimension (CD) performance. Our investigation evaluated CD performance with and
without the application of Sub-resolution Assist Features (SRAF). These results enabled us to determine the Iso-Dense
Bias (IDB), and sensitivity to laser bandwidth, for both SRAF and no-SRAF cases, as well as the impact on Process
Window. From the IDB results we present the required laser bandwidth stability in order to maintain OPE variation
within CD Budget tolerances. We also introduce OPE matching results between different generation Immersion
Lithography exposure tools evaluated for 45nm Node Logic Device.
New approach to determine best beam focus
Show abstract
As patterning technology advances beyond 45-nm half-pitch, the process window shrinks dramatically even with
advanced resolution enhancement techniques. Beamfocus represents one of the process parameters that has a significant
contribution to the overall critical feature dimension error budget. In building an optical model for proximity correction,
the final model quality strongly depends on matching the focus used in the simulation to the experimental focus
conditions. In this paper, we present a new method to determine the best beamfocus and verify its accuracy using actual
test pattern measurements.
High-order distortion effects induced by extreme off-axis illuminations at hyper NA lithography
Show abstract
Aggressive pitch requirements for line/space pattern devices require the usage of extreme off-axis illumination schemes
to enhance the resolution of the exposure tools. These illumination schemes stress the quality of the optics because of the
anisotropy of the optical paths through the lens. Moreover, the marginalities on the patterning are dramatically enhanced
if two or more illumination modes are requested in the lithography process.
The effects on overlay between double exposure layers exposed with different illumination settings, with one being an
extreme illumination setting, will be discussed and two approaches will be addressed to compensate the resulting overlay
fingerprint.
The first approach optimizes the lens setup by means of a dedicated scanner option to minimize the lens effects on
overlay and reduce the distortion for each layer: in this case the simulation time and the impact on other imaging
parameters will be carefully evaluated.
The second methodology corrects the induced misalignment by a high order modelling compensation. This approach
requests the insertion of a suitable set of overlay measurement targets into the product frame to appropriately fit the
distortion matching of the two layers.
Poster Session: Resolution Enhancement
Line end shortening and corner rounding for novel off-axis illumination source shapes
Show abstract
Previous study has shown that off-axis illumination (OAI) which employs duplicate conventional source shape such as
double dipole, double annular or double quadrupole can reduce the effect of line width fluctuation and process window
degradation at the forbidden pitch. In this paper, influence of the new OAI source shape on line end shortening and
corner rounding effect is studied. Despite the advantage of reduced line width fluctuation, the proximity effect at line
ends and corners for new source shapes need to be examined because both lateral and longitudinal pattern fidelity is
important in actual implementation. Simulation study will be used for the study of line end shortening and corner
rounding effect using new source shapes and the results will be compared with those resulted from annular illumination.
Line end structures such as end to end, staggered, and T-shaped patterns are used for line end shortening study. For
corner rounding, L-shaped and U-shaped structure are used. The pattern density and line end separation of feature will be
varied to determine the important factors that cause image distortion. Results has shown that new source shapes have
similar line end shortening and corner rounding characteristic with the conventional one. Besides, the variation of new
source shapes for different pattern density and line end separation is relatively smaller compared with conventional OAI
source shapes.
The analysis of polarization characteristics on 40nm memory devices
Show abstract
Hyper NA system has been introduced to develop sub-60nm node memory devices. Especially memory
industries including DRAM and NAND Flash business have driven much finer technology to improve
productivity. Polarization at hyper NA has been well known as important optical technology to enhance
imaging performance and also achieve very low k1 process. The source polarization on dense structure has
been used as one of the major RET techniques. The process capabilities of various layers under specific
illumination and polarization have been explored.
In this study, polarization characteristic on 40nm memory device will be analyzed. Especially, TE
(Transverse Electric) polarization and linear X-Y polarization on hyper NA ArF system will be compared and
investigated. First, IPS (Intensity in Preferred State) value will be measured with PMM (Polarization
Metrology Module) to confirm polarization characteristic of each machine before simulation. Next simulation
will be done to estimate the CD variation impact of each polarization to different illumination. Third, various
line and space pattern of DRAM and Flash device will be analyzed under different polarized condition to see
the effect of polarization on CD of actual wafer. Finally, conclusion will be made for this experiment and
future work will be discussed.
In this paper, the behavior of 40nm node memory devices with two types of polarization is presented and
the guidelines for polarization control is discussed based on the patterning performances.
22 nm technology node active layer patterning for planar transistor devices
Show abstract
As the semiconductor device size shrinks without concomitant increase of the numerical aperture (NA=1.35) or
index of the immersion fluid from 32 nm technology node, 22 nm patterning technology presents challenges in
resolution as well as process window. Therefore, aggressive Resolution Enhancement Technique (RET), Design for
Manufacturability (DFM) and layer specific lithographic process development are strongly required. In order to achieve
successful patterning, co-optimization of the design, RET and lithographic process becomes essential at the 22 nm
technology node.
In this paper, we demonstrate the patterning of the active layer for 22 nm planar transistor device and discuss
achievements and challenges in 22 nm lithographic printing. Key issues identified include printing tight pitches and 2-D
features simultaneously without sacrificing the cell size, while maintaining large process window. As the poly-gate pitch
is tightened, the need for improved corner rounding performance is required inorder to ensure proper gate length across
the entire gate width.
Utilizing water immersion at NA=1.2 and 1.35, we will demonstrate patterning of the active layer in a 22 nm
technology node SRAM of a bit-cell having a size of 0.1 μm2 and smaller while providing large process window for
other features across the chip. It is shown that highly layer-specific and design-aware RET and lithographic process
developments are critical for the success of 22 nm node technology.
C-quad polarized illumination for back end thin wire: moving beyond annular illumination regime
Show abstract
The objective of this work is to describe the advances in the use of C-Quad polarized illumination
for densest pitches in back end of line thin wire in 32m technology and outlook for 28 nm
technology with NA of 1.35 on a 193nm wavelength scanner. Through simulation and experiments,
we found that moving from Annular to C-Quad illumination provides improvement in intensity and
contrast. We studied the patterning performance of C-Quad illumination for 1D dense, semi dense,
isolated features with and without polarization. Polarization shows great improvement in contrast
and line edge roughness for dense pattern. Patterning performance of isolated and semi-isolated
features was the same with and without polarization.
Poster Session: Simulation
A proposed image intensity expressing local irradiance
Show abstract
Authors would like to raise a discussion about image intensity for surface exposure, off course, including optical
lithography. As a springboard for the discussion, a novel definition of image "intensity", which expresses local
irradiance associating with optical image, is proposed. An experimental result, which strongly supports the proposed
"intensity", is also obtained.
To describe exposure dose, energy input for unit area with unit of J/m2, is applied as a measure of this amount. A
phrase of "dose-to-clear" is frequently used to show sensitivity of a resist film. In contrast, conventional image intensity
of optical image is defined as a value, which is proportional to volume energy density associating with image. The value
is described with unit of J/m3. In some papers, it is mentioned that number of photochemical reactions in resist film is
proportional to the volume energy density of electromagnetic filed, that is, conventional image intensity. It seems
unclear what physical value is proper measure of surface exposure.
We considered that, in optical lithography, energy flux is proper value to indicate degree of resist exposure from
experience and some former reports. Then, a novel image "intensity", which expresses local irradiance associating with
optical image, is proposed. The proposed image "intensity" is proportional to surface normal component of Poynting
vector.
The divergence of image and resist process metrics
Show abstract
It is common for computational lithography optimization to be performed using the metrics of the
simulated aerial image (AI). Using the AI, the wafer-level CD can be estimated in a number of ways, such
as thresholding with or without convolution of the AI with a point-spread function. The assumption of such
an approach is that the relationship between the AI CD and the resist CD response is linear. However, the
properties of resist reaction-diffusion-development yield a process which is highly non-linear. For example,
it is well-known that different photoresists produce a different lithographic response to the same aerial
image; isofocality, depth-of-focus, exposure latitude, MEF etc. all vary from one resist to another for the
same projection optics and mask. Several publications have demonstrated that a well-calibrated physical
resist model can be extrapolated to accurately predict the CD and profile response of the resist process over
a wide range of optical and process conditions1-4. In this work, the divergence in performance between
resist processes and the projected image-in-the resist is explored through simulation.
Advanced model and fast algorithm for aerial image computation with well controlled accuracy
Show abstract
Modeling of an aerial image in projection lithography was considered as an important part of R&D for a long time. Its
role evolved from an "illustrative" to "predictive" method. In last years it became one of the basic components for
optimization of both layouts (PSM, OPC, DFM) [1-5] and optical systems (scanner NA, shape and size of illuminator etc)
[6-8]. Mathematical models and algorithms for the simulation of aerial images were developed based on either Hopkins's
or Abbe's or coherent decomposition approaches. In this paper, we describe an analytical advancement of Abbe's
method. We present new algorithms for faster simulation of aerial images for integrated circuit patterns. Our approach
can be efficiently used for repetitive simulations of varied optical systems (no need for time-consuming re-generation of
kernel functions or TCC); the accuracy of simulation is well-controlled and does not depend on the problem of "square
grid over circular NA".
A novel fast 3D resist simulation method using Chebyshev expansion
Show abstract
A new simulation method with Chebyshev expansion is proposed to calculate three-dimensional resist profiles in a short
time using Fast Cosine Transform (FCT) algorithm. This method can be applied to the solution of the full 3D model for
OPC and LCC, and it is valid to evaluate the cross-sectional resist shape under the condition where the influence of
reflection wave from the underlayer is significant. We show the results of evaluation with regard to accuracy and
precision, expanding three-dimensional profiles using Chebyshev expansion. In addition, we report the comparison with
numerical experiments.
Modeling mask scattered field at oblique incidence
Show abstract
In optical lithography light diffracted from the mask has been customary assumed to have constant amplitude with the
angle of incidence of the light illuminating the mask. This approximation, known as constant scattering coefficient
approximation, has been successfully used at small NA. As the NA increases to unity and beyond, to cope with the
continuous demand for shrinking integrated circuits device dimensions and densities, the validity of this approximation
becomes questionable. In this paper, we study diffracted field variation with the angle of incidence using physical theory
of diffraction. An asymptotic theory like the physical theory of diffraction allows us to better understand, quantify, and
model using analytical formulae, induced effects of light diffraction from mask at oblique incidence. This paper presents
a semi analytical model that describes diffracted field variation with angle of incidence. The model accuracy is validated
by comparison with rigorous field simulations using Panoramic software.
Partially coherent image computation using elementary functions
Show abstract
It is well-known that calculations of the propagation of partially coherent light, such as those required for
the calculation of two-dimensional image intensities, involve four-dimensional functions. Recently, Wald et
al [Proc SPIE, 59621G, 2005] outlined a method for reducing the four-dimensional problem to a purely twodimensional
one. Instead of an exact modal expansion of the mutual coherence function or cross-spectral density,
an approximate expansion is used, into what we call elementary functions. In this paper, rules of thumb are
developed for fast and efficient computation of the image intensity in a simple partially coherent lithographic
imaging system.
Chemically amplified resist modeling in OPC
Show abstract
The mechanism of chemically amplified resist plays a critical role in the modeling of the latent image. To achieve a
practical model which can fit into the time frame of OPC, some simplifications and assumptions have to be made. We
introduced regression kernels that take into account best exposure focus difference between isotropic pitch, dense, and
line end features for the evaluation of image intensity. It compares the image intensity (signal) over small changes
above and/or below the regressed "nominal" image position, which in principle corresponds to evaluating the intensity
signal at various depths of a fixed resist profile thus can also be regressed for optimization during model development.
Our calibration has shown that the model brought a great improvement in prediction for difficult structures such as dense
features at or near the optical resolution limit and 2-dimensional features, which are the limiter of the overall model
fitting accuracy for 45nm node and below. By replacing other existing techniques, total number of output kernels used
for OPC operation is actually reduced with improvement of model accuracy. This model is proven to be a very effective
yet accurate addition to the current OPC technology.
High-speed microlithography aerial image contour generation without images
Show abstract
To evaluate the quality of microlithography result,
massive aerial images are often generated
for careful inspection using applications such as
OPC LCC (Lithography Compaliance Check).
The number of the pixels used in a 2D aerial
image is in the order of O(n * n), where n is
the image resolution, which means the runtime
scales in a n2 fashion. However, most of
the quality indexes such as CDs or EPE (Edge
Placement Error) can be readily observed using
contours only and the number of pixels in
a specific contour is around O(n) in general.
Therefore, there is a huge waste (at least O(n))
of both computation time and memory in most
microlithography aerial image simulation tools.
The question is: "how to compute an image
contour without explicitly generate images?".
In this paper, we show that it is indeed feasible
to know the image contour with an explicit
image formation. The concept is to represent
the image in an implicit way. In our algorithm,
we utilize hierarchical region-wise function
such as 2D polynomials to fit the aerial image
kernels instead of using a bitmap type fit.
Therefore, any LUT (Look-up-table) operation
can be transformed into a polynomial look up
and mathematical operations. Since there are
only additive and subtractive operations during
aerial image generation, we only need to
apply same operations to the polynomial coefficients.
Once the LUT operation is done,
Poster Session: Source and Mask Optimization
PSM design for inverse lithography with partially coherent illumination
Show abstract
Phase-shifting masks (PSM) are resolution enhancement techniques (RET) used extensively in the semiconductor
industry to improve the resolution and pattern fidelity of optical lithography. Recently, a set of gradient-based
PSM optimization methods have been developed to solve for the inverse lithography problem under coherent
illumination. Most practical lithography systems, however, use partially coherent illumination due to non-zero
width and off-axis light sources, which introduce partial coherence factors that must be accounted for in the
optimization of PSMs. This paper thus focuses on developing a framework for gradient-based PSM optimization
methods which account for the inherent nonlinearities of partially coherent illumination. In particular, the
singular value decomposition (SVD) is used to expand the partially coherent imaging equation by eigenfunctions
into a sum of coherent systems (SOCS). The first order coherent approximation corresponding to the largest
eigenvalue is used in the PSM optimization. In order to influence the solution patterns to have more desirable
manufacturability properties and higher fidelity, a post-processing of the mask pattern based on the 2D discrete
cosine transformation (DCT) is introduced. Furthermore, a photoresist tone reversing technique is exploited in
the design of PSMs to project extremely sparse patterns.
Manufacturability of ILT patterns in low-NA 193nm environment
Show abstract
With escalating costs of higher-NA exposure tools, lithography engineers are forced to evaluate life-span extension of
currently available lower-NA exposure tools. In addition to common resolution enhancement techniques such as off-axis
illumination, edge movement, or applying sub-resolution assist features, Inverse Lithography Technology (ILT) tools
available commercially at this moment offer means of extending current in-house tool resolution and enlarging process
window for random as well as periodic mask patterns. In this paper we explore ILT pattern simplification procedures and
model calibration for a range of illumination conditions. We study random pattern fidelity and critical dimension
stability across process window for 65nm contact layer, and compare silicon results for both conventional optical
proximity correction and inverse lithography techniques.
Inverse vs. traditional OPC for the 22nm node
Show abstract
The 22nm node will be patterned with very challenging Resolution Enhancement Techniques (RETs) such
as double exposure or double patterning. Even with those extreme RETs, the k1 factor is expected to be
less than 0.3. There is some concern in the industry that traditional edge-based simulate-then-move Optical
Proximity Correction (OPC) may not be up to the challenges expected at the 22nm node. Previous work
presented the advantages of a so-called inverse OPC approach when coupled with extreme RETs or
illumination schemes. The smooth mask contours resulting from inverse corrections were shown not to be
limited by topological identity, feedback locality, or fragment conformity. In short, inverse OPC can
produce practically unconstrained and often non-intuitive mask shapes. The authors will expand this
comparison between traditional and inverse OPC to include likely 22nm RETs such as double dipole
lithography and double patterning, comparing dimensional control through process window for each OPC
method. The impact of mask simplification of the inverse OPC shapes into shapes which can be reliably
manufactured will also be explored.
Innovative pixel-inversion calculation for model-based sub-resolution assist features and optical proximity correction
Show abstract
We propose an inversion calculation method based on a simple "pixel-flipping" approach. The simple method
features innovative wavefront-expansion and wavefront-based damping techniques in order to obtain accentuated
corrections near the drawn pattern. The method is first employed to be a stand-alone optical proximity correction
solution that directly calculates the corrected masks with acceptable contours and image contrast. In addition, a
model-based pre-OPC flow, where the initial sizing of drawn patterns and surrounding sub-resolution assist features
(SRAF) are simultaneously generated in a single iteration using this inversion calculation is also proposed to minimize
technology-transition risks and costs. A mask simplification technique based on the central moments is introduced in
order to snap the corrections into 45 degree and axis-aligned line segments. This approach allows achieving optimized
corrections while minimizing the impact to the existing and validated correction flow.
Source optimization for three-dimensional image designs through film stacks
Show abstract
In this paper, we will outline the approach for optimizing the illumination conditions to print three-dimensional images
in resist stacks of varying sensitivity in a single exposure. The algorithmic approach for acheiving both optimal common
and weakest window is presented. Results will be presented which demonstrate the ability of the technique to create threedimensional
structures. The performance of the common and weakest window formulation will be explored using this
approach. Additionally, due to physical restrictions there are limitations to the type of patterns that can be printed with a
single exposure in this manner, thus the abilities of such a technique will be explored.
Poster Session: Spacer-based Processes
Pattern decomposition and process integration of self-aligned double patterning for 30nm node NAND FLASH process and beyond
Show abstract
As IC manufacturing goes from 45nm to 30nm node half-pitch, the lithography process k1 factor will fall below 0.25 by
using water-based ArF-immersion scanner. To bridge the gap between ArF-immersion and next generation lithography,
which is not ready yet for production, Double Patterning Technology (DPT) has been evaluated and identified as a
promising solution as it utilizes existing equipment and processes. Self Aligned Double Patterning (SADP) has the
advantage of dense array definition without overlay issue and is hence useful for memory device; but its characteristic
restricts the feasibility of two-dimensional circuit pattern definition on the other hand.
This paper describes the ideas of 30nm node NAND FLASH cell circuit critical feature (pickup, gate, contact array)
definition by decomposing the target patterns to SADP defined dense array in conjunction with cropping and/or
periphery masks steps. The concerns and issues of cropping/periphery mask step process integration as well as SADP
alignment algorithm are investigated, and the countermeasures with alternative process schemes and novel frame designs
are presented. Finally, simulation prediction has shown that the capability of 30nm NAND FLASH critical features
patterning with depth of focus equal to or above 0.15um is expected at each mask step by ArF-dry lithography.
A manufacturing lithographic approach for high density MRAM device using KrF double mask patterning technique
Show abstract
MRAM, a potential candidate of next generation or "universal" memory device, has been
in process development and targeted for production. This high density non-volatile
memory has a fast <20ns read/write cycle and unlimited endurance. Wordline layer is
important for writing. Using KrF tool capability only, this "line & contact hole" wordline
pattern must meet the challenge of aggressive pitch size shrinkage and process margin
requirements in order to deliver reliable writing efficiency. Thus, appropriate process
integration schemes demonstrating single exposure, double exposure and double
patterning are compared. A comprehensive study from mask layout simulation and its
cost to litho OL/CD process window experimental data analysis will be presented to
achieve potential high yield manufacturing goal of the critical wordline design and
process integration.
Alignment and overlay improvements for 3x nm and beyond process with CVD sidewall spacer double patterning
Show abstract
Sidewall Spacer Double Patterning (SSDP) has been adopted for the primary patterning technique for 3x nm technology
node and beyond in flash memory device manufacturing. Three mask flow are used in SSDP process scheme in order to
form the actual device layer; Core mask to define the template pattern, Trim mask to cut (cropping) the unneeded line
ends from sidewall spacer, and Pad mask to pattern the periphery structures. Inter-layer and intra-layers alignment with
sidewall spacer double patterning requires some engineering efforts compared to traditional single patterning alignment
techniques. In this paper, we study the impacts of hard-mask materials on the inter-layer alignment as well as the mark
design and process flow impact on intra-layer alignment. For intra-layer alignment, we searched various ASML
ATHENA alignment marks and found the only workable mark (VSPM-AA157 Polar). Although the wafer quality
scores during alignment were less than 0.1% in many cases, the alignment was successful and yielded acceptable
performance for research and development activities requiring less than 10nm misalignment. Further new mark design
and test should be carried in implementing in sidewall spacer double patterning process.
Poster Session: Tools
Birefringence simulations of annealed ingot of calcium fluoride single crystal: consideration of creep behavior of ingot during annealing process
Show abstract
We developed an analysis system for simulating birefringence of an annealed ingot of CaF2 single crystal caused by the
residual stress after annealing process. The analysis system comprises the heat conduction analysis that provides the
temperature distribution during the ingot annealing, the stress analysis to calculate the residual stress after ingot
annealing, and the birefringence analysis of an annealed ingot induced by the residual stress. In the residual stress
calculation, we can select either the elastic thermal stress analysis using the assumption of a stress-free temperature or
more exact stress analysis considering the time-dependent nonlinear behavior of a material called creep. When we use
the residual stress calculated from the creep deformation analysis of a CaF2 ingot, we can obtain reasonable results both
for the optical path difference values and for its distributions in comparison with the experimental results.
Cost-effective shrink of semi-critical layers using the TWINSCAN XT:1000H NA 0.93 KrF scanner
Show abstract
The TWINSCAN XT:1000H extends KrF lithography to expose layers that previously required more costly ArF
lithography. These layers, including implants and metal interconnects, contain multiple, through pitch or random, 2-
dimensional (2D) features.
In this paper, we show process windows for 115 nm random via holes using conventional illumination, 110 nm dense &
isolated via holes using a soft quasar illumination shape, 95 nm trenches through pitch with an annular illumination
mode as well as the process windows for a combination of patterns representative for implant structures using a soft
annular illumination mode.
We also prove that the XT:1000H can be integrated in an existing high volume manufacturing environment: transfer of a
65 nm logic metal-1 layer from a high NA XT:1400 dry ArF scanner to the XT:1000H has been evaluated by optimizing
the illumination settings and applying advanced mask design approaches to meet requirements for exposure latitude,
depth of focus and MEEF. In addition, we show that the CD proximity matching performance between the XT:1000H
and NA 0.8 XT:850 KrF scanners can be maximized using illumination setting optimization and EFESE focus scan.
Finally, matched machine overlay performance between the XT:1000H and an XT:1900Gi ArF immersion scanner has
been evaluated.
Optical performance of laser light source for ArF immersion double patterning lithography tool
Show abstract
In advanced lithography processes, immersion lithography technology is beginning to be used in volume production at
the 45-nm technology node. Beyond that, double-patterning immersion lithography is considered to be one of the
promising technologies -meeting the requirements of the next-generation 32-nm technology node. Light source
requirements for double patterning lithography tool are high power and high uptime to enhance economic efficiency, as
well as extremely stable optical performances for high resolution capabilities.
In this paper, the GT62A, Argon Fluoride (ArF) excimer laser light source which meets these requirements is introduced.
The GT62A has an emission wavelength of 193-nm, a power output of 90 W and a repetition rate of 6,000 Hz. The dose
uniformity of the GT62A was improved for reduction of Critical Dimension (CD) variation and better Critical
Dimension Uniformity (CDU). A stable wavelength and a spectrum bandwidth of the GT62A satisfy the requirements of
the high resolution lithography tools which need the steady focus stability. In addition, we verified by simulation that the
spectrum bandwidth control in the GT62A contributes to Depth of Focus (DOF) enhancement. The new technology for
the light source and detailed optical performance data are presented.
True polarization characteristics of hyper-NA optics excluding impact of measurement system
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High lens numerical aperture for improving the resolution of a lithographic lens requires a high incident angle of
exposure light in resist, which induces the vectorial effect. As a result, the vectorial effect has become more sensitive and
vectorial fingerprint with higher accuracy has been required for effective image forming simulation. We successfully
obtained true polarization characteristics of projection optics without the effect of measurement optics for more accurate
image forming simulation. Accuracy of the result of separating Jones matrix of projection optics and that of
measurement optics are presented.
Reliability report of high power injection lock laser light source for double exposure and double patterning ArF immersion lithography
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ArF immersion technology is spotlighted as the enabling technology for the 45nm node and beyond. Recently, double
exposure technology is also considered as a possible candidate for the 32nm node and beyond. We have already released
an injection lock ArF excimer laser, the GT61A (60W/6kHz/10mJ/0.35pm) with ultra line-narrowed spectrum and
stabilized spectrum performance for immersion lithography tools with N.A.>1.3, and we have been monitoring the field
reliability data of our lasers used in the ArF immersion segment since Q4 2006. We show GT series reliability data in the
field. GT series have high reliability performance. The availability that exceeds 99.5% proves the reliability of the GT
series. We have developed high power injection lock ArF excimer laser for double patterning, the GT62A
(90W/6000Hz/15mJ/0.35pm(E95)) based on the GigaTwin (GT) platform. Number of innovative and unique
technologies are implemented on GT62A in order to reduce running cost of laser. We have introduced unique technology
to enable 40 billion pulse lifetime of laser chambers to drastically reduce running cost. In addition, we have improved
lifetime of Line Narrowing Module significantly by changing optical path. Furthermore, the extension of gas refill
intervals was achieved by introducing new gas supply module and sophisticated gas control algorithm. We achieved the
reduction of operation cost and down time by introducing these three technologies.
Immersion-cluster uptime enhancement technology toward high-volume manufacturing
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In immersion lithography, importance is placed on technology for controlling coating along the edge of the wafer. In the
case of a top-coat process, it has been observed that the top coat can peel off during immersion exposure due to weak
adhesion to the substrate, a characteristic of top-coat films. The peeling of the film is thought to adversely affect
immersion-exposure equipment and the wafer surface by the formation of defects due to the contamination of the
immersion-exposure tool and by residual particles. Nikon Corporation and Tokyo Electron Ltd. (TEL) have performed
joint research and development in response to these problems. TEL has studied rinsing technology for the wafer edge
section and established coating processes and control techniques that rinse the edge section to remove foreign matter and
that control the cutting position of each film in the edge section. TEL has developed new processes and hardware to
remove foreign matter introduced into the immersion-exposure tool, and has shown that this technology can help prevent
contamination of exposure equipment. Nikon has established efficient on-body periodic rinsing as a new technology for
exposure equipment that can reduce defect.
Lithography line productivity impact using Cymer GLX technology
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Leading-edge scanners in fabs worldwide have particularly high system utilization and require peak levels of system
throughput and availability. Laser gas exchanges typically occur daily on these systems (or every 100M pulses or less),
with each exchange lasting up to 20 minutes. This downtime has a direct negative effect on availability, and if it is
reduced, the productivity of the litho cell increases.
This paper will outline the immediate success fabs have experienced after equipping scanners with Cymer's Gas
Lifetime eXtension (GLXTM) technology, which increases scanner availability by extending the time between excimer
laser gas exchanges by a factor of more than 10. To date, more than 100 leading-edge scanners feature Cymer's GLX
technology, which has improved light source availability by more than 1.5 percent. Moreover, multiple chipmakers
report more than 2 percent improvement in litho cell productivity due to GLX, corresponding to 2000 wafers/month
increase for a 100,000 wafers/month fab. The increase in measured productivity is the leveraged benefit of reducing
process interruptions around the refill cycle
GLX technology extends the shot-based interval between gas refills to 1 billion pulses for Cymer's XLA light sources,
and provides excellent stability in key optical performance parameters, such as bandwidth and dose stability over the
entire gas life. This paper will provide extensive performance data during extended light source operation on litho cells
equipped with GLX technology, and multiple use scenarios will be examined, including usage at memory and logic fabs.
The paper will also discuss the performance of GLX2TM technology which further extends the maximum time between
light source gas exchanges from 1B pulses to 2B pulses, and reduces downtime associated with gas refills by a factor of
20. The stability and productivity benefits of this new technology can be realized under all light source utilization
scenarios. With GLX2, the refill interval at high utilization chipmakers is 3 weeks, and 4-8 weeks at lower utilization
customers. Metrics illustrating the success of each of these capabilities will be presented. The second-generation of GLX
technology was launched in July 2008 after chipmakers responded favorably to GLX performance metrics.
Enabling high volume manufacturing of double patterning immersion lithography with the XLR 600ix ArF light source
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Deep ultraviolet (DUV) lithography improvements have been focused on two paths:
further increases in the effective numerical aperture (NA) beyond 1.3, and double
patterning (DP). High-index solutions for increasing the effective NA have not gained
significant momentum due to several technical factors, and have been eclipsed by an
aggressive push to make DP a high-volume manufacturing solution. The challenge is to
develop a cost-effective solution using a process that effectively doubles the lithography
steps required for critical layers, while achieving a higher degree of overlay performance.
As a result, the light source requirements for DP fall into 3 main categories: (a) higher
power to enable higher throughput on the scanner, (b) lower operating costs to offset the
increased number of process steps, and (c) high stability of optical parameters to support
more stringent process requirements. The XLR 600i (6kHz, 90W @15mJ) was
introduced last year to enable DP by leveraging the higher performance and lower
operating costs of the ring architecture XLR 500i (6kHz, 60W @10mJ) platform
currently used for 45nm immersion lithography in production around the world. In
February 2009, the XLR 600ix was introduced as a 60/90W switchable product to
provide flexibility in the transition to higher power requirements as scanner capabilities
are enhanced. The XLR 600ix includes improved optics materials to meet reliability
requirements while operating at higher internal fluences. In this paper we will illustrate
the performance characteristics during extended testing. Examples of performance
include polarization stability, divergence and pointing stability, which enable consistent
pupil fill under extreme illumination conditions, as well as overall thermal stability which
maintains constant beam performance under large changes in laser operating modes.
Furthermore, the unique beam uniformity characteristics that the ring architecture
generates result in lower peak energy densities that are comparable to those of a typical
60W excimer laser. In combination with the XLR's long pulse duration, this allows for
long life scanner optics while operating at 15mJ.