This PDF file contains the front matter associated with SPIE Proceedings Volume 7140, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and the Conference Committee listing.

This paper describes the research done at center for plasma material interactions (CPMI) to address the EUVL (extreme ultra- violet lithography) contamination control to achieve the HVM (high volume manufacturing) requirements in industry. Energetic atom and macro-particle emission are unavoidable when plasmas are used to generate photons in both DPP and LPP based EUV sources. These emitted particles interact first with the collection optics for the EUV radiation. Then some of the low energy sputtered collector material and some of the condensable Sn fuel exit at the intermediate focus (IF). This is undesirable. A critical requirement of stepper manufactures is to have only clean photons at the IF of EUV source-collector module. The very EUV photons that the system is designed to create can have an effect on the projection and illumination optics causing a reduction of mirror reflectivity. Even with advanced mitigation techniques, stepper optics can be damaged due to energetic and thermal neutrals. Particle contamination is problematic at the mask, and resist issues on the wafers themselves have an effect on the masks and optic elements. The efficiency of mitigation schemes is discussed. We present progress on our recent experiments on the measurement of ionic and neutral debris at Intermediate Focus (IF) in the DPP source. We also present progress on cleaning Sn deposition off of a multi-shell collector mock-up using reactive ion etching plasma, particle contamination removal from the mask blanks, and line edge roughness reduction in photoresisit.

One of the main experimental setups for EUV lithography is the ASML EUV Alpha-Demo Tool (ADT), which achieves the first full-field EUV exposures at a wavelength of 13.6nm and a numerical aperture of 0.25. We report on the assessment of the baseline imaging performance of the ADT installed at IMEC, and review the work done in relation to EUV reticles and resists. For the basic imaging performance of the ADT, we have studied 40 LS patterns through dose and focus and at multiple slit positions, to extract exposure latitude and depth of focus. Measurements of reticle CD vs. wafer CD were done to determine the Mask Error Enhancement Factor (MEEF) for dense features. We also discuss the uniformity of the different features across the field, and the factors that influence it. The progress in EUV resist performance has been tracked by screening new materials on the EUV ADT. Promising resist materials have been tested on the ASML ADT and have demonstrated sub 32nm Line/Space and 34nm dense contact hole resolution. One of the main topics related to EUV reticles is reticle defectivity along with reticle defect printability. We have experimentally measured the number of wafer defects that repeat from die-to-die after reticle exposure on the ADT. To examine the wafer signature of the repeating defects, a SEM-based defect review is then conducted. We have used rigorous simulations to show that the defect signature on wafer can correspond to a relatively large ML defect, which can print as a hollow feature.

The main challenge facing the implementation of EUV resist and processing has been concurrent achievement of high sensitivity, high resolution, and low line width roughness (LWR). In order to improve the performance of EUV resist, Selete is actively pursuing its benchmarking. The results from this benchmarking were found to be as follows: E_size improved with the increasing capability of EUV pattern exposure. Sensitivity improved during this year. Resolution is found to be almost sufficient for 32-nm half-pitch (hp), but not quite good enough for 22-nm hp. Resist blur of the resist, which marked good score in benchmarking, is found to be 10nm to 11nm. LWR is still far from its target value.

Flare in EUV mirror optics has been reported to be very high and long range effect due to its character which is inversely proportional to the 4th order of wavelength. The high level of flare will generate CD (Critical Dimension) variation problem in the area where the gradient of aerial pattern density is large while the long range influencing character would confront an issue of computational challenge either for OPC (Optical Proximity Correction) modeling or for any other practical ways to accommodate such a long range effect. There also exists another substantial challenge of measuring and characterizing such a long range flare accurately enough so that the characterized flare can successfully be used for the compensation in the standard OPC flow.

We have investigated three candidate lithography technologies for 2x nm HP generation and beyond for the application to LSI, namely, double patterning technology (DPT), EUV lithography (EUVL) and nanoimprint lithography (NIL). In terms of lithography unit technologies and lithography integration technologies, each technology has advantages and disadvantages from the viewpoint of difficulty, development resources, extendability, process cost, and so on. Using a development matrix consisting of development steps and development stages, we clarified the current development status for each technology. This matrix indicates the items for which technological critical breakthroughs are necessary to realize LSI production. From this study, we made three lithography development scenarios for the feasibility stage and the production stage for 2x nm HP generation and beyond.

A two-dimensional photonic crystal (PC) structure introduced into the anode layer of an organic light-emitting diode (OLED) was designed to enhance the light extraction efficiency. Using the plane wave expansion method and the finite-difference time-domain method to simulate the optical properties, we found that the extraction efficiency of the OLED device can be greatly enhanced by modifying the lattice constant of the PC array. In our simulation results, the enhancement of the extraction efficiency can approach 60% for the optimized square PC pattern with a period of ~500nm in the OLED device emitting at the center wavelength of 510nm. In this work, the PC pattern was also fabricated to implement the simulation results via the UV-curing nano-imprint technique. To maximize the enhancement effect, the residual layer on the imprinted surface should be really thin over a large area and could thus be easily removed by the RIE process.

As we are moving towards the 32nm node and beyond, the tightening of CD control requirements is becoming very challenging for the semiconductor industry. Therefore, year after year the need for accuracy in CD measurement is becoming one of the major components in process control. In order to succeed reaching in a near future the 'true CD' that will guarantee high yield and high performances, the semiconductor industry has to quickly move into a new 'Industrial Reference Metrology Model'. Today the industrial configuration of CD Metrology relies on CD-SEM or Scatterometry techniques depending on the criticality of the level that is measured. Both techniques are challenged and tend to show strong fundamental limitations in term of accuracy when being used in their conventional configuration (conventional ellipsometry or reflectometry for Scatterometry and threshold algorithm for CD-SEM). Therefore a huge effort has to be made on reference metrology inside the industrial semiconductor environment. The calibration of CD-SEM through Pitch standard is definitely not enough because it does not guarantee any accuracy onto CD measurement which is the main output. In the same way, using Scatterometry in the industrial environment without several 'golden' standards that have been calibrated with a true reference technique is also definitely limited for future technological nodes in order to avoid correlation between outputs (CD, height, Sidewall Angle) that will inevitably lead to wrong process window definition and bad process control. In this paper we will present some experimental results illustrating in practical terms the needs for future CD metrology and the current limitations of industrial techniques. For example, we will talk about emerging 3D multiwires FET devices which require specific 3D metrology. Based on the conclusion which shows the increasingly need for accuracy in the industrial environment, we will discuss about a potential new Reference Metrology Landscape that take into account the limitations of standard industrial techniques (i.e CD-SEM and Scatterometry). These complementary metrology capabilities which will become mandatory in a near future will help the semiconductor industry to corner well with accurate measurement and Reference Metrology inside the fab.

Historically, in a volume production environment, process induced variation in optical property (n&k) of film stack was not significant for the most of applications using scatterometry. Many papers presented before addressed the CD variation in the production by adopting the fixed optical property approach [1-8]. However, with shrinkage of device size, and introduction of new material and process, n&k variation of some critical layers can not be ignored. In this paper, it presents impacts on measured optical CD due to n&k variation of one critical film in a 70nm DRAM ArF lithography process at a patterned area (A-layer). A solution to minimize the impacts using floating n&k in the scatterometry model is discussed, developed and verified.

Critical dimension atomic force microscope (CD-AFM or 3D-AFM) is an important metrology technique for full three-dimensional measurements of linewidth CD and sidewall shape. Recent improvements in the 3D-AFM platform design, including high-precision/low-drift sample stages and high resolution optics, have been coupled with 'enhanced CD' (eCD) scan mode and novel AFM tip design. Especially, the eCD mode features a fast scanning actuator system (FA) and a bottom corner transitional rescan algorithm (TRS). The actuation system utilizes high gain feedback electronics and high bandwidth piezoelectric actuator to pull away a slender tip much faster from a small trench sidewall. The transitional rescan algorithm detects a rising sidewall before rescanning the transition for better bottom corner profiling. The paper presents evaluation data to show these enhancements resulted in improved measurement capability for small trenches required for shrinking device size, better sidewall profiling, more accurate bottom CD and LWR/LER measurement, faster scan speed, and less tip wear [1]. All the improvements ensure 3D-AFM continues to have the lowest measurement uncertainty among all other dimension metrology techniques.

The potential of spectroscopic Mueller polarimetry for the dimensional characterization of periodic structures has already been discussed in several instances. With respect to standard scatterometry; the added value of the technique is related to the information contained in the 16 elements of the Mueller matrix, while usual scatterometry provides only two. The additional information can prove useful to decorrelate dimensional or optical parameters, and to assess the adequacy of the model describing the profiles to be reconstructed: if the model is adequate, the optimal values of the dimensional parameters must remain stable when the measurement conditions, and thus the input data, are varied. This issue has been addressed for a series of 1D gratings etched in bulk Si and characterized by a spectroscopic polarimeter operating in the visible (Horiba Jobin Yvon MM-16), as well as CD-SEM and state-of-the art CD-AFM. With the usual lamellar or trapezoidal models both the CD and thickness values exhibit up to 10 nm systematic variations with measurement conditions. In contrast, with an original model taking into account the non-flatness of the open areas between adjacent lines the parameters become consistent to within 2 nm, well below typical tool-to-tool offsets. The corresponding profiles are also compatible with the CD-AFM images.

Light depolarization occurs whenever different polarization responses add up incoherently, as it may be the case with inhomogeneous samples. The most convenient technique to characterize such samples is Mueller matrix polarimetry, as it is the only one providing all the relevant information in presence of depolarization. We studied the case of small grating boxes surrounded by bare silicon, in conditions where both the gratings and the substrate were illuminated by the Mueller polarimeter beam. The grating optical response is modeled by using rigorous coupled-waves analysis, and added incoherently to that of the substrate by merely summing the corresponding Mueller matrices. The line width and the depth of the grating as well as the percentage of substrate in irradiated spot area were obtained by fitting the experimental data taken with controlled displacement of the light spot in the boundary region between grating and substrate. Accurate grating parameters could be obtained with the fraction of the spot area within the grating box was larger than 30%. Moreover, these parameters remained relatively constant when this fraction was further decreased to 5%.

It could be argued that the biggest challenge of the 32 nm half pitch node is the production implementation of double patterning lithography. Within the framework of this broad domain, a specific challenge which has been highlighted is overlay control due to the sharing between two exposures the overlay control allocation of a single patterning step. The models used in the literature to support this assertion are reviewed and compared with recent results. An analysis of the implications for overlay metrology performance and cost of ownership is presented and compared with actual capabilities currently available with both imaging and scatterometry sensor technology. Technology matching between imaging and scatterometry emerges as a requirement to enable combined imaging scatterometry overlay control use cases.

Overlay requirements for semiconductor devices are decreasing faster than anticipation. Beyond 50nm technology node, overlay budget becomes much tighter as 20% of half pitch. If Double Patterning Technology implemented, CD error will consume overlay control budget, which must be tighter than 1nm or 2nm. For 32nm technology node, the overlay control budget might be less than 5nm. In this paper, we studied the possibility of 5nm overlay control by using Zone Alignment (ZA), High Order Correction (HOC) and Correction Per Exposure (CPE). ZA is a novel zone dependency alignment strategy which compensates an improper averaging effect through weighting all surrounding marks with a linear model. HOC is an alignment correction method which can compensate nonlinear overlay error up to fifth order polynomial. CPE is a function of Grid-Mapper package, which is a field base method to correct overlay error field by field. It's also a good approach to minimize the grid fingerprint difference between exposure tools. The results of this paper indicate that ZA and HOC can reduce 15~25% uncorrectable overlay residual against conventional linear model and the stability in mass production has been demonstrated. Therefore, it is still not possible to control overlay within 5nm. CPE shows very good overlay residual performance as our expectation, and it's a possible approach to achieve 5nm overlay control in 32nm technology node. In addition, the feedback or feed-forward mechanisms have to be established for mass production worthy.

Need for accuracy, precision, speed and sophistication in metrology has increased tremendously over the past few years. Lithography performance will increasingly depend on post patterning metrology and this dependency will be heavily accelerated by technology shrinkage. These requirements will soon become so stringent that the current metrology capabilities may not be sufficient to support these near future needs. Accuracy and precision requirements approaching well into sub-nanometer range while the demand for increase in sampling also continues, triggering the need for a new technology in this area. In this technical presentation the authors would like to evaluate such technology that has the potential to support the future needs. Extensive data collection and tests are ongoing for both CD and overlay. Data on first order diffraction based overlay shows unprecedented measurement precision. The levels of precision are so low that for evaluation special methods has been developed and tested. In this paper overlay measurement method and data will be discussed, as well as applicability for future nodes and novel lithography techniques. CD data will be reported in the future technical publications.

We have proposed a new inspection method of in-line focus and dose controls for semiconductor high volume manufacturing. We referred to this method as the focus and dose line navigator (FDLN). Using FDLN, the deviations from the optimum focus and exposure dose can be obtained by measuring the topography of the resist pattern on a process wafer that was made under a single-exposure condition. Generally speaking, FDLN belongs to the technology of solving the inverse problem as scatterometry. The FDLN sequence involves following the two steps. Step 1:creating a focus exposure matrix (FEM) using a test wafer for building the model as supervised data. The model means the relational equation between the multi measurement results of resist patterns ( e.g. Critical dimension (CD), height, sidewall angle) and FEM's exposure conditions. Step 2: measuring the resist patterns on a manufacturing wafers and feeding the measurement data into the library to extrapolate focus and dose. In this paper, we explain again about the theorem of the FDLN and show experimental results using the many kind CDmeasurement tool(the advanced CD-AFM, optical CD measurement tool, the advanced CD-SEM and the Overlay measurement tool).

Identifying hotspots--structures that limit the lithography process window--become increasingly important as the industry relies heavily on RET to print sub-wavelength designs. KLA-Tencor's patented Process Window Qualification (PWQ) methodology has been used for this purpose in various fabs. PWQ methodology has three key advantages (a) PWQ Layout--to obtain the best sensitivity (b) Design Based Binning--for pattern repeater analysis (c) Intelligent sampling--for the best DOI sampling rate. This paper evaluates two different analysis strategies for SEM review sampling successfully deployed at Inotera Memories, Inc. We propose a new approach combining the location repeater and pattern repeaters. Based on a recent case study the new sampling flow reduces the data analysis and sampling time from 6 hours to 1.5 hour maintaining maximum DOI sample rate.

In the early development stage of 32nm processes, identifying and isolating systematic defects is critical to understanding the issues related to design and process interactions. Conventional inspection methodologies using random review sampling on large defect populations do not provide the information required to take accurate and quick corrective action. This paper demonstrates the successful identification and isolation of systematic defects using a novel methodology that combines Design Based Binning (DBB) and inline Defect Organizer (iDO). This new method of integrating design and defect data produced actionable inspection data, resulting in fewer mask revisions and reduced device development time.

Two methods for monitoring acid/base airborne molecular contamination (AMC) in 193nm lithography exposure tools, tracks, and process bays have historically been used for cleanroom and process contamination control. Ion Mobility Spectrometry (IMS) is a predominant technique used by semiconductor manufacturers for real-time AMC detection allowing for identification of subtle trends in AMC levels over time or alarming during high concentration events. Manual impinger sampling with ion chromatography (IC) analysis is a second technique used which pre-concentrates the air sample to allow for low detection limits and allows for some increased speciation of ions. The use of one or both of these techniques has a significant impact on the effectiveness of AMC detection and control, therefore, the equipment and strategy used within an AMC monitoring program can provide large competitive advantages that are not easily or quickly duplicated by other companies.

The impact of embedded substrate defects on end-of-line die yield has become significant for advanced process technology nodes. Quality control and grading of wafers intended for leading-edge devices thus require effective detection and identification of embedded defects. In this paper, we present the results of a study on incoming prime-grade wafers using a new defect inspection system capable of dark field scattering and bright field differential interference contrast inspection. The wafers were scanned on a KLA-Tencor Surfscan SP2XP inspection tool, and the combined scan signal were real time analyzed to classify the defects of interest from particles. Inspection of the wafers both before and after a resist-coat process showed that all air pockets detected on the bare substrates resulted in coating defects. In the second part of the study, a set of epitaxial (epi) wafers was inspected using oblique- and normal- incidence dark field scattering as well as bright field differential interference contrast. The defects were classified by rules-based binning, and found to contain a large number of killer defects including epi stacking faults and bumps. Classification results were confirmed by SEM review, and showed that this multi-channel methodology successfully identified the killer defects with >95% accuracy and purity.

Recently, a unique capability in highly sensitive detection of residue defects in photoresist patterns on a metal hard mask has been verified experimentally [T. Hayashi et al., Proc. SPIE, 6922 (2008) 6922-129]. In order to reveal the mechanism for the new defect inspection technique, the charging up induced by 300 eV - 2000 eV electron bombardment of thin insulating layers (SiO2, ~tens of nm) on Si is studied by using a self-consistent Monte-Carlo simulation of the transport of a primary electron and secondary electrons (SE) and the generation of an electric field due to the charges in the layer. The calculation is compared with the contrast changes in the SEM images of thermally oxidized layers (20~100 nm) on a Si wafer. Low-energy EB (or thick SiO2 layer) causes the positive charging of the layer, whereas the high-energy EB, which penetrates under thin SiO2 layer, relaxes the charging of the layer due to electron-hole recombination in Si. The thickness dependence of the SE yield for low- and high-energies is investigated, which explains the observed changes in the SEM images of the insulating layers on Si.

This paper describes a methodology for after-develop inspection (ADI) using a broadband DUV/UV/visible brightfield inspector with a unique optical mode. The VIB (Varied Illumination Brightfield) optical mode enables capture of unique killer defects at low nuisance rate on certain 45nm and 32nm ADI layers, significantly improving litho inspection sensitivity. By implementing this inspection, defect engineers were able to detect critical excursions at ADI rather than at later process steps. This shortened process development time and allowed for re-work, significantly reducing wafer cost.

The optimization of the source topology and mask design [1,2] is vital to future advanced ArF technology node development. In this study, we report the comparison of an iterative optimization method versus a newly developed simultaneous source-mask optimization approach. In the iterative method, the source is first optimized based on normalized image log slopes (NILS), taking into account the ASML scanner's diffractive optical element (DOE) manufacturability constraints. Assist features (AFs) are placed under the optimized source, and then optical proximity correction (OPC) is performed using the already placed AFs, in the last step the source is re-optimized using the OPC-ed layout with the AFs. The source is then optimized using the layout from the previous stage based on a set of user specified cost function. The new approach first co-optimizes a pixelated freeform source and a continuous transmission gray tone mask based on edge placement error (EPE) based cost function. ASML scanner specific constraints are applied to the optimized source, to match ASML's current and future illuminator capabilities. Next, AF "seeds" are identified from the optimized gray tone mask, which are subsequently co-optimized with the main features to meet the process window and mask error factor requirement. The results show that the new method offers significant process window improvement.

We made a new model for the pattern failure, which was the pattern collapse and the pattern bridging, of the resist patterns of 43nm 1:1 lines and spaces (L/S) exposed as a focus-exposure matrix, in order to explain and predict the process window of the pattern failure. It was found that the conventional 'Imax-Imin' model was unable to be fitted to the experimental pass/fail data. Instead of the Imax and Imin, we selected the critical dimension (CD) and the normalized image log slope (NILS) as the model input. The new 'CD-NILS' model corresponded well to the experimental pass/fail data. The good correspondence was assumed to be due to the properly selected model input. The pattern collapse, which occurs during the drying of the water at the rinse of the resist patterns, is expected to be accelerated by the smaller line CD and the larger line width roughness (LWR) due to smaller NILS. The pattern bridging, which occurs at the resist development, is expected to be accelerated by the larger line CD and the larger LWR. The CD-NILS model predicted the process window precisely when a new process condition (= a new illumination in this case) was adopted. It suggests that the CD-NILS model is a powerful methodology for predicting the process window in order to optimize the process condition and to optimize the lithography design.

With the shrinking of all fundamental features in modern IC manufacturing, the aerial image calculation is becoming insufficient for accurate simulation of the printable wafer. In this presentation, a reliable simulation methodology based on basic principles is being introduced which includes an exact analytical solution of the Maxwell equations inside the photoresist as well as all other relevant layers. This solution contains multi-layers including bottom anti-reflection coating (BARC), silicon dioxide, nitride layers, as well as immersion in the medium between the stepper and the photoresist. The calibration is performed in order of parameter importance. This calibration gives higher weight to the most critical parameters. The latent image in the resist is computed, the resulting acid concentration is derived from the latent image, and the PEB (post exposure baking) is completed by invoking a reaction-diffusion system. The diffusion equation component orthogonal to the resist surface is solved exactly in closed form due to the small dimension of the resist thickness. The development is performed in a similar way. The latent image is compared to SEM images and the simulation parameters are calibrated through a newly developed optimization scheme to produce very accurate simulation fidelity. The methodology given here has been very successfully applied in detection of printing failures (hot-spots) for state of the art compact designs. An accuracy smaller than 1nm has been obtained. The system is very fast, suitable for entire chip analysis and highly parallelized. This calibration can be performed on a dual core laptop. Several practical examples are given.

The k1 factor continues to be driven downwards, even beyond its theoretical limit 0.25 in order to enable the 32 nm feature generation and beyond. Due to the extremely small process window that will be available for such extremely demanding imaging challenges, it is necessary that each unit contributing to the imaging system be driven to its ultimate performance capability. The units in such an integrated imaging system include the projection lens, illumination optics, in-situ metrology tooling, reticle stage control, and wafer stage control. In this paper we are going to discuss the required functions especially for projection lens and illumination system and how to optimally control each unit in cooperation with the others in order to achieve the goal of 32 nm patterning and beyond.

The conventional segment-based OPC approach has been applied successfully for many CMOS generations and is currently favored. However, Inverse lithography technology (ILT) is a promising candidate for next-generation optical proximity correction (OPC). Still, there are issues that need to be thoroughly addressed and further optimized. In this work, we propose a model-based pre-OPC flow where the sizing of drawn patterns and placement of surrounding sub-resolution assist features (SRAF) are simultaneously generated in a single iteration using an ILT method. The complex patterns can then be simplified for a conventional OPC solution.

Since the 1980's, immersion exposure has been proposed several times. At the end of 1990's, however, these concepts were almost forgotten because other technologies, such as electron beam projection, EUVL, and 157 nm were believed to be more promising than immersion exposures. The current work in immersion lithography started in 2001 with the report of Switkes and Rothschild. Although their first proposal was at 157 nm wavelength, their report in the following year on 193 nm immersion with purified water turned out to be the turning point for the introduction of water-based 193 nm immersion lithography. In February, 2003, positive feasibility study results of 193 nm immersion were presented at the SPIE microlithography conference. Since then, the development of 193 nm immersion exposure tools accelerated. Currently (year 2008), multiple hyper NA (NA>1.0) scanners are generating mass production 45 nm half pitch devices in semiconductor manufacturing factories. As a future extension, high index immersion was studied over the past few years, but material development lagged more than expected, which resulted in the cancellation of high index immersion plans at scanner makers. Instead, double patterning, double dipole exposure, and customized illuminations techniques are expected as techniques to extend immersion for the 32 nm node and beyond.

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.

We introduce the 'Orientation Zernike Polynomials', a base function representation of retardation and diattenuation which are most relevant for vector imaging. We show that the 'Orientation Zernike Polynomials' provide a complete and systematic description of vector imaging using high NA lithography lenses and, hence, a basis for an in depth understanding of both polarized and unpolarized imaging, and its modeling.

A third generation phase shift polarization monitor reticle is reported with improved resolution within the pupil and across the slit. The polarization state of illumination can be measured for lithography systems with NA up to 1.45. A double-reticle concept is proposed to expose both polarization test patterns and SEM alignment marks and polarimeter coordinates in the resist to optimize exposure for each independently. Both SEM imaging and polarization calculation is improved with the double reticle scheme. The single-exposure approach previously employed which can only measure three polarization states (X, Y and unpolarized) has been enhanced by a novel reciprocal exposure technique. The new exposure approach allows lithography engineers to vary effective polarization and measure at multiple custom polarization settings. Experimental results show that the sensitivity of the new reticle to polarization has more than doubled compared to the previous generation.

Optical proximity correction (OPC) methods are resolution enhancement techniques (RET) used extensively in the semiconductor industry to improve the resolution and pattern fidelity of optical lithography. Recently, a set of generalized gradient-based OPC optimization methods have been developed to solve for the inverse lithography problem under coherent illumination. Most practical lithography systems, however, operate under partially coherent illumination due to non-zero width sources and off-axis illumination from spatially extended sources. OPC methods derived under the coherent illumination assumption fail to account for the nonlinearities of partially coherent illumination and thus perform poorly in the latter scenario. This paper focuses on developing gradient-based binary mask optimization methods which account for the inherent nonlinearities of partially coherent systems. Two nonlinear models are used in the optimization. The first relies on a Fourier representation of the nonlinear model which approximates the partially coherent system as a sum of coherent systems. The second model is based on an average coherent approximation which is computationally faster. In order to influence the solution patterns to have more desirable manufacturability properties, wavelet regularization is added to the optimization framework. The advantages and limitations of both models in the inverse lithography problem are discussed and several illustrative simulations are presented.

KrF lithography is nowadays widely used for volume production spanning many device layers ranging from front-end 90nm to mid- & back-end layers in 45nm and 32nm ITRS imaging nodes. In this paper we discuss the addition of the new high-NA XT:1000H TWINSCAN(TM)scanning exposure tool to the KrF portfolio. We discuss advances in the system design and elaborate on its imaging and overlay performance. It is shown that stable tool performance supports 80nm resolution volume manufacturing. Extendibility with polarization towards sub-80nm is also addressed.

Full-field EUV exposure tool named EUV1 integrated and exposure experiments were started with the numerical aperture of the projection optics of 0.25 and conventional partial illumination with coherence factor of 0.8. 32nm elbow patterns were resolved in full arc field in static exposure. In the central area 25nm line-and-space patterns were resolved. In scanning exposure, 32nm line-and-space patterns were successfully exposed on a full wafer. Wavefront error of the projection optics was improved to 0.4nmRMS. Flare impact on imaging was clarified depend on the flare evaluation using Kirk test. Metal oxide capping layer and oxygen injection method were developed for the contamination control in EUV exposure tools. High-NA projection optics design is also reviewed.

This paper provides a review of development progress for a laser-produced-plasma (LPP) extreme-ultra-violet (EUV) source with performance goals targeted to meet joint requirements from all leading scanner manufacturers. Laser produced plasma systems have been developed as a viable approach for the EUV scanner light source for optical imaging of circuit features at sub-32nm and beyond nodes on the ITRS roadmap. Recent advances in the development of the system, its present average output power level and progress with various subcomponents is discussed. We present the latest results on peak EUV and average EUV power as well as stability of EUV output, measured in burst-mode operation at the nominal repetition rate of the light source. In addition, our progress in developing of critical components, such as normal-incidence EUV collector and liquid-target delivery system is described. We also report on dose stability, plasma position stability and EUV distribution at the output region of the source. This presentation reviews the experimental results obtained on systems with a focus on the topics most critical for an HVM source. The capability to scale LPP power by further development of the high power CO2 drive laser in order to increase duty cycle and duration of continuous light source operation is shown. Production systems with thermal management and capable of 5 sr light collection are being assembled and tested. A description of the development of a normal-incidence ellipsoidal collector is included. Improvements in substrate quality lead to increased EUV reflectance of the mirror. Results on the generation of liquid tin droplets as target material for efficient plasma generation are also described. The droplet generator serves as a key element in the precise and spatially stable delivery of small quantities of liquid tin at high repetition rates. We describe a protection module at the intermediate focus (IF) region of the source and imaging of the EUV distribution using a sub-aperture collector and a fluorescent screen. A path to meet requirements for production scanners planned well into the next decade is also presented.

XTREME technologies and Philips EUV have provided the majority of available EUV sources based on Discharge Produced Plasma (DPP) technology worldwide since 2003. The fact that all existing prototype scanners make use of DPP sources and that further power scaling and debris mitigation upgrades are made according to plan clearly contributes to the maturity of this technology. We will present the latest status of our tin based DPP sources in the joint development work of XTREME technologies and Philips EUV. Demonstration experiments pave the way for this technology towards the HVM power level.

Accelerating voltage as low as 5 kV for operation of the electron-beam micro-columns as well as solving the throughput problem is being considered for high-throughput direct-write lithography for the 22-nm half-pitch node and beyond. The development of efficient proximity effect correction (PEC) techniques at low-voltage is essential to the overall technology. For realization of this approach, a thorough understanding of electron scattering in solids, as well as precise data for fitting energy intensity distribution in the resist are needed. Although electron scattering has been intensively studied, we found that the conventional gradient based curve-fitting algorithms, merit functions, and performance index (PI) of the quality of the fit were not a well posed procedure from simulation results. Therefore, we proposed a new fitting procedure adopting a direct search fitting algorithm with a novel merit function. This procedure can effectively mitigate the difficulty of conventional gradient based curve-fitting algorithm. It is less sensitive to the choice of the trial parameters. It also avoids numerical problems and reduces fitting errors. We also proposed a new PI to better describe the quality of the fit than the conventional chi-square PI. An interesting result from applying the proposed procedure showed that the expression of absorbed electron energy density in 5keV cannot be well represented by conventional multi-Gaussian models. Preliminary simulation shows that a combination of a single Gaussian and double exponential functions can better represent low-voltage electron scattering.

Using a simple theoretical model, we calculated three-dimensional profiles of photoresists that were exposed by arbitrarily-shaped localized fields of high-transmission metal nano-apertures. We applied the finite-difference time-domain (FDTD) method to obtain the localized field distributions. These distributions are generated by excitation of localized surface plasmon polaritons underneath a circular, C-shaped or bowtie-shaped aperture. We predicted the two-dimensional exposure profiles of the photoresist as a function of the photoresist contrast when the results of the FDTD simulations were applied to the theoretical model. The three-dimensional exposure profiles of the photoresist were also visualized as a function of the exposure dose and the gap distance between the aperture and the photoresist. The three-dimensional exposure profiles provided useful information in determining the process parameters for nano-patterning by plasmonic lithography using the high-transmission nano-aperture.

In recent years, DRAM and Flash technology node has shrunk below to 45nm half pitch (HP) patterning with significant progresses of hyper numerical aperture (NA) immersion lithography system and process development. Several technologies such as extreme ultra violet (EUV) lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been developed for sub 40nm HP device. High index immersion lithography (HIL) is also one of the candidates for next generation lithography technology that has benefits of product cost, process simplification and usage for existing infrastructure though this technology must overcome critical issues--high index immersion fluid and lens optic development. In this paper, we will present simulation results on sub 40nm imaging characterization for HIL. First, we have studied the image performance for sub 40nm patterning with HIL. The image contrast, optical proximity effect and mask error enhanced factor (MEEF) are investigated through simulation. As pattern size decrease and lens NA gets bigger and bigger, the features on mask get smaller even below the wavelength of light and polarization related effects become one of the most critical issues. From comparison with results for 45nm HP patterning, we are able to suggest the reasonable process condition for HIL process. Then, we have investigated the optimum BARC condition to make preparations for 32nm HP pattering.

Mask defect is one of the biggest problems in Extreme Ultraviolet Lithography (EUV) technology. EUV mask must be free of small defects, requiring development of new inspection tools and low defect fabrication processes. So, we studied the influences of the defects on the mask for 22 nm line and space pattern. First, we changed the light quality caused by the various wavelength shift, incident angle, and the defect material with different refractive index. Second, we changed the defect size from 20 nm to 16 nm because 18 nm defect is assumed to a critical defect size for 22 nm node. Third, we also changed the defect positions; on top of the absorber, on the valley of the absorber, and at the sides of the absorber. Finally, we simulated the influence for the different shaped defect. A square pillar defect shows very different behavior compared to the more realistic round shaped defect. Defect of higher refractive index gives little influence, while defect of lower refractive index gives larger influence. A more realistic elliptical shaped defect gives less influence compared to square shaped defect. All the defect and EUV parameters will influence to the printability of the defect, but more study is needed to judge whether a certain defect can influence the printed pattern.

The cost of ownership (COO) of candidate technologies for 32 nm and 22 nm half-pitch lithography is calculated. To more accurately compare technologies with different numbers of process steps, a model that includes deposition, etching, metrology, and other costs is created. Results show lithography COO for leading edge layers will increase by roughly 50% from the 45 nm to the 32 nm half-pitch nodes. Double patterning and extreme ultraviolet lithography (EUVL) technologies have roughly the same COO under certain conditions. For 22 nm half-pitch nodes, EUVL has a significant cost advantage over other technologies under certain mask cost assumptions. Double patterning, however, may be competitive under worst case EUVL mask cost assumptions. Sensitivity studies of EUVL COO to throughput and uptime show EUVL may be cost-competitive at lower uptime and throughput conditions. In spite of these higher costs, total lithography costs for 32 nm and 22 nm half-pitches remain within reach of the Moore's Law trend. Finally, the COO of 450 mm lithography is calculated and shows the expected cost reduction is between 0% and 15%.

For extreme ultraviolet lithography (EUVL) to become a high volume manufacturing technology for integrated circuit manufacturing, the cleanliness of the system, especially the photomask, is of high importance. For EUV photomasks, which cannot be protected from contamination by the use of a pellicle, an effective and quick cleaning technology needs to be ready in order to maintain wafer throughput. There are challenges to extend current wet cleaning technologies to meet the future needs for damage-free and high efficiency mask cleaning. Accordingly, a unique process for cleaning particulates from surfaces, specifically photomasks as well as wafers, has been evaluated at the University of Illinois Urbana-Champaign. The removal technique utilizes a high density plasma source as well as pulsed substrate biases to provide for removal. Helium is used as the primary gas in the plasma, which under ionization, provides for a large density of helium metastable atoms present in the plasma. These metastable helium atoms have on the order of 20 eV of energy which can transfer to particles on the substrate to be cleaned. When the substrate is under a small flux of ion bombardment, these bonds then remain broken and it is theorized that this allows the particles to be volatilized for their subsequent removal. 100 % particle removal efficiency has been obtained for 30 nm, 80 nm, and 200 nm polystyrene latex particles. In addition, removal rate has been correlated with helium metastable population density determined by optical emission spectroscopy.

Recent progresses in the photoresists and photolithography for LCD industry applications have been primarily driven by the following two factors: advancement in the material performances (high resolution, high contrast ratio, low dielectric constant) for higher display quality, and cost reduction in the fabrication process. Along with crucial demand for cost competitiveness by improving production efficiency, environmental consciousness has been a major priority at fabrication process design to minimize the amount of waste produced. Having said the above, integration of two or more fabrication processes into a single process by using multi-tone mask technology has been the interest of research, due to its obvious advantage of reducing fabrication processes and cost. For example, multi-tone mask technology application has been widely employed on the TFT side to reduce the different types of photomasks being used. Similar trend has been employed on the CF side as well, where application of multi-tone mask technology is being investigated to integrate fabrication of multiple CF micro-components into a single process. In this presentation, we demonstrate a new approach of fabricating photospacer and peripheral CF components (MVA protrusion, sub-photospacers) in a single integrated process through multi-tone mask technology.

Various studies have been published on the formation and prevention of reticle haze; however, yield loss due to reticle haze is still an issue for most of the IC makers. For a mass production IC manufacturing fab, an easy and practical solution is needed to prevent haze generation. In this study, we focus on the solution, which can be easily implemented inside production fab and does not require a total implementation of specific type of gas or equipment. A reticle carrier with purging function combining with the use of a purge station for purging and storage is used. After implementing this solution in a 12" DRAM fabrication facility, the number of wafers printed without haze development on reticles protected by this solution can be up to 150,000 wafers, and this is great achievement in help ramping up the production and also maintain high yield. This solution has been proven to be effective in reducing the generation of haze.

The continuous integrated circuit miniaturization and the shrinkage of critical dimension (CD) have pushed the development of optical proximity correction (OPC), and also making CD more sensitive to process variations. Traditional OPC optimizes mask patterns at nominal lithography conditions, which may lead to poor performance with process variations. Hence, OPC software nowadays needs to take different process conditions into consideration to enhance the robustness of layout patterns. In this paper, we propose an algorithm which considers the defocus as a random variable when incorporating it into an inverse imaging framework to optimize the input mask, in order to gain more robustness for a wider range of focus errors. The optimal mask is calculated in a statistical manner by minimizing the expected difference between output patterns at different defocus conditions and the target pattern. With the necessary tradeoff in the close proximity of the nominal focus condition, the optimized mask gives more robust performance under a wider range of focus errors.

Double Patterning allows to further extend the use of water immersion lithography at its maximum numerical aperture NA=1.35. Splitting of design layers to recombine through Double Patterning (DP) enables an effective resolution enhancement. Single polygons may need to be split up (cut) depending on the pattern density and its 2D content. The split polygons recombine at the so-called 'stitching points'. These stitching points may affect the yield due to the sensitivity to process variations. We describe a methodology to ensure a robust double patterning by identifying proper split- and design- guidelines. Using simulations and experimental data, we discuss in particular metal1 first interconnect layers of random LOGIC and DRAM applications at 45nm half-pitch (hp) and 32nm hp where DP may become the only timely patterning solution.

When k1 is smaller than the resolution limit, e.g., for a half-pitch (HP) ≤32nm, the most advanced immersion scanner does not have sufficient imaging capability. Extreme ultraviolet (EUV) technology at wavelength of 13.5nm is considered a practical light source for next-generation lithographic technology [1,2]. However, before EUV lithography is suited to mass production, an appropriate exposure technology is needed to fill the gap between immersion ArF and EUV scanners. Double patterning technology (DPT) is a technology that extends the usability of immersion ArF systems. Notably, DPT relaxes the minimum pitch of a circuit layout for each split exposure; thus, ArF water-based immersion systems can be extended to 32 nm node and beyond. Improvements to exposure system hardware are needed to enhance imaging, overlay, and productivity performance. Additionally, patterning-related processes [3-5] must be improved to ensure patterning fidelity when two splits are combined. The remaining challenge is to develop an intelligent approach for splitting the original layout to two different exposure mask layouts. Generally, DPT can be categorized as two types according to its applications. One type is the so-called 'litho DPT,' which adopts dual litho-etching steps. The final pattern is a combination of two individual litho-etched patterns. In this case, a normal pattern-splitting method is required to keep the minimum HP of separate patterns as large as possible. The best method for pattern splitting is to use a rule-based approach, which separates features according to their geometrical information such as edge-to-edge and/or vertex-to-vertex distance. When using a rule-based scheme, a full-chip pattern decomposition is practical because it can has fast processing speed. The other type is 'spacer DPT,' which adopts a single split pattern as a sacrificial layer to form spacers deposited onto pattern edges. The idea implies that one can arbitrarily select one of the split layouts. However, a normal pattern-splitting technique is still required. With the assistance of polygon Boolean operations, the trim layout (to remove residual polygons) and makeup layout (to repair irregular missing polygons) can be generated using scripting electronic design automation (EDA) software. In this study, some examples of pattern splitting are demonstrated using the Tachyon pattern-splitting tool. Furthermore, Tachyon scripts are utilized to create layouts with consideration of OPC for spacer DPT. The patterns created after each process step can be emulated with the scripts to help the process verification. All techniques developed in this study for DPT pattern splitting are applicable for 32nm node and beyond.

In this paper, we will present experimental results on sub-40nm node patterning of DRAM and some technical issues for capping freezing in simplified double patterning lithography. Lithography resolution limit of single pattern is 40nm in ArF immersion process. For sub-40nm patterning, we have to use double patterning lithography or EUV process. But, double patterning lithography process is very complicated and expensive solution. And EUV volume production technology will be not ready until 2012. Therefore, we have tried a simplified double patterning lithography.

High NA (1.35) Immersion litho runs into the fundamental limit of printing at 40-45nm half pitch (HP). The next generation EUVL tool is known to be ready not until year 2012. Double patterning (DP) technology has been identified as the extension of optical photolithography technologies to 3xnm and 2xnm half-pitch for the low k1 regime to fill in the gap between Immersion lithography and EUVL. Self Aligned Double Patterning (SADP) Technology utilized mature process technology to reduce risk and faster time to market to support the continuation of Moore's Law of Scaling to reduce the cost/function. SADP uses spacer to do the pitch splitting bypass the conventional double patterning (e.g. Litho-Freeze-Litho-Etch (LFLE), or Litho-Etch-Litho-Etch (LELE)) overlay problem. Having a tight overlay performance is extremely critical for NAND Flash manufacturers to achieve a fast yield ramp in production. This paper describes the challenges and accomplishment of a Line-By-Spacer (LBS) SADP scheme to pattern the 29nm half-pitch NAND Flash STI application. A 193nm Dry lithography was chosen to pattern on top of the amorphous carbon (a-C) film stack. The resist pattern will be transferred on the top a-C core layer follow by spacer deposition and etch to achieve the pitch splitting. Then the spacer will be used to transfer to the bottom a-C universal hardmask. This high selectivity a-C hardmask will be used to transfer the 29nm half-pitch pattern to the STI. Good within wafer CD uniformity (CDU) <2nm and line width roughness (LWR) <2nm for the 29nm half-pitch NAND FLASH STI were demonstrated as the benefits using double amorphous carbon hardmask layers. The relationships among the photoresist CDs, CD trimming , as-deposited spacer film thickness, spacer width and the final STI line/core space/gap space CDs will also be discussed in this paper since patterning is combining both lithography performance with CVD and Etch process performance. Film selection for amorphous carbon and the complete DP hardmask scheme in terms of etching selectivity, optical properties and stress optimization was another key challenge to balance excellent litho alignment signal strength and straight pattern profiles without line bending effects. Etching efforts also played a very important roll to obtain pattern integrality under such a high aspect ratio (> 10) case through the whole SADP process. Finally, cost analysis for 193nm dry lithography SADP will be compared to 193nm Immersion lithography SADP.

We have studied both the mask CD specification and the mask defect specification for spacer patterning technology (SPT). SPT has the possibility of extending optical lithography to below 40nm half-pitch devices. Since SPT necessitates somewhat more complicated wafer process flow, the CD error and mask defect printability on wafers involve more process factors compared with conventional single-exposure process (SEP). This feature of SPT implies that it is very important to determine mask-related specifications for SPT in order to select high-end mask fabrication strategies; those are for mask writing tools, mask process development, materials, inspection tools, and so on. Our experimental studies reveal that both mask CD specification and mask defect specification are somehow relaxed from those in ITRS2007. This is most likely because SPT reduces mask CD error enhanced factor (MEF) and the reduction of line-width roughness (LWR).

Given the increasingly stringent CD requirements for double patterning at the 32nm node and beyond, the question arises as to how best to correct for CD non-uniformity at litho and etch. For example, is it best to apply a dose correction over the wafer while keeping the PEB plate as uniform as possible, or should the dose be kept constant and PEB plate tuning used to correct. In this paper we present experimental data using both of these approaches, obtained on an ASML XT:1900Gi and Sokudo RF^3S cluster.

As VLSI products are being developed rapidly, design rules of semiconductor devices are correspondingly shrinking. Therefore, the electric couplings between adjacent lines are increasing and this phenomenon requires control of critical dimension uniformity (CDU) more tightly. In addition to that, the development of lithography tool for sub- 40nm design rule (D/R) is being delayed, which makes most IC manufacturer drive double patterning technology (DPT) as next generation lithography (NGL) solution. CD control is one of critical issues to implement DPT for mass production, because CD of 1st pattern affects the formation of 2nd pattern seriously so that the uniformity of 1st pattern is more important. In this paper, the improvement of CD uniformity is investigated, especially for 3Xnm flash device for where double patterning technique is applied. Several methods have been considered or evaluated to improve CD uniformity. Among them, DoseMapperTM of ASML shows promising results. Using this system, in field uniformity (IFU) & in wafer uniformity (IWU) are improved 14% in 3&sgr;. To be implemented as a technology for mass production and to maintain the best performance, several efforts in terms of metrology and process will be further discussed in this paper.

In an effort to keep scaling at the speed of Moores law, novel methods are being developed to facilitate advanced semiconductor manufacturing at the 32nm node and beyond. One such method for enabling the creation of dense pitches beyond the current lithography resolution limit is spacer pitch splitting. This method typically involves patterning a sacrificial gate pattern, then performing a standard spacer deposition and etch back process, after which the sacrificial gate is removed and the remaining spacers themselves are used as the effective mask for the pattern transfer. Some of the key advantages of this process are the ability to create sub-resolution lines and also the improvement in Line Edge Roughness seen on the final pattern. However, there are certain limitations with this process, namely the ability to only pattern lines in one dimension, and also the complexity of the metrology, where the final Critical Dimension result is a function of the litho condition from the sacrificial gate patterning, and also the various film layer depositions as well as the spacer etch back process. Given this complexity, the accurate measurement of not only the spacer width but also the spacer shape is important. In this work we investigate the use of scatterometry techniques to enable these measurements on leading edge devices.

IC manufacturers have a strong demand for transferring a working process from one scanner to another. In an ideal transfer, a reticle set that produces devices within specification on a certain scanner has the same performance on another exposure tool. In real life, however, reticles employ optical proximity correction (OPC) which incorporates by definition the inherent optical fingerprint of a specific exposure tool and process. In order to avoid the additional cost of developing a new OPC model and acquiring a new reticle for each exposure tool, IC manufacturers therefore wish to 'match' the optical fingerprint of their scanners as closely as possible. In this paper, we report on the matching strategy that we developed to perform a tool-to-tool matching. We present experimental matching results for several tool combinations at numerical apertures (NA) 0.75, 0.85 and 1.2. Matching of exposure tools is obtained by determining the sensitivities to scanner parameter variations like NA, Sigma, Focus Drilling, Ellipticity and Dose from wafer data and/or simulations. These sensitivities are used to calculate the optimal scanner parameters for matching the two tools.

Double patterning is recognized as the best candidate for 32 nm half-pitch lithography. Currently pitch splitting processes are being considered for logic processes and spacer processes are being considered for memory. In pitch splitting, errors in overlay between the first and second exposure become CD errors on the final pattern. For this reason, overlay requirements are severe for pitch splitting double patterning. Revised CD and overlay budgets are presented, as well as technical requirements to satisfy these budgets. Spacer processes do not have similar restrictions on overlay, so they can be achieved using current immersion tools. Exposure tool requirements for double patterning are discussed and modifications to current platforms are described.

Low pass filtering taking place in the projection tools used by the IC industry leads to a range of optical proximity effects, OPEs, resulting in undesired characteristics of patterns projected by the scanners. Commonly used scanner imaging models are capable of capturing OPEs driven by the fundamental imaging conditions such as wavelength, illuminator layout, reticle technology, and lens numerical aperture.

An important need in the Optical Proximity Correction (OPC) process is to be able to identify problem correction areas. However, many times when a problem correction area is identified, multiple instances of the same problem occur throughout the correction. This can lead to potentially hundreds or thousands of repeated structures that must be filtered by the development engineer. In some instances, hundreds of thousands of problem areas may be identified, but in reality, all the areas are the same lithographic pattern. One way of identifying repeated patterns in an analysis data base is to use Boolean geometric logic to isolate matching patterns. The problem with this approach is determining what area is the area of process influence. This invariably leads to a conservative analysis of similar patterns, which leads to many repeated failures that are actually the same failure. This study will discuss a solution to this problem using process models and process model approximations to determine if patterns are the same from the point of view of the process. This will be accomplished using the output model intensity, the output model slope, and the pattern response to focus variation. When these three values are the same, it is hypothesized the layout patterns are the same from a process point of view. In addition, the study will discuss methodologies to speed up the model analysis and adjust accuracy and sensitivity.

At advanced technology nodes with extremely low k1 lithography, it is very hard to achieve image fidelity requirements and process window for some layout configurations. Quite often these layouts are within simple design rule constraints for a given technology node. It is important to have these layouts included during early RET flow development. Most of RET developments are based on shrunk layout from the previous technology node, which is possibly not good enough. A better methodology in creating test layout is required for optical proximity correction (OPC) recipe and assists feature development. In this paper we demonstrate the application of programmable test layouts in RET development. Layout pattern libraries are developed and embedded in a layout tool (ICWB). Assessment gauges are generated together with patterns for quick correction accuracy assessment. Several groups of test pattern libraries have been developed based on learning from product patterns and a layout DOE approach. The interaction between layout patterns and OPC recipe has been studied. Correction of a contact layer is quite challenge because of poor convergence and low process window. We developed test pattern library with many different contact configurations. Different OPC schemes are studied on these test layouts. The worst process window patterns are pinpointed for a given illumination condition. Assist features (AF) are frequently placed according to pre-determined rules to improve lithography process window. These rules are usually derived from lithographic models and experiments. Direct validation of AF rules is required at development phase. We use the test layout approach to determine rules in order to eliminate AF printability problem.

Scatter Bar (SBAR) insertion is a computationally expensive operation. SBAR are usually generated rule-based. SBAR rule tables dictate the insertion of SBAR with different SBAR width dependent on the width of the printable main features and the spacing between the main features and SBAR. Optimization of the SBAR rules drives manufactures to ever more complex SBAR tables which increase the runtime. In advanced process nodes, SBAR printing issues, missing SBAR due to clean-up problems and joining SBAR of different width together remain challenging. On the other hand, pixelized inversion methods may yield optimized SBAR solutions, especially in terms of SBAR placement for contact layers, but comes at the expense of significant computational effort and increased mask writing and inspection time. Since OPC changes the spacing between SBAR and main features, an accurate and optimized SBAR solution requires OPC and SBAR optimization to run interactively. This work focuses on both line/space and contact layers To ensure fast SBAR optimization, SBAR placement and SBAR width optimization are separated. SBAR of uniform width are placed fast driven by a simple rule-based table comprising only a single SBAR width. This intermediate SBAR layer is subject into a model-based approach, which fragments the SBAR layer based on proximity with respect to the main features or other SBAR, and assigns measurement sites to each SBAR fragment. A model is used to move each SBAR fragment inward or outward so that the image cut line shows a maximum SBAR intensity closer to a predefined SBAR printing threshold. While the main features are unchanged, several iterations are applied to converge the SBAR fragments. Keeping the SBAR fragments fixed, OPC is applied to the main features. Repeating these steps allows optimization of the SBAR width and the OPC simultaneously. Site based as well as contours based verification methods are applied to ensure that the SBAR printing margin has been significantly improved. The improved SBAR printing margin allows manufactures to apply more aggressive SBAR placement rules, which, in addition to the optimized SBAR width, helps to enlarge the depth of focus, therefore, widen the common process window of the lithography process.

It is common for computational lithography optimization to be performed using the metrics of the simulated aerial image (AI). Using the AI, the wafer-level CD can be estimated in a number of ways, such as thresholding with or without convolution of the AI with a point-spread function. The assumption of such an approach is that the relationship between the AI CD and the resist CD response is linear. However, the properties of resist reaction-diffusion-development yield a process which is highly non-linear. For example, it is well-known that different photoresists produce a different lithographic response to the same aerial image; isofocality, depth-of-focus, exposure latitude, MEF etc. all vary from one resist to another for the same projection optics and mask. Several publications have demonstrated that a well-calibrated physical resist model can be extrapolated to accurately predict the CD and profile response of the resist process over a wide range of optical and process conditions. In this work, the divergence in performance between resist processes and the projected image-in-the resist is explored through simulation.

Double patterning based on existing ArF immersion lithography is considered the most viable option for 32nm and below CMOS node. Most of double patterning approaches previously described require intermediate process steps like as hard mask etching, spacer material deposition, and resist freezing. These additional steps can significantly add to the cost of production applied the double patterning. In this paper, pattern freezing free litho-litho-etch double patterning process is investigated to achieve a narrow pitch imaging without the intermediate processing steps. Pattern freezing free litho-litho-etch double patterning utilizing positive-positive resist combination demonstrated composite pattern generation.

With the decrease in pitch in the line/space patterning, micro-bridge defects have become the major defect in the immersion applications. As a result, reducing micro-bridge defect count is one of the key tasks for mass production of semiconductor devices using immersion lithography for both topcoat and non-topcoat processes. In this paper, we focus on the non-topcoat approach particularly the embedded barrier layer (EBL) technology. The advanced EBL materials discussed in this paper have demonstrated to be able to reduce total defect including micro-bridge defect count to the same level as that of a topcoat process. It was found that the developer solubility of the EBL materials in both bright and dark fields and the contrast of the EBL materials play important roles for reducing overall defectivity.

Merck has developed a range of reactive liquid crystal materials (Reactive Mesogens) that are designed to form thin, birefringent, coatable films for optical applications. Reactive Mesogen (RM) films are typically coated from solution and polymerized in-situ to form thin, optics-grade coatings. Merck RM materials are customized formulations including reactive liquid crystals, surfactants, photoinitiators and other proprietary additives. Merck have optimized the materials to achieve the optimum physical performance in each application. In this paper we focus on the optimization of RM materials to achieve the finest patterning resolution and defined feature shape whilst maintaining good physical properties of the films. Several conventional trade-offs are investigated and circumvented using novel material concepts. Different methods of patterning RM materials are discussed and the merits of each considered. Thermal annealing of non-polymerized regions can create isotropic islands within the polymerized anisotropic matrix. Alternatively, the non polymerized material can be re-dissolved in the coating solvent and rinsed away. Each of these techniques has benefits depending on the processing conditions and these are discussed in depth.

Recent years, resin Black Matrix (BM) for color filter (CF) of LCD have been produced at Optical Density (OD) 4.0/micron. However, making the higher luminance backlight is required because of the display fineness improvement. And the BM with higher OD targeting over OD4.0/micron is desired to prevent light leakage through BM film. In addition, higher sensitivity BM resist development is important to get higher throughput at larger size mother glass applications. But above two requirements is in trade-off relationship because BM resist has to react with very weak light through the BM film. BM resist development is faced on two major technical issues. The first is optical leakage through the CF film with the higher luminance backlights application in LCD to achieve display fineness. And the other is film upsurge at the intersection of BM and RGB film. It is difficult to maintain the uniformity of liquid crystal distribution in the pixel by the lack of uniformity of BM and RGB film and it is one of route cause of optical leakage. There are two solutions to prevent these problems. One is thick film applications of current OD resist with taper shape profile at the intersection with RGB film. It is effective solution to minimize the upsurge of RGB film, but BM film thickness at taper shaped area becomes thinner at the tip of BM film structure. Therefore it is difficult to prevent optical leakage completely with current OD resist. On the other hand, thinner film application with higher OD BM resist, the second solution, is applicable to prevent both the RGB film upsurge and optical leakage issue. The technical keyword of the second solution is the development of BM resist with higher OD and higher sensitivity than current resist. In this paper, we discuss the development of resin BM resists and resist pattern generation for these two technical solutions. In the resist development, we will report the high sensitivity BM resist with 4.0/micron and higher OD for thinner film application.

It is known that the photolithography characteristic of the color resist film depends on the variety of the pigments and the exposure condition. Recently, the color filter containing the high density pigments is hoped to make the wide color gamut LCD panel. Then, it is very important to know the composition of the color resist film and the exposure condition to achieve a good balance between the color characteristic and the photolithography characteristic. In this experiment, it is shown that the photolithography characteristics of Red and Blue resist films don't depend on the exposure illuminance easily in a range narrower than the width of the mask for the reason that the UV light goes into deeply without being absorbed by the pigments. However, in a range wider than the width of the mask or at very low exposure illuminance, their characteristics depend on the exposure illuminance by reason that the amount of the light irradiation decreases and the influence of the inhibition by oxygen becomes larger. On the other hand, it is shown that the photolithography characteristic of Green resist film depends on the exposure illuminance regardless of a range and the exposure illuminance value because the UV light can not go deeply into the coating by being absorbed by pigments in the resist. Thus, it is confirmed that the degree of curing and the pattern profile of color resist film is greatly different according to the composition and exposure condition.

We succeeded in development of SOG materials comprised of cage-type phenyl silsesquioxanes (PSQ) and their alkali soluble derivatives. The alkali soluble silsesquioxane (APSQ) can provide both positive and negative tone photosensitive SOG combination with diazo naphtoquinone (DNQ) and photo-base (acid) agent, respectively. Here we present feature of photolithography process and film properties for our SOG materials.

As semiconductor feature sizes continue to decrease, the phenomena of line edge roughness (LER) becomes more disruptive in chip manufacturing. While many efforts are underway to decrease LER from the photoresist, postdevelop smoothing techniques may be required to continue shrinking chip features economically. This paper reports on one such method employing the use of an ion beam at grazing incidence along the features. This method smooths relatively long spatial length LER, a potential advantage over other smoothing techniques that focus on just small-scale LER. LER reduction numbers using Ne and Ar beams are reported at both short and long spatial wavelength. Variables include beam energy, length of time and angular dependence. LER measurements are taken using Hitachi image analysis software on top-down analytical SEM measurements. Line profile data are taken from cross sectional SEM photographs. Tests have achieved a reduction in LER from 9.8±0.67 nm to 5.5±0.86 nm for 45 nm 1:1 lines using an Ar beam at 500 eV for 6 s at an 85o angle of incidence. A reduction from 10.1±1.07 nm to 6±1.02 nm was shown using an Ar beam at 1000 eV for 4 s at a 60o angle of incidence.

Amorphous Carbon Layer (ACL) and SiON system has been proven to be a good hardmask combination. These layers are formed by a high cost, low throughput CVD process. This paper discloses a reliable, low cost, high throughput process using a simple spin on layer structure. Through manipulation of various parameters, additional BARC layer is eliminated and the process is further simplified to a tri-layer structure. Also, PR/SiON/C-SOH (Carbon-Spin-On-Hardmask) system has been compared to PR / Si-SOH (Si-Spin-On-Hardmask ) / C-SOH system and found their performances are comparable. This indicates the PR / Si-SOH / C-SOH process is an economical yet comparable substitute.

In recent microlithography of semiconductor fabrication, spin-on hardmask (SOH) process continue to gain popularity as it replaces the traditional SiON/ACL hardmask scheme which suffers from high CoO, low productivity, particle contamination, and layer alignment issues. In the SOH process, organic polymer with high carbon content is spin-cast to form a carbon hardmask film. In the previous papers, we reported the development of organic SOH materials and their application in sub-70 nm lithography. In this paper, we describe the synthesis of organic polymers with very high carbon contents (>92 wt.%) and the evaluation of the spin-coated films for the hardmask application. The high carbon content of the polymer ensures improved etch resistance which amounts to >90% of ACL's resistance. However, as the carbon content of the polymers increases, the solubility in common organic solvents becomes lower. Here we report the strategies to improve the solubility of the high carbon content resins and optimization of the film properties for the SOH application.

This work discusses the requirements and performance of Honeywell's middle layer material, UVAS, for trilayer patterning. UVAS is a high Si content polymer synthesized directly from Si containing starting monomer components. The monomers are selected to produce a film that meets the requirements as a middle layer for trilayer patterning and gives us a level of flexibility to adjust the properties of the film to meet the customer's specific photoresist and patterning requirements. Results of simulations of the substrate reflectance versus numerical aperture, UVAS thickness, and under layer film are presented. Immersion lithographic patterning of ArF photoresist line space and contact hole features will be presented. A sequence of SEM images detailing the plasma etch transfer of line space photoresist features through the middle and under layer films comprising the TLP film stack will presented. Excellent etch selectivity between the UVAS and the organic under layer film exists as no edge erosion or faceting is observed as a result of the etch process. The results of simulations of Rsub versus NA, and the thickness of each film comprising a two layer antireflective film stack will also be discussed.

Trilayer stacks with alternating etch selectivity were developed and extensively investigated for high NA immersion lithography at 32nm node and beyond. This paper discusses the fundamental aspects of the Si-containing BARC (Si-BARC) materials with ultra-high silicon content and carbon-rich underlayers that we developed. Designing of materials at a molecular level is presented. It was demonstrated that this fundamental understanding assisted in achieving satisfactory shelf life and excellent coating defect results. Prolith^® simulations using trilayer stacks showed superior reflectivity control for hyper-NA immersion lithography. The impact of high incident angles on substrate reflectivity was analyzed and this paper demonstrated that trilayer scheme provides wider process windows and is more tolerant to topography than conventional single layer BARC. Extensive resist compatibility investigation was conducted and the root causes for poor lithography results were investigated. Excellent 45nm dense lines performance employing the spin-on trilayer stack on a 1.2 NA immersion scanner is reported. In addition, pattern transfers were successfully carried out and the Si-BARC with high silicon content demonstrated outstanding masking property. In comparison to the theoretical %Si values, better correlation with etch selectivity was observed with experimental %Si. Furthermore, this paper addresses the wet rework of trilayer materials and results using Piranha rework are presented. Clean 12in wafers were obtained after reworking trilayer stacks, as evidenced by defect analysis.

The work shown in this paper examines the effect of single and dual BARC on reflectivity at 1.35 NA using reflectivity simulations, coupled with process windows and swing curves, to gauge the effectiveness of reflection control for various BARCs on wafer. The BARC refractive index should be determined by the application, which in this case is the word line gate layer for 40 nm Flash memory. The materials required for best reflection control depends upon the film stack beneath it and the illumination used. An additional constraint is the thickness of the BARC film being scaled to thinner values as required by the future scaling of resist critical dimensions. Results from using two single layer BARCs and a dual organic BARC show what impact reflectivity has on various performances for gates in the center and edge of the array.

In the current semiconductor industry, hardmasks have become essential for successful patterning in many applications. Silicon-based anti-reflective spin-on hardmask (Si-SOH), which can be built by spin-on coating, is desirable in terms of mass production throughput and cost of ownership. As the design rule shrinks, the thickness of photoresist also becomes thinner, which forces the thickness of Si-SOH to be thinner resulting in a tighter thickness margin. In this case, controlling of optical properties of Si-SOH is important in order to obtain low reflectivity in the exposure process. Previously, we reported papers on silicon-based anti-reflective spin-on hardmask materials for 193 nm lithography and immersion ArF lithography. In this paper, the technique for optimization of optical properties, especially n and k values, of Si-SOH is described. To control n and k values, several chromophores were screened and the ratio among them was optimized. Although the amount of chromophores increased and the silicon contents decreased, our etch resistance enhancement technique allowed Si-SOH to have sufficient etch resistance. Characterization of this Si-SOH and lithographic performance using these materials are described in detail.

A photosensitive developer-soluble bottom anti-reflective coating (DBARC) system is described for KrF and ArF lithographic applications. The system contains an acid-degradable branched polymer that is self-crosslinked into a polymeric film after spin coating and baking at high temperature, rendering a solvent-insoluble coating. The DBARC coating is tunable in terms having the appropriate light absorption (k value) and thickness for desirable reflection control. After the exposure of the resist, the DBARC layer decrosslinks into developer-soluble small molecules in the presence of photoacid generator (PAG). Thus the DBARC layer is removed simultaneously with the photoresist in the development process, instead of being etched away in a plasma-etching chamber in the case of traditional BARC layers. The etch budget is significantly improved so that a thin resist can be used for better resolution. Alternatively, the etch step can be omitted in the case of the formation of layers that may be damaged by exposure to plasma.

To obtain high resolution lithography in semiconductor industry for 45 nm node and beyond, 193 nm immersion lithography is a state-of-the-art technology. The hyper NA process in immersion technology requires unique design of bottom antireflective coating (BARC) materials to control reflectivity and improve lithography performance. Based on simulations, high n low k materials are suitable for BARC applications in hyper NA process. This paper describes the principle of the material development of high n low k BARC materials and its applications in hyper NA lithography process. The BARC material contains a dye with absorbance maximum lower than the exposure wavelength, e.g 170-190 nm. The enhancement of n values due to anomalous dispersion was illustrated by dispersion curves of new BARC materials. The relationship of the optical indices of BARC materials at 193 nm with the absorption properties of dyes was investigated. The novel high n low k materials have shown excellent lithography performances under dry and immersion conditions.

In semiconductor manufacturing processes, bubbles (often referred as microbubbles) can be contaminants that reduce manufacturing yield. In photolithography processes, a Point-of-Use filter is used on a clean track system to ensure lower wafer defect level by providing particle and bubble free photochemicals. However, filter changeout often results in significant chemical consumption and tool downtime due to purging of air from the system. This paper describes a technique developed to rapidly eliminate microbubbles during filter startup in a two stage dispense system. The experimental results suggest that by providing a constant pressure to the fluid after wetting the filter, we were able to effectively eliminate microbubbles in the fluid. Therefore, the filter startup process was significantly improved.

In previous studies, we identified filter properties that have a strong effect on microbubble formation on the downstream side of the filter membrane. A new Highly Asymmetric Polyarylsulfone (HAPAS) filter was developed based on the findings. In the current study, we evaluated newly-developed HAPAS filter in environmentally preferred non-PFOS TARC in a laboratory setting. Test results confirmed that microbubble counts downstream of the filter were lower than those of a conventional HDPE filter. Further testing in a manufacturing environment confirmed that HAPAS filtration of TARC at point of use was able to reduce defectivity caused by microbubbles on both unpatterned and patterned wafers, compared with a HDPE filter.

SRAF (sub-resolution assist feature) generation technology has been a popular resolution enhancement technique in photo-lithography past sub-65nm node. It helps to increase the process window, and these are some times called ILT(inverse lithography technology). Also, many studies have been presented on how to determine the best positions of SRAFs, and optimize its size. According to these reports, the generation of SRAF can be formulated as a constrained optimization problem. The constraints are the side lobe suppression and allowable minimum feature size or MRC (mask manufacturing rule check). As we know, bigger SRAF gives better contribution to main feature but susceptible to SRAF side lobe issue. Thus, we finally have no choice but to trade-off the advantages of the ideally optimized mask that contains very complicated SRAF patterns to the layout that has been MRC imposed applied to it. The above dilemma can be resolved by simultaneously using lower dose (high threshold) and cleaning up by smaller MRC. This solution makes the room between threshold (side lobe limitation) and MRC constraint (minimum feature limitation) wider. In order to use smaller MRC restriction without considering the mask writing and inspection issue, it is also appropriate to identify the exact mask writing limitation and find the smart mask constraints that well reflect the mask manufacturability and the e-beam lithography characteristics. In this article, we discuss two main topics on mask optimizations with SRAF. The first topic is on the experimental work to find what behavior of the mask writing ability is in term of several MRC parameters, and we propose more effective MRC constraint for aggressive generation of SRAF. The next topic is on finding the optimum MRC condition in practical case, 3X nm node DRAM contact layer. In fact, it is not easy to encompass the mask writing capability for very complicate real SRAF pattern by using the current MRC constraint based on the only width and space restriction. The test mask for this experimental work includes not only typical split patterns but also real device patterns that are generated by in-house model-based assist feature generation tool. We analyzed the mask writing result for typical patterns and compared the simulation result, and wafer result for real device patterns.

A recent new class of resists referred to as polymer-bound PAG resists, which have slightly increased PAG loading and reduced photo acid diffusion relative to tranditional blended CAR systems have shown promise in improving resolution, faster photospeed, higher stablility and LER. we have developed two kinds of PAG, which are cationic and anionic polymerizable PAGs. One is that the polymer backbone is directly connected with cationic part in PAG and the other is that the polymer backbone is directly connected with anionic part in PAG. In this study we described the synthetic process of polymerizable PAGs and the polymerization process to make PAG-bound polymers and then, the lithography properties of resists composed of PAG-bound polymer were reffed to.

Reflectivity comparison study of bottom anti reflectivity coating (BARC) was investigated at 30nm node devices with same gate width at different pitch sizes. The goal of this study is to elucidate the practical target of reflectivity for high NA immersion lithography especially focusing on the changes in the CD variation. Using double patterning technology (DPT) and single patterning technology (SPT) patterns in high NA systems, we studied the impact of reflectivity to the lithography performance for various ARC thicknesses. A strong dependence of n, k values (of BARC and substrate) on reflectivity was confirmed by simulation. Standing wave effects were investigated by vertical profiles inspection and changes in lithographic performances. Finally, we investigated the critical dimension uniformity (CDU), and line width roughness (LWR) variations for various reflectivities using hard mask substrates. Our experimental and simulation results clearly show that a 0.1% reflectivity target is highly recommendable for the sub-30 nm device process using high NA immersion lithography.

The optical proximity effect (OPE) is one of the most serious problems, as the optical lithography is pushed into the smaller feature size below the exposure wavelength. Some of the typical ways to solve this problem are to use the optical proximity correction (OPC) and the phase shift mask (PSM). However, these sophisticated techniques increase the cost of making masks, as well as the risk of getting defects on the masks. In this study we optimize the annular off-axis illumination (OAI) conditions to reduce the Isolated-Dense bias (IDB), in order to improve the resolution and the depth of focus (DOF) as a solution to fight for OPE. Through the simulation done with AIMS Fab 248 exposure system, the energy distribution on the photo-resist is analyzed with the intensity distribution across the simulated exposure images. The optimization is performed with the aid of Taguchi method. On the basis of the simulation analysis, the optimum optical parameters (the numerical aperture NA, the degree of coherence Sigma, and the ratio of the inner and the outer radii of the rings Annular) are selected to obtain the high resolution and enough DOF to reduce IDB value. The low IDB can be realized by using optimal optical parameters before exposure processes, without using sophisticated OPC and PSM on the masks.

In resolution limited lithography process, the contact hole pattern is one of the most challenging features to be printed on wafer. A lot of lithographers struggle to make robust hole patterns under 45nm node, especially if the contact hole patterns are composed of dense array and isolated hole simultaneously. The strong OAI(Off Axis Illumination) such as dipole is very useful technique to enhance resolution for specific features. However the contact hole formed by dipole illumination usually has elliptical shape and the asymmetric feature leads to increment of chip size. In this paper, we will explore the lithographic feasibility for the coexisting dense array with isolated contact holes and the technical issues are investigated to generate finer contact hole for both dense and isolated feature. Conventional illumination with resist shrinkage technique will be used to generate dense array and isolated contact hole maintaining original shape for the sub-50nm node memory device.

This work demonstrates a methodology for evaluating the multiple feature error budget of NAND-Flash Gate layer and investigates the process capability of the Double Patterning Technology (DPT) options, LELE and Spacer, for NAND Flash 32nm and below. Since the effective k1 limit for DPT is near 0.14 for dense 1D features, three types of ASML scanners are potential candidates for imaging such devices: XT:1400, XT:1700i and XT:1900i. We will present the results of a simulation evaluation of the DPT process capability of these scanners for NAND-Flash Gate layer with 32nm and 22nm half pitch. The DPT capability involves not only lithography but also the subsequent patterning steps of the selected process flow. Moreover, the pattern sensitivity to scanner parameter variations increases with further scaling. It is therefore crucial to take into account the reasonable budgets of scanner dose, focus and overlay errors as well as the error budgets of film deposition, etch and mask registration. This work will not only evaluate the LELE DPT and Spacer feasibility for the mentioned scanners but also analyze the main contributors of CDU in DPT processes and indicate directions we may follow to improve.

193nm immersion and Hyper NA lithography are used at 45nm and beyond. The next generation of lithography will use a new technology such as Double Pattering, EUV or EB. Double patterning is one of the currently acceptable technologies. Three common double pattern techniques are Litho-Etch-Litho-Etch (LELE), freezing, and sidewall (spacer) process. From a technical standpoint LELE is a very promising process, except for the second litho alignment. However, the cost of ownership will be very high because LELE will cost about twice as much as the current single litho patterning process. In order to build up a suitable double patterning technique, many device makers are developing unique processes. Two of these processes are freezing and sidewall. Flash memory makers are diligently investigating the sidewall process by CVD. This is because of the lack of a second litho alignment step, even with its high cost. The high cost of the CVD process can be reduced if a spin on material is used. One of the goals of this paper is to reduce the cost of ownership by using spin on coatings for the sidewall process. Currently we are investigating this approach to control the sidewall width, profile and other properties.

According to ITRS road map, it will be achieved 22 nm half pitch until 2016. However, it is hard to make although EUV, high index immersion. We have positive strategy for 22 nm half pitch with immersion and double patterning and RRP. We can make 22 nm half-pitch with hard mask by using RRP that can shrink trench pattern and double patterning that can get over resolution limitation. Immersion technology can make 44 nm half pitch in NA 1.35. When the developed resist profile can be reflow, so line is increased and space is decreased. It can be 22 nm trench pattern with 66 nm width by using RRP. Hence, we can obtain 66 nm line and 22nm space pattern by etching. And then, we can obtain 22 nm half pitch after doing double patterning. We tried to evaluate this strategy by commercial and home-made simulator.

The demand for more highly integrated semiconductor devices is driving efforts to reduce pattern dimensions in semiconductor lithography. It has been found that 193-nm immersion lithography can achieve smaller patterns without having to modify the infrastructure used for existing state-of-the-art 193-nm dry lithography. As a result, 193-nm immersion lithography is a promising technology for use in mass production processes. Recently, the scanning speed of the exposure stage has been increasing in order to achieve high throughput for mass production. Currently, the topcoat process is one of the promising candidates for this high speed scanning process. On the other hand, the non topcoat resist process is being tested from a C.O.O. (cost of ownership) point of view. However, there are some important points that become apparent, such as specific defect countermeasures and wafer bevel control. Nikon and TEL developed the novel immersion exposure tool and coater/developer system application technology in order to solve these immersion specific issues. In this paper, we examine the process performance using novel immersion exposure tool and coater/developer system.

For lithography technology to support the scaling down of semiconductor devices, 193-nm immersion exposure processing is being introduced to mass-production at a rapid pace. At the same time, there are still many unclear areas and many concerns to be addressed with regards to defects in 193-nm immersion lithography. To make 193-nm immersion lithography technology practical for mass production, it is essential that the defect problems be solved. Importance must be attached to understanding the conditions that give rise to defects and their transference in the steps between lithography and etching processes. It is apparent that double patterning (DP) will be the mainstream technology below 40nm node. It can be assumed that the risk of the defect generation will rise, because the number of the litho processing steps will be increased in DP. Especially, in the case of Litho-Etch-Litho-Etch (LELE) process, the concept of defect transfer becomes more important because etch processing is placed between each litho processing step. In this paper, we use 193-nm immersion lithography processing to examine the defect transference from lithography through the etching process for a representative 45nm metal layer substrate stack for device manufacturing. It will be shown which types of defects transfer from litho to etch and become killer defects.

Considering the usage extension of ArF immersion lithography down to the node of hp 22nm, EUVL should be able to cope with at least the 16 nm and preferably the 11 nm nodes. However, numerical aperture (NA) of projection optics in EUVL exposure tools needs to be around 0.4 which requires the oblique angle of around 8 degrees for the illumination. When one considers that the thickness of multilayer is around 280 nm, the reflectivity drop area at the edge of absorbers has the width of approximately 40 nm that corresponds to the width of 10 nm on wafer. There is another serious problem. Particle check will become extremely difficult for a pellicle-less EUVL mask with smaller feature size. Killer particles cannot be detected by an optical inspection system any longer at 22 nm and smaller. In consideration of all these serious problems, the only simple solution is to increase the mask magnification factor from the conventional 4X to 8X.1-4) Although is has been reported that the throughput of an 8X exposure too is 30-70% compared with that of 4X,5X the throughput can be increased to be equal or even higher than that of 4X when 450 nm wafer is applied.

Focused Ion Beam (FIB) lithography not only can produce features on photoresist, it can also be used to manufacture mold for Nanoimprint. FIB provides fast results with a well focused minimum 7 nm diameter Ga₊ ion beam, and making mold for Nanoimprint with FIB immunes oneself from photoresist issues involved in sub-45 nm large area patterning. However, due to surface charge accumulation, large area patterning often results in displaced and overlapped patterns, similar to e-beam lithography. This displacement occurs in area as small as 5 µm², and is a function of beam dwell time and ion current dose. A small dwell time can lessen this displacement to certain degree if the pattern is small, but fails when the area to be pattern is large. In this paper we present a correct scheme in which the ion beam is check periodically against a pre-drilled mark for beam displacement, and made adjustment in beam control correspondently. In this manner, a large area (10 µm²) pattern of 50 nm squares is successfully demonstrated on a Si wafer.

Generally, rule based optical proximity correction (OPC) together with conventional illumination is used for contact layers, because it is simple to handle and processing times are short. As the design rule is getting smaller, it becomes more difficult to accurately control critical dimension (CD) variation because of influence by nearby contact holes pattern. Especially, random contact hole shows greater amount of CD difference between X and Y direction compared to array contact holes. Several resolution enhancement techniques (RET) were used to resolve this kind of problem, but didn't meet the overall expectations. In this paper, we will present the results for novel contact hole model-based OPC for sub 60nm memory device. First, model calibration method will be proposed for contact holes pattern, which utilizes two thousands of real contact holes pattern to improve model accuracy in full chip. Second, verification method will be proposed to check weak points on full chip using model based verification. Finally, method for further enhancing CD variation within 5nm for model based OPC will be discussed using Die-to-Database Verification.

Haze occurrence is time-dependent, also known as degradation Haze. Thereby optimum time of purge operation became a significant reference index of mask operation for Haze resistance in fabrication. In advanced study, a concept of mask Q-time ("Q-time" is abbreviated from Queue time) was conducted to analyze the optimization of purge operation. TLV ("TLV" is abbreviated from Threshold Limit Value) of Q-time is a novel review index, a crucial index for Haze prevention and control originated in a new analysis method that have never published. Mask Q-time analysis method includes two analytic models, one of models is HDB ("HDB" is abbreviated from Haze Detonation Baseline) for the analysis of optimum purge operation in Haze defect resistance before Haze occurrence, HDB was defined by the ratio of wafer accumulation over the TLV of HDB (wafer/wafer) and the ratio of wafer dispersion over the TLV of HDB (frequency/frequency). The other analytic model, HGB ("HGB" is abbreviated from Haze Growth Baseline) for the analysis of optimum collocation of absorbent adsorption and purge operation in Haze defect growth control after Haze occurrence, HGB was defined by two factors, the ratio of wafer exposure(min/min) and the ratio of mask purge operation(min/min).

The downscaling of the feature size and pitches of the semi-conductor device requires enough process window and good CDU of exposure field for improvement of device characteristics and high yield. Recently several DBMs (Design Based Metrologies) are introduced for the wafer verification and feed back to for DFM and process control. The major applications of DBM are OPC feed back, process window qualification and advanced process control feed back. With these tools, since the applied tool in this procedure uses e-beam scan method with database of design layout like other ones, more precise and quick verification can be done. In this work the process window qualification procedure will be discussed in connection with EDA simulation results and then method for obtaining good CDU will be introduced. DoseMapperTM application has been introduced for better field CDU control, but it is difficult to fully correct large field with limited data from normal CD SEM methodology. New DBM has strong points in collecting lots of data required for large field correction with good repeatability (Intra / Inter field).

This study proposes an integrated optical system for flat panel display (FPD) substrate inspection. For such a system, auto-focusing is a challenging problem since the microscope magnification ratio is as large as 10X to 50X and the corresponding depth of field (DOF) can thus reduced to 5 µm. Considering its low-cost and its capability in maintaining the depth of field that may be deteriorated by the increase of magnification ratio, this work uses the digital versatile disc (DVD) pickup head is used as the auto-focusing sensor. To verify the auto focus can be achieved. We construct experiment to simulate the real vibration. Change different position from lens to FPD substrate DVD calculate focus error signal (FES) to control PZT stage return to focus position immediately in 0.5 sec.

With recently semiconductor manufacturers Critical Dimension shrink down to 70nm and beyond, I-line layer CD would approach to it's resolution limitation. CD uniformity controling will be strongly influenced by developing process. Regarding I-line layer developing process, CD uniformity is always varying with various developing parameters setting (as nozzle design, developing time, pulse spin, etc).

Recently, the dramatic acceleration in dimensional shrink of DRAM memory devices has been observed. For sub 60 nm memory device, we suggest the following method of optical proximity correction (OPC) to enhance the critical dimension uniformity (CDU). In order to enhance CD variation of each transistor, hundreds of thousand transistor CD data were used through design based metrology (DBM) system. In a traditional OPC modeling method, it is difficult to realize enhancement of CD variation on chip because of the limitation of OPC feedback data. Even though optical properties are surely understood from recent computational lithography models, there are so many abnormalities like mask effect, thermal effect from the wafer process, and etch bias variation of the etching process. Especially, etch bias is too complicate to predict since it is related to variations such as space among adjacent patterns, the density of neighboring patterns and so on. In this paper, process proximity correction (PPC) adopting the pattern to pattern matching method is used with huge amount of CD data from real wafer. This is the method which corrects CD bias with respect to each pattern by matching the same coordinates. New PPC method for enhancement of full chip CD variation is proposed which automatically corrects off-targeted feature by using full chip CD measurement data of DBM system. Thus, gate CDU of sub 60 nm node is reduced by using new PPC method. Analysis showed that our novel PPC method enhanced CD variation of full chip up to 20 percent.

The imaging performances of XY linear and TE Azimuthal polarization were compared by thin mask approximation and rigorous 3D mask simulation. The simulations were performed for 40nm and 44nm half pitch patterns with a hyper NA (1.35) system. Each polarization state was assumed to have a parametric DOP (degree of polarization) value that was set to 0.95. Rotated dipole illuminators of several angles were used for the associated tilted patterns to see the imaging impact by IPS (intensity in the preferred state of polarization) change in the process with XY linear polarization that has a fixed angle of polarization. The difference in performance between two polarization modes were compared by NILS and DOF margin. Additionally, the imaging quality of BIM (binary intensity mask) with polarization beam was studied to that of att-PSM at given process conditions. Two types of available BIM masks of different thickness were applied to simulation to understand 3D mask simulation impact on the imaging contrast and process margin. The estimation of two-diffraction beam balance was performed to explain the imaging simulation as well. The polarization sensitivities of NILS and CD change by DOP were found for each feature with given exposure conditions. The main purpose of this study is to understand how much overestimation or underestimation of conventional thin mask simulation could be combined in the process simulation by comparing rigorous 3D mask consideration.

Now it comes to the 45nm technology node, which should be the first generation of the immersion micro-lithography. And the brand-new lithography tool makes many optical effects, which can be ignored at 90nm and 65nm nodes, now have significant impact on the pattern transmission process from design to silicon. Among all the effects, one that needs to be pay attention to is the mask pellicle effect's impact on the critical dimension variation. With the implement of hyper-NA lithography tools, light transmits the mask pellicle vertically is not a good approximation now, and the image blurring induced by the mask pellicle should be taken into account in the computational microlithography. In this works, we investigate how the mask pellicle impacts the accuracy of the OPC model. And we will show that considering the extremely tight critical dimension control spec for 45nm generation node, to take the mask pellicle effect into the OPC model now becomes necessary.

We applied the immersion lithography to get 32 nm node pattern with 1.55 NA, without using double exposure / double patterning. A chromeless phase shift mask is compared with an attenuated phase shift mask to make 32 nm dense 1:1 line and space pattern. We compared the aerial image, normalized image log slope, exposure latitude, and depth of focus for each mask type in order to see the effect of the post exposure bake and acid diffusion length. The process window shrinks fast if the diffusion length is larger than 10 nm for both mask types. However, up to 20 nm diffusion length, 32 nm can be processible if the exposure latitude of 5% is used in production.

One of the most important factors in ArF resist development is a resin platform, which dominates a lot of parts of resist characteristics. It has been much changed in order to improve their physical properties such as resolution, pattern profile, etch resistance and line edge roughness. Through the low etch resistance in ArF initial (meth)acryl type copolymer and low transmittance in COMA type copolymer most researchers were interested in developing of (meth)acryl type copolymer again for ArF photoresist. On the other hand, we have studied various polymer platforms suitable ArF photoresist except for meth(acryl) type copolymer. As a result of this study we had developed ROMA type polymers and cycloolefin-(meth)acryl type copolymers. Among the polymers cycloolefin-(meth)acryl type copolymer has many attractions such as etch roughness, resist reflow which needs low glass transition temperature and solvent solubility. In this study, we intend to find out cycloolefin-(meth)acryl copolymer characteristics compared with (meth)acryl copolymer. And, we have tried to find out any differences between acrylate type copolymer and cycloolefin-(meth)acrylate type copolymer with various evaluation results. As a result of this study we are going to talk about the reason that the resist using acrylate type copolymer and cycloolefin-(meth)acryl type copolymer show good pattern profile while acrylate type copolymer show poor pattern profile. We also intend to explain the role of cycloolefin as a function of molecular weight variation and substitution ratio variation of cycloolefin in cycloolefin-(meth)acrylate resin.One of the most important factors in ArF resist development is a resin platform, which dominates a lot of parts of resist characteristics. It has been much changed in order to improve their physical properties such as resolution, pattern profile, etch resistance and line edge roughness. Through the low etch resistance in ArF initial (meth)acryl type copolymer and low transmittance in COMA type copolymer most researchers were interested in developing of (meth)acryl type copolymer again for ArF photoresist. On the other hand, we have studied various polymer platforms suitable ArF photoresist except for meth(acryl) type copolymer. As a result of this study we had developed ROMA type polymers and cycloolefin-(meth)acryl type copolymers. Among the polymers cycloolefin-(meth)acryl type copolymer has many attractions such as etch roughness, resist reflow which needs low glass transition temperature and solvent solubility. In this study, we intend to find out cycloolefin-(meth)acryl copolymer characteristics compared with (meth)acryl copolymer. And, we have tried to find out any differences between acrylate type copolymer and cycloolefin-(meth)acrylate type copolymer with various evaluation results. As a result of this study we are going to talk about the reason that the resist using acrylate type copolymer and cycloolefin-(meth)acryl type copolymer show good pattern profile while acrylate type copolymer show poor pattern profile. We also intend to explain the role of cycloolefin as a function of molecular weight variation and substitution ratio variation of cycloolefin in cycloolefin-(meth)acrylate resin.

Pursuit of lower k₁ for pushing the resolution limit becomes one of the most demanding tasks to meet stringent patterning requirements in next generation lithography. Particularly, the patterning of densely packed array devices with periodic and symmetric features is among the most challenging missions to enable high density memory chips to quickly move forward as projected by Moore's Law. As dictated by the physical limitation of optical system design, current immersion scanners are not capable of reliably printing feature sizes down to sub-40nm regime unless resorting to high index fluids or other effective Resolution Enhancement Techniques (RETs). Fortunately, recent prosperous progress in double patterning technique seems to give realistic hope as a straightforward bridge between the current immersion scanners [1] and the relatively immature EUV scanners [2]. State-of-the-art double patterning technique [3] includes the well known LLE (Litho-Litho-Etch) [4], LELE (Litho-Etch-Litho-Etch) [5], self-aligned [6] and other approaches [7]. Among them the self-aligned approach is regarded as more appropriated for mass production of high density arrays due to less concerned of overlay budget [8]. In this paper, we studied the integrated lithography performance of one innovative self-aligned double patterning scheme for the demonstration of sub-40nm capability by the use of the most advanced 193nm dry scanner. In addition, silicon containing bottom reflective coating (BARC) was employed for the CD trimming in order to optimize the lithography & etch process windows [9]. A 37.5nm half-pitch L/S memory array with well controlled line edge roughness (LER) was successfully demonstrated in this work by the above mentioned selfaligned spacer approach. The equivalent k₁~0.146 was readily achieved without too much complex integration, which is especially suitable for the future high density memory arrays as in FLASH or DRAM.

In order to achieve miniaturization of the device, and still following device design rules, the photo-resist film thickness has decreased. The thinner photo-resist thickness will improve the resolution limit and prevent the pattern collapse issue. In order to solve these problems a multilayer process is used that has several advantages over previous process designs: reflectivity control in hyper-NA lithography process, decreasing LWR, and the viewpoint of lithographic process margin. The multilayer process consists of three layers: layer one is patterned photo-resist, the second layer is Si-ARC (Si contented Anti Reflective Coatings), and the third layer is SOC (Spin on Carbon) also known as underlayer. There are two processes to deposit Si-ARC and SOC, the first is by spin coating with either a track or spin coater, the second is with a Chemical Vapor Deposition (CVD). From a cost of ownership standpoint the spin on process is better. In the development of spin on Si-ARC and SOC materials it is important to consider the resist profile and the shelf life stabilities. Another important attribute to consider is the etching characteristics of the material. For the Si-ARC the main attribute when determining etch rate is the Si content and for the SOC material the main attribute is the C content in the material. One problem with the spin on multilayer process is resist profile and this paper will examine this problem along with the characteristics of developed material is described.

Control of circuit CD in a photolithographic process has become increasingly important, particularly for those advanced nodes below 45nm because it influences device performances greatly. The variation of circuit CD depends on many factors, for example, CD uniformity on reticles, focus, lens aberrations, partial coherence, photoresist performance and LASER spectral bandwidth. In this paper, we focus on LASER spectral bandwidth effects to reduce circuit CD variation. High-volume products of a leading technology node are examined and a novel LASER control function: Gas Lifetime eXtenstion (GLX) is implemented to obtain stable LASER bandwidth. The LASER bandwidth variation was stabilized by changing laser F2 gas concentration through advanced control algorithm and signal process techniques. Product photo-pattern CD variation and device electrical performances will be examined to confirm the benefits of the LASER bandwidth stabilization.

Tighter CD control requirements of the smaller devices in modern semiconductor products demand control of all potential sources of change in imaging characteristics. Bandwidth of ArF lasers is known to be one of the important parameters to be controlled to improve CD control of wafers. CD changes of Device Critical Patterns for memory products, for example spacing of DRAM isolation patterns, due to laser bandwidth changes were investigated through simulations. The purpose of the simulation study was to find out if there are optimum combinations of layout and illumination setting, if variations can be compensated by illumination adjustments and if the bandwidth performance of the laser meets requirements. The simulations were carried out using Cymer proprietary methods for high accuracy using improved laser spectrum sampling techniques[1]. Different CD behavior was observed for different combinations of pattern layout, illumination and bandwidth. Preferred illumination settings were found which suppress CD changes caused by bandwidth variation, especially for diffusion layer of DRAM layouts. Adjustment of illumination settings was demonstrated to cancel out CD shifts due to bandwidth change for the diffusion layer case. For all example cases, which demonstrated typical DRAM product conditions, simulation verified that the amount of CD shift can be controlled within allowed tolerances if Cymer's ABS technology was used for bandwidth control.

The etch loading effect from wafer center to wafer edge results in worse Bit-line Contact layer (CB) to Gate Conductor layer (GC) overlay alignment performance at the wafer edge which directly impacts device yield. One workaround for this is to introduce additional image shifts during exposure at the edge of the wafer however this will reduce throughput due to the extra time required for wafer measurement (additional leveling scans) and extra exposure time (additional image). We demonstrate a new method which can avoid this overhead using Correction Per Exposure (CPE). We are proposing to use CPE with manually generated overlay corrections. In this way, we are achieving the necessary wafer-edge overlay compensation, and there is no throughput-loss because there is no extra-routing.