This PDF file contains the front matter associated with SPIE Proceedings Volume 6924, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and the Conference Committee listing.

In the last 35 years modeling of projection printing has undergone many paradigm shifts in physical models, computational engines, algorithms and opportunities. The trigger event for the first quantitative positive resist Dill model was the development and application of automated thin-film measurement equipment. The use of partial coherence which helps imaging also complicates the understanding and necessitates the use of simulation to guide lithography practice. Simulation has also played an important role in discovery (intensity imbalance in phase-shifting masks), invention (self-interferometric mask monitors) and creation of analysis techniques (first-cut accurate fast-CAD). The current challenges and growth areas for simulation include calibration, synergy with metrology, electronic self-testing and linking circuit design and fabrication.

Double patterning technology (DPT) is one of the main options for printing logic devices with half-pitch less than 45nm; and flash and DRAM memory devices with half-pitch less than 40nm. DPT methods decompose the original design intent into two individual masking layers which are each patterned using single exposures and existing 193nm lithography tools. The results of the individual patterning layers combine to re-create the design intent pattern on the wafer. In this paper we study interactions of DPT with lithography, masks synthesis and physical design flows. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step which will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons where required; and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers.

Double patterning has emerged as the likely lithography technology to bridge the gap between water-based ArF immersion lithography and EUV. The adoption of double patterning is driven by the accelerated timing of the introduction of device shrinks below 40nm half pitch, especially for NAND flash. With scaling, increased device sensitivity to parameter variations puts extreme pressure on controlling overlay and critical dimension uniformity. Double patterning also makes unique demands on overlay and CDU. Realizing that there is no further increase in NA past the current 1.35 on the horizon, the focus has shifted from a straight shrink using the newest tool to learning how to reduce the effective k₁ through improvements to the tool's control of CDU and overlay, as well as innovative RET, mask, and process technology. In double patterning lithography, CDU and overlay are complex and entangled errors. In an approach where the pattern is split into two masks and recombined in successive lithography and etch steps, a line or space width is defined by edges placed at separate masks. In an approach where double patterning is achieved by self-aligned processes, CD error at the first sacrificial mask will translate into pattern placement errors in the final pattern. In all approaches, it is crucial to understand how these errors interact so that the combined effects can be minimized through proper tool controls, mask OPC and split algorithms, and process choices. Without aggressive actions, the complexity of this problem combined with the economic drawbacks of using multiple masking steps to define critical device layers threaten to slow overall device shrink rates. This paper will explore the main sources of critical dimension and overlay errors in double patterning lithography and will point out directions we may follow to make this an effective manufacturing solution.

We constructed CD budget for spacer patterning technology which is one of the strongest candidates in double patterning technologies for below 3x nm half pitch generations. In the CD budgeting, three patterning portions of grid patterns should be considered, namely, "line", "paired space" and "adjoined space", because they have individual process error sources that affect CD variations. Analysis of the patterning process flow revealed that the amount of CD variations for positive type spacer patterning technology was in the order of "adjoined space" > "paired space" > "line". Also, the experimental verifications in CD variations substantiated the constructed CD budget. From the viewpoint of design for manufacturability (DfM), these process features should be taken into account in the device engineering. Therefore, for the successful implementation of spacer patterning technology into high-end devices, we propose a cross- functional development scheme encompassing device technologies and process technologies using the constructed CD budget.

Double patterning lithography - either with two litho and etch steps or through the use of a sacrificial spacer layer, have equal complexity and particularly tight requirements on CDU and Overlay. Both techniques pose difficult challenges to process control, metrology and integration, but seem feasible for the 32nm node. In this paper, we report results in exploring CDU and overlay performance at 32nm 1/2 pitch resolution of two double patterning technology options, Dual Photo Etch, LELE and sidewall spacer with sacrificial layer. We discuss specific aspects of CD control present in any double patterning lithography, the existence of multiple populations of lines and spaces, with overlay becoming part of CDU budget. The existence of multiple and generally uncorrelated CD populations, demands utilization of full field and full wafer corrections to bring together the CDU of these multiple populations in order to meet comparable 10% CDU as in single exposure. We present experimental results of interfield and intrafield CD and overlay statistical and spatial distributions confirming capability to improve these distributions to meet dimensional and overlay control levels required by 32nm node. After compensation, we achieved a CDU control for each population, of 2nm or better and 3nm overlay on multiple wafers and multiple state of art, hyper NA immersion scanners. Results confirmed our assumptions for existence of multiple CDU populations entangled overlay into CDU.

Double Patterning is investigated at IMEC as a timely solution to meet the 32nm node requirements. It further extends the use of water immersion lithography at its maximum numerical aperture NA=1.35. The aim of DP is to make dense features possible by splitting a design into two more sparse designs and by recombining into the target pattern through a double patterning flow (stitching). Independently of the implementation by the EDA vendors and designers, we discuss some guidelines for split and for DP-compliant design to ensure a robust stitching through process variations. We focus more specifically on the first metal interconnect patterning layer (metal1) for random logic applications. We use both simulations and experiments to study the patterning of 2D split test patterns varied in a systematic way.

Lithography becomes much more challenging when CD shrinks to 22nm nodes. Since EUV is not ready, double patterning combined with Resolution Enhancement Technology (RET) such as shrink techniques seems to be the most possible solution. Companies such as TSMC^[1] and IBM^[2] etc. are pushing out EUV to extend immersion ArF lithography to 32nm/22nm nodes. Last year, we presented our development work on 32nm node contact (50nm hole at 100nm pitch) using dry ArF lithography by double patterning with SAFIER shrink process[3]. To continue the work, we further extend our dry litho capability towards the 22nm node. We demonstrated double patterning capability of 40nm holes at 80nm pitch using ASML XT1400E scanner. It seems difficult to print pitches below 140nm on dry scanner in single exposure which is transferred into 70nm pitch with double patterning. To push the resolution to 22nm node and beyond, we developed ArF immersion process on ASML XT1700i-P system at the College of Nanoscale Science and Engineering (Albany, NY) combined with a SAFIER process. We achieved single exposure process capability of 25nm holes at 128nm pitch after shrink. It enables us to print ~25nm holes at pitch of 64nm with double patterning. Two types of hard mask (HM), i.e. TIN and a-Si were used in both dry and immersion ArF DP processes. The double patterning process consists of two HM litho-shrink-etch steps. The dense feature is designed into two complementary parts on two masks such that the density is reduced by half and minimum pitch is increased by at least a factor of 21/2 depending on design. The complete pattern is formed after the two HM litho-shrink-etch steps are finished.

Variation in the critical dimension (CD) of a transistor is a primary concern for advanced lithography. Because variation from sources such as corner rounding or line edge roughness does not scale with CD, variability in transistor performance increases with scaling and may impact the timing or even the functionality of critical circuits such as static random access memories (SRAM) and ring oscillators. Spacer lithography is an attractive patterning method for future technology nodes, because its use of a very uniform and controllable chemical vapor deposition (CVD) step allows for the definition of very narrow lines with low variation and reduced pitch^1,2. In practice, however, the possible pitch reductions are limited by the need for conventional lithography to produce negative features (e.g., trenches and holes) and increasing CD variability with iterated spacer processing. In this work, an extension to spacer lithography is presented to overcome these limitations. Negative features down to 30nm in width are fabricated using spacer-defined features. A multi-tiered hard mask process is also presented to enable eight-fold pitch reduction with no increase in CD variation. In combination, these processes enable ultra-dense circuit integration for regular layouts.

The spacer patterning technique (SPT) is well known as one of the methods expanding the resolution limit and mainly useful for patterning line & space of memory device. Although contact array could be achieved by both spacer patterning technique and double exposure & etch technique (DEET) ¹, the former would be preferable to the latter by the issues of overlay burden and resolution limit of isolated contact. The process procedure for contact array is similar to that for line & space which involves the 1st mask exposure, etch, carbon polymer deposition, the 2nd mask exposure and etch step sequentially. With SPT, it would be possible to realize contact array of 30nm half pitch including 30nm isolated contact as well as line & space of 30nm half pitch.

A double patterning (DP) process is introduced with application for advanced technology nodes. This DP technique is enabled by a novel low-temperature pulsed deposition layer (PDL^TM) oxide film which is deposited directly on patterned photoresist. In this article, we will report the results of fabrication of sub-50nm features on a 100nm pitch by the PDL-spacer DP process using 0.85 NA dry ArF lithography. This result represents the potential of the PDL-based DP to significantly enhance the resolution of the patterning process beyond the limits of optical lithography. Components of CD variance for this spacer DP scheme will be discussed.

Novel RET-Pixelated Phase Mask (PPM) is proposed as a novel Resolution Enhancement Technique (RET). PPM is made of pixels of various phases with lateral dimensions significantly smaller than the illuminating radiation wavelength. Such PPM with a singular choice of pixel dimensions acts as a mask with variable phase and transmission due to radiation scattering and attenuation on pixel features with the effective intensity and phase modulated by the pixel layout. Key properties of the pixelated phase masks, the steps for their practical realization, and the benefits to random logic products discussed. Wafer patterning performance and comparative functional yield results obtained for a 65nm node microprocessor patterned with PPM, as well as current PPM limitations are also presented.

In this paper, a new resolution enhancement technique named 2D-TCC technique is proposed. This method can enhance resolution of line patterns as well as that of contact hole patterns by the use of an approximate aerial image. The aerial image, which is obtained by 2D-TCC calculation, expresses the degree of coherence at the image plane of a projection optic considering mask transmission at the object plane. OPC of desired patterns and placement of assist patterns can be simultaneously performed according to an approximate aerial image called a 2D-TCC map. Fast calculation due to truncation of a series in calculating an aerial image is another advantage. Results of mask optimization for various line patterns and the validity of the 2D-TCC technique by simulations and experiments are reported.

In this paper, we will present comparison of attenuated phase shift mask and binary intensity mask at hyper-NA immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for polarized illumination in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of binary intensity mask are used for this experiment; those are ArF att.PSM ( MoSi:Å ), thick Cr ( 1030Å ) BIM (Binary Intensity Mask), thin Cr ( 590Å ) BIM and multi layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA immersion scanner are performed to study influence of mask structure, process margin and effect of polarization. Two types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with contact hole shape. Line and space pattern is also studied through 38nm to 50nm half pitch for this experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE is also used in order to study the influence of mask structure and polarization effect through rigorous EMF simulation. Transmission and polarization effects of zero and first diffraction order are simulated for both att.PSM and BIM. First and zero diffraction order polarization are shown to be influenced by the structure of masking film. As pattern size on mask decreases to the level of exposure wavelength, incident light will interact with mask pattern, and then transmittance changes for mask structure. Optimum mask bias is one of the important factors for lithographic performance. In the case of att.PSM, negative bias shows higher image contrast than positive one, but in case of binary intensity mask, positive bias shows better performance than negative one. This is caused by balance of amplitude between first diffraction order and zero diffraction order light. Process windows and mask error enhancement factors are measured with respect to various design rules, i.e., different k1 levels at fixed NA. In the case of one dimensional line and space pattern, thick Cr BIM shows the best performance through various pitches. But in case of two dimensional DRAM cell pattern, it is difficult to find out the advantage of BIM for sub-45nm. It needs further study for two dimensional patterns. Finally, it was observed that thick Cr binary intensity mask for sub-45nm has advantage for one dimensional line and space pattern.

This work describes the advantages, tolerances and integration issues of using Pixelated Phase Masks for patterning logic interconnect layers. Pixelated Phase Masks (PPMs) can act as variable high-transmission attenuated phase shift masks where the pixelated phase configuration simultaneously optimizes OPC and SRAF generation. Thick mask effects help enable PPMs by allowing larger minimum pixel sizes and phase designs with near equal sized zero and piphase regions. PPMs with a 3-tone pixel mask (un-etched glass, etched glass, chrome) offer more flexible patterning capability compared to 2-tone pixel mask (no chrome) style but at the detriment of a more complex mask making process. We describe the issues and opportunities associated with using PPMs for patterning a 65nm generation first level metal layer of a micro-processor.

The use of transverse electric (TE) polarization has dominated illumination schemes as selective polarization is used for high-NA patterning. The benefits of TE polarization are clear - the interference of diffracted beams remains absolute at oblique angles. Transverse magnetic (TM) polarization is usually considered less desirable as imaging modulation from interference at large angle falls off rapidly as the 1/cosθ. Significant potential remains, however, for the use of TM polarization at large angles when its reflection component is utilized. By controlling the resist/substrate interface reflectivity, high modulation for TM polarization can be maintained for angles up to 90° in the resist. This can potentially impact the design of illumination away from most recent TE-only schemes for oblique imaging angles (high NA). We demonstrate several cases of TM illumination combined with tuned substrate reflectivity for 0.93NA, 1.20NA, and 1.35NA and compare results to TE and unpolarized cases. The goal is to achieve a flat response through polarization at large imaging angles. An additional application of TM illumination is its potential use for double patterning. As double patterning and double exposure approaches are sought in order to meet the needs of 32nm device generations and beyond, materials and process engineering challenges become prohibitive. We have devised a method for frequency doubling in a single exposure using an unconventional means of polarization selection and by making use of the reflective component produced at the photoresist/substrate interface. In doing so, patterns can be deposited into a photoresist film with double density. As an example, using a projection system numerical aperture of 1.20, with water as an immersion fluid, and a conventional polyacrylate 193nm photoresist, pattern resolution at 20nm half-pitch are obtainable (which is 0.125lambda/NA). The process to transfer this geometry into a hardmask layer uses conventional materials, including the photoresist layer and thin film silicon oxide based materials.

As the industry hits a road block with RETs that attempt to aggressively scale k1, we propose to extend the life of optical lithography by a complete co-optimization between circuit choices, layout patterns and lithography. We demonstrate that the judicious selection of a small number of layout patterns along with the appropriate circuit topologies would not only enable k1 relaxation but also efficient implementation of circuits. Additionally, in this paper, we discuss the use of regular design fabrics to extend the life of current generation lithography equipment. We will introduce the Front End of Line (FEOL) limited regular design fabric. The metal 1 patterns for this fabric are selected such that we can utilize a 1.2 NA 32nm metal 1 lithography process without any area penalty with respect to standard cells with conventional design rules, which require a 32nm metal 1 process with a rather unrealistic k1 of 0.35 while using a more advanced 1.35 NA tool. We also demonstrate simulation results on 2-dimensional layout patterns. The results suggest that smart selection of layout patterns can enable the extension of single exposure lithography to a 32nm production lithography process.

The imaging of Contact Hole (CH) layouts is one of the most challenging tasks in hyper-NA lithography. Contact Hole layouts can be printed using different illumination conditions, but an illumination condition that provides good imaging at dense pitches (such as Quasar or Quadrupole illumination), will usually suffer from poor image contrast and Depth of Focus (DOF) towards the more isolated pitches. Assist Features (AF) can be used to improve the imaging of more isolated contact holes, but for a random CH layout, an AF placement rule would have to be developed for every CH configuration in the design. This makes optimal AF placement an almost impossible task for random layouts when using rule-based AF placement. We have used an inverse lithography technique by Mentor Graphics, to treat a random contact hole layout (drawn at minimal pitch 115nm) for imaging at NA 1.35. The combination of the dense 115nm pitch and available NA of 1.35 makes the use of Quasar illumination necessary, and the treatment of the clip with inverse lithography automatically generated optimal (model-based) AF for all geometries in the design. Because the inverse lithography solution consists of smooth shapes rather than rectangles, mask manufacturability becomes a concern. The algorithm allows simplification of the smooth shapes into rectangles and greatly improves mask write time. Wafer prints of clips treated with inverse lithography at NA 1.35 confirm the benefit of the assist features.

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um² area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

Pattern matching methods are examined as fast-CAD tools for full-chip across process window examination of postdecomposition double patterning layouts. The goal is to demonstrate the ability to anticipate lithographic weakness due to many sources. This includes the decomposition strategy itself, OPC of individual sub-layers, focus-exposure process window and illumination. This study is an intermediate step to using fast-CAD assessment tools within pattern decomposition algorithms to guide decisions based on lateral influences instead of rules. The accuracy of the pattern matcher as a method for hot spot detection is investigated, and a model relating coma match factors and edge movement is refined to have an R² value of 0.95. The validity of the pattern matcher is explored by relating pre-OPC matches to post-OPC matches, and by showing that the lateral influence functions for Z₀ and Z₃ have high matches at distinct locations, implying that OPC which corrects for one of Z₀ and _Z3 will not necessarily correct for the other. The pattern matcher is run on a post decomposition layout and locations are identified with high variability under coma, and their sensitivity is verified with aerial image simulations. For one such example, a different split is made and the match factor drops by 55%.

Double patterning is used to scale designs below k1 factors that can be obtained with single patterning. Because of the double litho and etch steps, however, this is an expensive and time consuming technique. Spacer defined double patterning, which is commonly used to shrink regular dense patterns as used in memory applications, is an expensive technique because of the many deposition and etch steps that are required. In this paper, we propose several alternative process flows which can reduce the cost-of-ownership by eliminating the intermediate etch step in a double litho, double etch for line/space patterns, and replace it by a process step in the track only. These alternative process flows use thermal freezing resist, positive/negative resist and coating a freezing material. For these materials 32nm node logic patterning can be demonstrated, and even 32nm half pitch can be patterned already with one technique. As alternative technique to spacer defined double patterning, dual tone development is proposed, which can generate pitch doubling in resist using a single exposure. Proof-of-concept of this technique is shown experimentally.

Double patterning based on litho-etch-litho-etch techniques requires the fabrication of small lines or of small spaces after first patterning. If spacer techniques are used for pitch fragmentation small lines are needed as carrier in dense arrays. In any case the CD control is crucial. Focus of this paper is the patterning of small lines with bilayer resist in comparison with single layer resist as pre-requisite for both methods, for various litho conditions. The basic suitability of a bilayer patterning has been demonstrated at k1=0.146 at half pitch of 37.5nm with a sufficient process window and a good CD uniformity after litho and after etch. Single layer resists suffer from pattern collapse and resist thickness loss at defocus if a CD trim by litho "overexposure" is applied. This results in deficiency of masking during etch, although the resist profiles and litho process windows look perfect. If a CD trim is achieved by an etch process the CDU is diminished and the minimum patterned space is enlarged compared to bilayer, due the widening by trim etch. The bilayer resist for 193nm dry lithography showed convincing overall performance. First results with 193nm immersion bilayer look also promising but shows grass formation.

Double patterning (DP) has now become a fixture on the development roadmaps of many device manufacturers for half pitches of 32 nm and beyond. Depending on the device feature, different types of DP and double exposure (DE) are being considered. This paper focuses on the requirements of the most complex forms of DP, pitch splitting, where line density is doubled through two exposures, and sidewall processes, where a deposition process is used to achieve the final pattern. Budgets for CD uniformity and overlay are presented along with tool and process requirements to achieve these budgets. Experimental results showing 45 nm lines and spaces using dry ArF lithography with a k1 factor of 0.20 are presented to highlight some of the challenges. Finally, alternatives to double patterning are presented.

In June 2007, Intel announced a new pixelated mask technology. This technology was created to address the problem caused by the growing gap between the lithography wavelength and the feature sizes patterned with it. As this gap has increased, the quality of the image has deteriorated. About a decade ago, Optical Proximity Correction (OPC) was introduced to bridge this gap, but as this gap continued to increase, one could not rely on the same basic set of techniques to maintain image quality. The computational lithography group at Intel sought to alleviate this problem by experimenting with additional degrees of freedom within the mask. This paper describes the resulting pixelated mask technology, and some of the computational methods used to create it. The first key element of this technology is a thick mask model. We realized very early in the development that, unlike traditional OPC methods, the pixelated mask would require a very accurate thick mask model. Whereas in the traditional methods, one can use the relatively coarse approximations such as the boundary layer method, use of such techniques resulted not just in incorrect sizing of parts of the pattern, but in whole features missing. We built on top of previously published domain decomposition methods, and incorporated limitations of the mask manufacturing process, to create an accurate thick mask model. Several additional computational techniques were invoked to substantially increase the speed of this method to a point that it was feasible for full chip tapeout. A second key element of the computational scheme was the comprehension of mask manufacturability, including the vital issue of the number of colors in the mask. While it is obvious that use of three or more colors will give the best image, one has to be practical about projecting mask manufacturing capabilities for such a complex mask. To circumvent this serious issue, we eventually settled on a two color mask - comprising plain glass and etched glass. In addition, there were several smaller manufacturability concerns, for example a "1X1" glass pillar (an isolated 0 phase pixel) were susceptible to collapse under the stress of mask processing, and therefore these had to be constrained out of the final configuration. A third key element was defining the objective function. We experimented with a large number of choices and eventually settled on a form that allows us to trade-off fidelity and contrast. A fourth key element was the optimization algorithm. The number of possible configurations for a trillion pixels present on our final product mask is greater than the number of total elementary particles in the known universe, so finding the proverbial needle in this haystack was difficult to say the least. We chose a mixture of stochastic and direct descent algorithms to find an arrangement that meets the demands. While we have not proved we are close to the absolute global minimum, we conducted several experiments to suggest this is the case. A fifth key element, and a large one at that, was scaling up our software system from micron length scale to centimeter length scale required for full chip tapeout. This software, in turn, has several key components - hierarchy handling, the non-trivial handling of pixelated domain boundaries, repair of regions not converged in terms of image quality, and verification of the entire assembled database. All elements described above were validated through the tapeout of an actual mask to pattern the most complex metal layer for the leading 65nm node microprocessor in high volume manufacturing. This very first experimental tapeout resulted in wafer parts yield comparable to yields on mass produced wafers made with production 65nm technology.

In this paper, an overview of Inverse Lithography Technology (ILT) based on Level Set Methods (LSM) is provided. Applications of ILT in the advanced lithography process are then shown for several different devices, including DRAM, SRAM, FLASH, random logic, and imaging devices. ILT is used to correct the main patterns, as well as automatically insert SRAFs using model-based mathematical methods. The process of SRAF generation in ILT is unified with the process of inversion. With the help of ILT, SRAFs can be inserted where physically needed, independent of source parameters or target patterns. Results that demonstrate the adaptive nature of ILT SRAF insertion capability are presented. Wafer verification results were collected by multiple advanced semiconductor manufacturing companies at advanced technology nodes, including 45nm and 32nm nodes, and compared with their current OPC solution. Final wafer results presented here demonstrate that ILT improves pattern fidelity, enlarges process window, and provides remarkable control for line-end shortening.

In this paper we introduce a new mask imaging algorithm that is based on the source point integration method (or Abbe method). The method presented here distinguishes itself from existing methods by exploiting the through-focus imaging feature of the Extended Nijboer-Zernike (ENZ) theory of diffraction. An introduction to ENZ-theory and its application in general imaging is provided after which we describe the mask imaging scheme that can be derived from it. The remainder of the paper is devoted to illustrating the advantages of the new method over existing methods (Hopkins-based). To this extent several simulation results are included that illustrate advantages arising from: the accurate incorporation of isolated structures, the rigorous treatment of the object (mask topography) and the fully vectorial through-focus image formation of the ENZ-based algorithm.

There is a surprising lack of clarity about the exact quantity that a lithographic source map should specify. Under the plausible interpretation that input source maps should tabulate radiance, one will find with standard imaging codes that simulated wafer plane source intensities appear to violate the brightness theorem. The apparent deviation (a cosine factor in the illumination pupil) represents one of many obliquity/inclination factors involved in propagation through the imaging system whose interpretation in the literature is often somewhat obscure, but which have become numerically significant in today's hyper-NA OPC applications. We show that the seeming brightness distortion in the illumination pupil arises because the customary direction-cosine gridding of this aperture yields non-uniform solid-angle subtense in the source pixels. Once the appropriate solid angle factor is included, each entry in the source map becomes proportional to the total |E|^2 that the associated pixel produces on the mask. This quantitative definition of lithographic source distributions is consistent with the plane-wave spectrum approach adopted by litho simulators, in that these simulators essentially propagate |E|^2 along the interfering diffraction orders from the mask input to the resist film. It can be shown using either the rigorous Franz formulation of vector diffraction theory, or an angular spectrum approach, that such an |E|^2 plane-wave weighting will provide the standard inclination factor if the source elements are incoherent and the mask model is accurate. This inclination factor is usually derived from a classical Rayleigh-Sommerfeld diffraction integral, and we show that the nominally discrepant inclination factors used by the various diffraction integrals of this class can all be made to yield the same result as the Franz formula when rigorous mask simulation is employed, and further that these cosine factors have a simple geometrical interpretation. On this basis one can then obtain for the lens as a whole the standard mask-to-wafer obliquity factor used by litho simulators. This obliquity factor is shown to express the brightness invariance theorem, making the simulator's output consistent with the brightness theorem if the source map tabulates the product of radiance and pixel solid angle, as our source definition specifies. We show by experiment that dose-to-clear data can be modeled more accurately when the correct obliquity factor is used.

The growing importance of mask simulation in a low-k1 realm is matched by an increasing need for numerical methods capable of handling complex 3D configurations. Various approximations applied to physical parameters or boundary conditions allowed a few methods to achieve reasonable run-times. In this work the theoretical foundation and simulation results of an alternative 3D mask modeling method suitable for OPC simulations are presented. We have established the throughput and accuracy of the Coupled-Dipole Simulation Method and have compared results to the rigorous FDTD approach using a test pattern. We will discuss in detail possible approximations needed in order to accelerate the method's performance.

In this paper, we will outline general mathematical techniques applied to the solution of the inverse problem for partially coherent lithographic imaging. The forward imaging problem is reviewed and its solution is discussed within the framework of 2D sampling and matrix coherence theory. The intensity distribution on the wafer is shown to be a bilinear functional in the sampled mask transmission values, and represents a continuous sparse set of variables for optimization. We review various iterative techniques to optimize the sampled mask transmission, called a tau-map. From the optimal tau-map, a procedure is required to construct a pixelated mask representation with restricted transmission values. This mask representation is not unique since the problem is ill-posed, and leads to multiple mask solutions for a single optimal tau-map. Various procedures based on spectral techniques and principle component analysis to quantize the mask are reviewed.

In the Hyper-NA immersion lithography regime, the electromagnetic response of the reticle is known to deviate in a complicated manner from the idealized Thin-Mask-like behavior. Already, this is driving certain RET choices, such as the use of polarized illumination and the customization of reticle film stacks. Unfortunately, full 3-D electromagnetic mask simulations are computationally intensive. And while OPC-compatible mask electromagnetic field (EMF) models can offer a reasonable tradeoff between speed and accuracy for full-chip OPC applications, full understanding of these complex physical effects demands higher accuracy. Our paper describes recent advances in leveraging High Performance Computing as a critical step towards lithographic modeling of the full manufacturing process. In this paper, highly accurate full 3-D electromagnetic simulation of very large mask layouts are conducted in parallel with reasonable turnaround time, using a Blue- Gene/L supercomputer and a Finite-Difference Time-Domain (FDTD) code developed internally within IBM. A 3-D simulation of a large 2-D layout spanning 5μm×5μm at the wafer plane (and thus (20μm×20μm×0.5μm at the mask) results in a simulation with roughly 12.5GB of memory (grid size of 10nm at the mask, single-precision computation, about 30 bytes/grid point). FDTD is flexible and easily parallelizable to enable full simulations of such large layout in approximately an hour using one BlueGene/L "midplane" containing 512 dual-processor nodes with 256MB of memory per processor. Our scaling studies on BlueGene/L demonstrate that simulations up to 100μm × 100μm at the mask can be computed in a few hours. Finally, we will show that the use of a subcell technique permits accurate simulation of features smaller than the grid discretization, thus improving on the tradeoff between computational complexity and simulation accuracy. We demonstrate the correlation of the real and quadrature components that comprise the Boundary Layer representation of the EMF behavior of a mask blank to intensity measurements of the mask diffraction patterns by an Aerial Image Measurement System (AIMS) with polarized illumination. We also discuss how this model can become a powerful tool for the assessment of the impact to the lithographic process of a mask blank.

In hyper-NA imaging, the vector properties of the light become important. Therefore, to characterize and to fully exploit the state-of-the-art lithographic apparatus, reconstruction of polarization matrices in the pupil plain of a projection lens has become indispensable. We will present a reconstructed Jones matrix of a benchtest projection optic. The reconstruction method is based on the concept of the first canonical coordinate of the Lie group, which conjures up a geometrical approach. The Jones matrix of this benchtest immersion projection lens is successfully reconstructed using the data obtained by an on-body tool called iPot. A reconstructed polarized wavefront and polarized wavefront measured by iPot agree very well. This newly developed methodology is essential to capturing the nature of light transformations in the hyper-NA projection lenses. It is of fundamental importance to quantifying the properties of the state-of-the-art projection lenses used in lithography.

Results are presented of mask imaging using the Extended Nijboer-Zernike (ENZ) theory of diffraction. We show that the efficiency of a mask imaging algorithm, derived from this theory, can be increased. By adjusting the basic Finite Difference Time Domain (FDTD) algorithm, we can calculate the near field of isolated mask structures efficiently, without resorting to periodic domains. In addition, the calculations for the points on the entrance sphere of the imaging system can be done separately with a Fourier transformed Stratton-Chu nearto- far-field transformation. By clever sampling in the radial direction of the entrance pupil, the computational effort is already reduced by at least a factor of 4.

If RET selection by simulation is to be successful for the deep sub-wavelength technologies of today, then the predictions of the simulator must be quantitatively accurate over the parameter space of interest. The Rigorous Physical resist Model (RPM) within PROLITH and Lithoware is separable from the illumination conditions and the reflection behavior of the wafer stack, and thus should be an excellent candidate for such projects. In this work, the RPM is calibrated for a commercially available ArF photoresist using topdown CD-SEM data, including focus-exposure matrices and CD vs. mask pitch data, under fixed process conditions. It will be shown that this RPM is able to predict the performance of line, trench and contact features, with quantitative accuracy, under different numerical aperture and illumination conditions, even when the wafer stack is altered significantly. The stack alterations include resist thickness change, the presence or absence of an immersion topcoat, substitution of different underlying substrate materials and the use of a single or double layer anti-reflection coating. The resist model accurately describes both the experimental calibration data and two separate experimental validation datasets. The RMS error seen in the extrapolative predictions is comparable to that observed between the model and the original calibration dataset.

High-refractive-index fluids (HIFs) are being considered to replace water as the immersion fluid in next generation 193nm immersion scanner. We have demonstrated the attractive optical properties for our HIF candidates, HIL-001, HIL-203 and HIL-204. Especially, HIL-203 and HIL-204 have higher transmittance compared to water. In this paper, we describe our latest results on the comparative evaluations including photo-degradation behavior and lens contamination phenomenon in a flow system. For laser induced fluid degradation behavior, it was shown the higher initial transmittance resulted in the higher laser durability. However, the complicated phenomenon was observed for the lens contamination test. That is, HIL-204 with higher initial transmittance showed higher lens contamination rate than HIL-203. From several analyses, the complicated behaviors among HILs were speculated to be caused by the different nature of photo-degraded impurities. In order to control the fluid transmittance change and suppress the lens contamination during exposure, the refining process was definitely necessary for HIL reuse system. Based on the refining mechanism and the refining material design, we have developed an appropriate refinement unit named Refine B. This approach provided us with the result that Refine B could control the change of fluid transmittance and suppress the lens contamination rate.

High index immersion lithography is one of the candidates for next generation lithography technology following water immersion lithography. This technology may be most attractive for the industry since it is effective in raising resolution without seriously changing the chip making processes. This motivates us to continue to study further NA expansion although there are many challenges with respect to either high index fluid development or high index lens material development. In this paper, the current status of high index lithography development compared with the industry's requirements is discussed while considering design feasibility.

A two-year study on the feasibility of High-n Immersion Lithography shows very promising results. This paper reports the findings of the study. The evaluation shows the tremendous progress made in the development of second-generation immersion fluid technology. Candidate fluids from several suppliers have been evaluated. All the commercial fluids evaluated are viable, so there are a number of options. Life tests have been conducted on bench top fluid-handling systems and the results referenced to full-scale systems. Parameters such as Dose per Laser Pulse, Pulse Rate, Fluid Flow Rate, and Fluid Absorbency at 193nm, and Oxygen/Air Contamination Levels were explored. A detailed evaluation of phenomena such as Last Lens Element (LLE) contamination has been conducted. Lens cleaning has been evaluated. A comparison of High-n fluid-based technology and water-based immersion technology shows interesting advantages of High-n fluid in the areas of Defect and Resist Interaction. Droplet Drying tests, Resist Staining evaluations, and Resist Contrast impact studies have all been run. Defect-generating mechanisms have been identified and are being eliminated. The lower evaporation rate of the High-n fluids compared with water shows the advantages of High-n Immersion. The core issue for the technology, the availability of High-n optical material for use as the final lens element, is updated. Samples of LuAG material have been received from development partners and have been evaluated. The latest status of optical materials and the technology timelines are reported. The potential impact of the availability of the technology is discussed. Synergy with technologies such as Double Patterning is discussed. The prospects for <22nm (hp) are evaluated.

A potential extension of water-based 193-nm immersion lithography involves transition to a higher refractive index organic immersion fluid coupled with a higher index last lens element. While considerable progress has been made in improving the photo-durability of the immersion fluid itself, photo-induced contamination of the last lens element caused by laser exposure in the presence of such organic fluids remains a major concern. In this work, we study remediation strategies for such contamination, which would be compatible with conventional lithographic production environments. In general, surface photocontamination layers were found to be highly graphitic in nature, where the first monolayer is strongly bound to the substrate. We have attempted to develop a surface passivation treatment for altering the monolayer chemistry and preventing large-scale contamination, but found such treatments to be unstable under laser irradiation. On the other hand, using hydrogen peroxide as a in-situ cleaning solution has been shown to be extremely effective. We also present first laser-based durability results of LuAG, which is a leading candidate material for high index last element to be used with high index fluids.

We have performed high-index immersion fluid studies to define the levels of both soluble and insoluble impurities present. These studies have also revealed the importance of process materials' purity in fluid contact. Fluid interactions with resist, leading to both surface and imaging defects, can be minimized by proper resist selection. Our Active Recycle Package technology can greatly extend the useful life of both the fluid itself, as well as the final lens element.

Volume production of 45nm node devices utilizing Nikon's S610C immersion lithography tool has started. Important to the success in achieving high-yields in volume production with immersion lithography has been defectivity reduction. In this study we evaluate several methods of defectivity reduction. The tools used in our defectivity analysis included a dedicated immersion cluster tools consisting of a Nikon S610C, a volume production immersion exposure tool with NA of 1.3, and a resist coater-developer LITHIUS i+ from TEL. In our initial procedure we evaluated defectivity behavior by comparing on a topcoat-less resist process to a conventional topcoat process. Because of its simplicity the topcoatless resist shows lower defect levels than the topcoat process. In a second study we evaluated the defect reduction by introducing the TEL bevel rinse and pre-immersion bevel cleaning techniques. This technique was shown to successfully reduce the defect levels by reducing the particles at the wafer bevel region. For the third defect reduction method, two types of tool cleaning processes are shown. Finally, we discuss the overall defectivity behavior at the 45nm node. To facilitate an understanding of the root cause of the defects, defect source analysis (DSA) was applied to separate the defects into three classes according to the source of defects. DSA analysis revealed that more than 99% of defects relate to material and process, and less than 1% of the defects relate to the exposure tool. Material and process optimization by collaborative work between exposure tool vendors, track vendors and material vendors is a key for success of 45nm node device manufacturing.

We evaluate several types of wafers and investigate the effect of wafer edge geometry on focus, dynamics and defectivity performance in ArF immersion lithography. Wafer edge geometry includes both edge shape (e.g. short, long, full round etc.) and edge roll-off (ERO) here. We found that focus accuracy at wafer edge depends on ERO, especially on ZDD (Z double derivative) and if we use the specified wafer which has low ZDD value, it keeps same good focus accuracy at the edge area as the one at the wafer center area. Dynamics (stage synchronization accuracy) was independent of wafer diameter, thickness and edge geometry. We also found that defectivity was strongly dependent on the edge shape. More bridging defects were found on the short edge wafer than the long edge wafer. This is related with wafer edge conditions after coating and during exposure.

Immersion technology is definitely the mainstream lithography technology for NAND FLASH in recent years since hyper-NA immersion technology drives the resolution limit down to the 40-50 nm half pitch region. Immersion defectivity and overlay issues are key challenges before introducing immersion technology into mass production. In this work, both long term immersion defectivity and overlay data, as well as good photoresist performance, show the Nikon S610C immersion scanner plus LITHIUS i+ cluster is capable of 40-50 nm NAND FLASH mass production. Immersion defects are classified based on their causes, and no tool specific immersion defects, e.g. bubbles and water marks, were found in the Nikon S610C plus TEL LITHIUS i+ cluster. Materials-induced immersion defects require more attention to achieve production-worthy results.

Water-based immersion technology has overcome various challenges and is starting to be used for the 45nm-node mass production. However, even though immersion technology is being used in memory device production, significant improvement in defect performance is needed before the technology can be used for logic devices. Canon has developed an immersion exposure system, the FPA-7000AS7, with numerical aperture of 1.35. In the AS7 immersion tool, there is little influence of vibration and evaporative cooling. The AS7 has an in-situ cleaning system in order to remove particles carried into the exposure tool. We evaluated the contamination of the projection lens and immersion nozzle due to photoacid generator (PAG) leaching from resist to water. We evaluated the cleaning effects of various cleaning processes and found the suitable processes for cleaning the projection lens and immersion nozzle from the view that it does not adversely affect the exposure tool: damage-free and easy drainage treatment. In addition, we evaluated the influence of particles on the wafer stage, since there is a major concern that particles entering the water may increase the defects. The number of particles adhering on the wafer during an exposure sequence can be reduced with the wafer stage cleaning. Periodical cleaning keeps the wafer stage clean, thus preventing the increase of exposure defects caused by particles. We performed a defect evaluation with the AS7. The average defect density was 0.042/cm² in the continuous exposure process of 25 wafers with a developer-soluble topcoat. Circle defects and bubble defects were not observed.

While lithography R&D community at large has already gotten the mind set for 32nm, all eyes are on 22nm node. Current consensus is to employ computational lithography to meet wafer CD uniformity (CDU) requirement. Resolution enhancement technologies (RET) and model OPC are the two fundamental components for computational lithography. Today's full-chip CDU specifications are already pushing physical limits at extreme lithography k₁ factor. While increasingly aggressive RET either by double exposure or double patterning are enabling imaging performance, for CDU control we need ever more accurate OPC at a greater computational efficiency. In this report, we discuss the desire for wanting more robust and accurate OPC models. One important trend is to have predictive OPC models allowing accurate OPC results to be obtained much faster, shortening the qualification process for exposure tools. We investigate several key parameters constitute to accuracy achievable in computational lithography. Such as the choice of image pixel size, numbers of terms needed for transmission cross coefficients (TCC), and "safe" ambit radius for assuring accurate CD prediction. Selections of image pixel size and "safe" ambit radius together determine % utilization for 2D fast Fourier transformation (FFT) for efficient full-chip OPC computation. For IC manufacturing beyond ArF, we made initial observations and estimations on EUV computational lithography. These discussions pave the way for developing a computational lithography roadmap extends to the end of Moore's Law. This computational lithography roadmap aims to be a complement for the current ITRS roadmap on what does it take to achieve CD correction accuracy.

Production optical proximity correction (OPC) tools employ compact optical models in order to accurately predict complicated optical lithography systems with good theoretical accuracy. Theoretical accuracy is not the same as usable prediction accuracy in a real lithographic imaging system. Real lithographic systems have deviations from ideal behavior in the process, illumination, projection and mechanical systems as well as in metrology. The deviations from the ideal are small but non-negligible. For this study we use realistic process variations and scanner values to perform a detailed study of useful OPC model accuracy vs. the variation from ideal behavior and vs. theoretical OPC accuracy. The study is performed for different 32nm lithographic processes. The results clearly show that incorporating realistic process, metrology and imaging tool signatures is significantly more important to predictive accuracy than small improvements in theoretical accuracy.

A new method for the simulation of diffraction limited images is presented that is suitable for application in optical proximity correction and verification, where fast execution is critical. The method is given the name hybrid Hopkins-Abbe, because it is literally a hybrid of Hopkins' and Abbe's diffraction theories. The hybrid Hopkin--Abbe method resolves the problem of the traditional Hopkins theory, namely the requirement for constant mask diffraction efficiencies. Simulation of electromagnetic scattering from the mask that takes into account the oblique angles of incidence from the illumination is performed by application of the domain decomposition method that is extended for offaxis illumination. Examples of 45nm and 32nm lines and spaces through pitch and through focus are presented to demonstrate the validity and accuracy of the hybrid Hopkins-Abbe method. The results obtained are in excellent agreement with a rigorous and independent (third party) simulator. Other aspects of hybrid Hopkins-Abbe method relevant to OPC application are also discussed.

Robust optical proximity correction (OPC) and design for manufacturability (DFM) methodology for optical variation among exposure tools is proposed. It is demonstrated that application of the methodology improves standard deviation of CD difference for target CD by 33% compared with the case of using the conventional methodology. Under the low-k1 lithography condition, hot spots induced by optical variation among exposure tools delay ramp-up of production of high-volume products. To realize robust pattern formation for all exposure tools, the following new methodologies are introduced : i) OPC modeling methodology using actual optics of primary tool, ii) OPC processing methodology using averaged or designed optics, iii) at the design stage, hot spot detection within the optical variation space centered on average or designed optics and hot spot fixing by layout modification or OPC optimization, iv) at the manufacturing stage, hot spot detection using actual optics and hot spot fixing by optical adjustment of troubled tool.

Pixelated phase masks rendered from computational lithography techniques demand one generation-ahead mask technology development. In this paper, we reveal the accomplishment of fabricating Cr-less, full field, defect-free pixilated phase masks, including integration of tapeout, front-end patterning and backend defect inspection, repair, disposition and clean. This work was part of a comprehensive program within Intel which demonstrated microprocessor device yield. To pattern mask pixels with lateral sizes <100nm and vertical depth of 170nm, tapeout data management, ebeam write time management, aggressive pattern resolution scaling, etch improvement, new tool insertion and process integration were co-optimized to ensure good linearity of lateral, vertical dimensions and sidewall angle of glass pixels of arbitrary pixelated layout, including singlets, doublets, triplets, touch-corners and larger scale features of structural tones including pit/trench and pillar/mesa. The final residual systematic mask patterning imperfections were corrected and integrated upstream in the optical model and design layout. The volume of 100nm phase pixels on a full field reticle is on the order tera-scale magnitude. Multiple breakthroughs in backend mask technology were required to achieve a defect free full field mask. Specifically, integration of aerial image-based defect inspection, 3D optical model-based high resolution ebeam repair and disposition were introduced. Significant reduction of pixel mask specific defect modes, such as electro static discharge and glass pattern collapse, were executed to drive defect level down to single digit before attempt of repair. The defect printability and repair yield were verified downstream through silicon wafer print test to validate defect free mask performance.

In this paper advanced OPC (Optical Proximity Correction) methods, additional with assistant features, and non-obvious methods were implemented to correct aberrations caused by aggressive illuminations in order to optimize the shape of the finger tips. OPC model and simulations were verified using 2D verification method.

In the Hyper-NA immersion age, it is essential to optimize all optical parameters, and so exposure tools must have functions to precisely control the parameters. There have been various reports indicating that polarization aberrations of projection optics affect imaging performance, but there have been few reports on reducing their influence in tools. We have developed a new method to optimize imaging performance with polarization taken into account. This paper describes a theoretical analysis of polarization with Pauli decomposition. A strict vectorial calculation of optical images matches our expression. Then, our solver software can determine the optimum conditions of all aberration parameters of exposure tools for specific IC patterns.

To determine the magnitude of the exposure latitude required for a process to be manufacturable, additional factors are considered that have a similar relationship between linewidth variation and image log-slope. Such parameters include resist thickness, flare, post-exposure bake temperature, and line-edge roughness. To obtain consistency between theory and experiment it is necessary to use the resist-edge log-slope generalization of image log-slope. Inclusion of these additional factors increases the required exposure latitude five to six times more than would be considered necessary from exposure tool dose control alone.

A theoretical analysis to estimate the effect of shot noise on CDU is induced from optical imaging perspectives combined with quantum theory, and is studied for 193-nm, EUV, and electron beam lithography. We found the CDU variation from shot noise is related to the number of particles absorbed in the printed area and to the image log slope (ILS). Hence, the CDU variation contributed by shot noise gets worse when the technology node advances from 45- to 32-, 22-, and 15-nm, EUV with higher ILS is no exception. For e-beam lithography, we are interested in the values of ILS calculated from array structures with different pitches, backscattering, wafer-stage movement, and raster-scan writing.

Depth of Focus (DOF) and exposure latitude requirements have long been ambiguous. Techniques range from scaling values from previous generations to summing individual components from the scanner. Even more ambiguous is what critical dimension (CD) variation can be allowed to originate from dose and focus variation. In this paper we discuss a comprehensive approach to measuring focus variation that a process must be capable of handling. We also describe a detailed methodology to determine how much CD variation can come from dose and focus variation. This includes examples of the statistics used to combine individual components of CD, dose and focus variation.

This paper examines the extendibility of the scatterometry techniques to characterize structures pushing the limits of current lithographic printing technologies. In particular, we investigate the limits of normal-incidence optical CD (NIOCD) measurements using the smallest features afforded by the most recent generation of hyper-NA immersion scanners. Special analysis techniques have also been developed and applied to cases relevant to double exposure and double patterning lithography. Models were used successfully to decouple CD and overlay values associated with patterning the first and second set of features on the wafer, using a single scatterometry measurement. These advances pave the way to the development of full solutions for the general case of double patterning structures with two different populations of lines or structures. In addition, the current study focused on seeking a better understanding of the use of scatterometry 3D features characterization, particularly as it relates to OPC model building and verification. The demonstration of tip-to-tip measurements on 3D structures is very encouraging as it introduces the advantages of scatterometry, such as reduced influence of line-edge roughness (LER) and better precision, to the practice of advanced OPC model building.

Nikon's production immersion scanners, including the NSR-S609B and the NSR-S610C, have now been in the field for over 2 years. With these tools, 55 nm NAND Flash processes became the first immersion production chips in the world, and 45 nm NAND Flash process development and early production has begun. Several logic processes have also been developed on these tools. This paper discusses the technical features of Nikon's immersion tools, and their results in production.

Canon has developed an immersion exposure tool, the FPA-7000AS7 (AS7), with the industry's highest NA of 1.35. This paper reports on its performance. The AS7's projection lens achieves ultra-low aberration with total RMS of less than 5 mλ and flare of less than 0.5%. The resolution capability is 37 nm with k1 = 0.259, and DOF of 0.8 μm was obtained owing to the ultra-low aberration and low flare. Regarding focus performance, a 3σ value of 19.3 nm for Lstage and 16.1nm for R-stage were attained in a whole area. The result of CD uniformity of 1.91nm (3σ) was obtained across the wafer with a total of 4032 measurement points. Distortion was 3.9 nm at the worst value. On the other hand the most critical issue of immersion is defects, so the nozzle, lens and stage must be cleaned to reduce defects. The result of defect evaluation of the AS7 was an average of 0.042 defect/cm² from 25 wafers in a lot and average 0.046 defect count/cm² from long-term defect evaluation for two months. From these results, we are confident that the AS7 is capable of 45-nm node device production.

Immersion lithography has been developed in a tremendous pace. Starting in late 2001, the technology now has moved to volume production of advanced flash memories. The immersion exposure system has been the key enabler in this progress. In this paper we discuss the evolution of the TWINSCAN immersion scanning exposure tools, and present an overview of its performance on imaging, lens heating control, overlay, focus and defects. It is shown that stable performance assures 45-nm device volume manufacturing. Extendibility of immersion towards 38-nm and 32-nm is discussed. For NAND the next device half pitch will be around 38-nm and it is shown that with 1.35 NA and low k1 dipole or CQUAD illumination a final extension with single exposure is possible. For the 32-nm node and beyond double patterning methods are required till EUV lithography is ready to be used in volume production. To secure tight CD tolerance the overlay performance of the immersion tools need to be tightened to numbers well below 3-nm. The paper presents overlay improvements towards the requirements for double patterning.

IC manufacturers have a strong demand for transferring a working process from one scanner to another. In an ideal transfer, a reticle set that produces devices within specification on a certain scanner has the same performance on another exposure tool. In real life, however, reticles employ optical proximity correction (OPC) which incorporates by definition the inherent optical fingerprint of a specific exposure tool and process. In order to avoid the additional cost of developing a new OPC model and acquiring a new reticle for each exposure tool, IC manufacturers therefore wish to "match" the optical fingerprint of their scanners as closely as possible. In this paper, we report on the matching strategy that we developed to perform a tool-to-tool matching. We present experimental matching results for several tool combinations at numerical apertures (NA) 0.75, 0.85 and 1.2. Matching of two exposure tools is obtained by determining the sensitivities to scanner parameter variations like NA, Sigma, Focus Drilling, Ellipticity and Dose from wafer data and/or simulations. These sensitivities are used to calculate the optimal scanner parameters for matching the two tools.

Double patterning (DP) lithography is expected to be deployed at the 32nm node to enable the extension of high NA (≥1.3) scanner systems currently used for 45nm technology. Increasing the light source power is one approach to address the intrinsically lower throughput that DP imposes. Improved energy stability also provides a means to improve throughput by enabling fewer pulses per exposure slit window, which in turn enables the use of higher scanner stage speeds. Current excimer laser light sources for deep UV immersion lithography are operating with powers as high as 60W at 6 kHz repetition rates. In this paper, we describe the introduction of the XLR 600i, a 6 kHz excimer laser that produces 90W power, based on a recirculating ring technology. Improved energy stability is inherent to the ring technology. Key to the successful acceptance of such a higher power, or higher energy laser is the ability to reduce operating costs. For this reason, the recirculating ring technology provides some unique advantages that cannot be realized with conventional excimer lasers today. Longer intrinsic pulse durations that develop in the multi-pass ring architecture reduce the peak power that the optics are subjected to, thereby improving lifetime. The ring architecture also improves beam uniformity that results in a significantly reduced peak energy density, another key factor in preserving optics lifetime within the laser as well as in the scanner. Furthermore, in a drive to reduce operating costs while providing advanced technical capability, the XLR 600i includes an advanced gas control management system that extends the time between gas refills by a factor of ten, offering a significant improvement in productive time. Finally, the XLR 600i provides a novel bandwidth stability control system that reduces variability to provide better CD control, which results in higher wafer yields.

The k1 factor continues to be driven downwards, even beyond its theoretical limit 0.25, in order to enable the 32 nm feature generation and beyond. Due to the extremely small process-window that will be available for such extremely demanding imaging challenges, it is necessary that not only each unit contributing to the imaging system be driven to its ultimate performance capability, but also that the final integrated imaging system apply each of the different components in an optimum way with respect to one another, and maintain that optimum performance level and cooperation at all times. Components included in such an integrated imaging system include the projection lens, illumination optics, light source, in-situ metrology tooling, aberration control, and dose control. In this paper we are going to discuss the required functions of each component of the imaging system and how to optimally control each unit in cooperation with the others in order to achieve the goal of 32 nm patterning and beyond.

Ellipsometry is defined as a technique for determining the properties of a bulk material or a thin film, such as optical index and thickness, from the measurement of a polarization state of a reflected light or a change of polarization states between the incident and reflected lights. On the other hand, polarimetry is defined as a technique for determining a polarization state of a light. In other words, ellipsometry uses polarization as a probe and polarimetry measures polarization itself. We have constructed a theory of polarimetry of illumination used in lithography equipments, fabricated a polarimeter mask, and demonstrated it for a hyper-NA (numerical aperture) immersion lithography scanner. The polarimeter mask comprises polarizers and quarter-wave (λ/4) plates that are crammed into a narrow space with a height of 6.35 mm. The thin plate polarizers available at a wavelength of 193 nm are made of calcite, and the λ/4-plates insensitive to angle of incidence are made of four thin plates, two of which are crystalline quartz; the other two are sapphire. A light traveling through a window of the polarimeter mask reaches an image detector at the wafer level through projection optics. Stokes parameters of the illumination light can be measured without any influence from polarization characteristics of the projection optics between the mask and the image detector.

Optical lithography has had great success in recent history in utilizing the most advanced optical technology to create NA=1.35 immersion lenses. These lenses have aberration levels at or below the 5m level. Much of this is due to advancements in lens design, materials, and aspheric polishing techniques. Now that the lenses are nearly "perfect", more attention is being given to the illuminator and its performance. This paper examines the fundamental metrics that are used to analyze the illumination source shape as it pertains to the optical proximity effect (OPE). It is found that the more traditional metric of partial coherence, σ, is often not sufficient to explain through pitch CD performance. Metrics are introduced to compare multiple sources and compared to their correlation to OPE with respect to a reference. A new parametric model for annular illumination is introduced and shown to correlate within an RMS=0.03nm of the OPE data.

In order to respond to the constant demand for more productivity in the manufacture of IC devices, higher throughput and higher resolution are fundamental requirements for each new generation of exposure tools. However, meeting both requirements lead to unwanted aberration we refer to as "thermal aberration". In our experience, the problem of the thermal aberrations does not correlated only to the duration of heavy use. It depends very strongly on both the optical settings and the mask patterns, also even on the specific interaction between the two. So, even if using the same illumination configurations, there is a possibility to observe different distribution of thermal aberrations. In this paper, we define and investigate various patterns to be used as targets for thermal aberrations compensation. These patterns are identified as the "weak patterns" of the thermal aberration. We assess several cases of thermal aberrations, and show how the optimized compensation for each is determined and then applied on the actual exposure tools.

The introduction of lithographic systems with NA=1.35 has enabled the extension of optical lithography to 45 nm and below. At the same time, despite the larger NA, k1-factors have dropped to 0.3 and below. Defining the appropriate strategies for these high-end lithographic processes requires the integration and co-optimization of the design, mask and imaging parameters. This requires an in-depth understanding of the relevant parameters for imaging performance during high volume manufacturing. Besides the Critical Dimension Uniformity (CDU) budget for the baseline lithographic system, it is crucial to realize that system performance may vary over time in volume manufacturing. In this paper the CDU budget will be restated, with all the well-known contributors, and extended with some new terms, such as volume manufacturing effects. Experimental low-k1 results will be shown from NA=1.35 lithographic tools and compared to model-based predictions under realistic volume manufacturing circumstances. The combination of extreme NA and low k1 makes it necessary to introduce computational lithography for scanner optimization. The potential of using LithoCruiser^TM and Tachyon^TM for optimising scanner source and OPC will be described. Also, using the fast scanner correction mechanisms to compensate for reticle, track and etch fingerprints and variations will be discussed.

This paper will provide experimental results of Phase-Shift Mask (PSM) Polarimetry, a previously introduced resistbased polarization monitoring technique that employs a specialized chromeless phase-shifting test reticle. The patterns derived from high-NA proximity effects have proven to be 2 to 3 times more sensitive to polarization than a previously reported generation of patterns. Example results in this paper show that for a numerical aperture (NA) of 0.93, this technique is likely capable of measuring the intensity in the preferred polarization state (IPS) to within about 3%. Data from a follow-on reticle for NAs up to 1.35 is expected soon and promises to measure IPS to within about 1.5%. This is expected to suffice for monitoring polarization at the 22nm node for water-based immersion tools over time or from tool to tool. This technique is extendable and likely offers even greater sensitivity for high-index immersion lithography, should NAs greater than 1.35 become available. Advantages and disadvantages of this technique will be addressed.

In this study, DP (Double Patterning) and DPS (Double Patterning with Spacer) were comprehensively compared through word line layout of 50nm node product, and special focus was put on the assessments of layout discontinuity zones through experimental validation. In conventional flash manufacturing, the lithographic proximity effect and etch loading effect around the array-gap zones have been inherent characteristics to be addressed. For DP process, apart from the overlay error induced pattern displacement and CD non-uniformity, the cross-coupling effects between adjacent features around the array-gap zones by two photo and two etch steps have further complicated the process optimization, therefore careful exploration was carried out to indicate the challenges on process optimization. The DPS can maintain good resultant CD uniformity of dense array through precisely programmed exposure CD and spacer thickness, it may also keep away from the proximity around array-gap zones. But, the second exposure is necessary for trimming the unwanted patterns and delineating the peripheral patterns. In purpose of trimming the unwanted patterns at array-gap zone in the 2nd exposure, the overlay registration will account for the CD control of boundary lines as well as the defectivity around this area.

In this paper we investigate the process margin for the 100nm half - pitch double exposure KrF lithography using binary masks for different illumination settings. The application of Double Exposure Lithography (DEL) would enlarge the capability of 248 nm exposure technique to smaller pitch e.g. for the integration of dedicated layers into 0.13 μm BiCMOS with critical dimension (CD) requirements exceeding the standard 248 nm lithography specification. The DEL was carried out with a KrF Scanner (Nikon S207D, NA_Lens = 0.82) for a critical dimension (CD) of 100nm half pitch. The chemical amplified positive resists SL4800 or UV2000 (Rohm & Haas) with a thickness of 325nm were coated on a 70 nm AR10L (Rohm & Haas) bottom anti-reflective coating (BARC). With a single exposure and using binary masks it is not possible to resolve 100nm lines with a pitch of 200 nm, due to the refraction and the resolution limit. First we investigated the effect of focus variation. It is shown that the focus difference of 1st and 2nd exposure is one critical parameter of the DEL. This requires a good focus repeatability of the scanner. The depth of focus (DOF) of 360 nm with the coherence parameter σ = 0.4 was achieved for DEL with SL4800 resist. The influence of the better resist resolution of UV2000 on the process window will be shown (DOF = 460 nm). If we change the focus of one of the exposures the CD and DOF performance of spaces is reduced with simultaneous line position changing. Second we investigated the effect of different illumination shapes and settings. The results for conventional illumination with different values for σ and annular illumination with σ_inner = 0.57 and σ_outer = 0.85 will be shown. In summary, the results show that DEL has the potential to be a practical lithography enhancement method for device fabrication using high NA KrF tool generation.

A new technology called the double patterning (DP) process with ArF immersion lithography is one of the candidate fabrication technologies for 32 nm-node devices. Over the past few years, many studies have been conducted on techniques for the DP process. Among these technologies, we thought that the double Si hard mask (HM) process is the most applicable technology from the viewpoint of high technical applicability to 32 nm-node device fabrication. However, this process has a disadvantage in the cost performance compared with other DP technologies since these HMs are formed by the chemical vacuum deposition (CVD) method. In this paper, we studied the DP process using a dual spin-on Si containing layer without using the CVD method to improve process cost and process applicability. Perhydropolysilazane (PSZ) was used as one of the middle layers (MLs). PSZ changes to SiO₂ through the reaction with water by the catalytic action of amine in the baking step. Using PSZ and Si-BARC as MLs, we succeeded in making a fine pattern by this novel DP technique. In this paper, the issues and countermeasures of the double HM technique using spin-on Si containing layers will be reported.

Double patterning technique is listed as the top option for 32nm technology nodes at recently updated 2007 International Technology Roadmap Semiconductor (ITRS). Double patterning (DP) effectively reduces the k1 factor to less than 0.25, however, various process challenges, including critical dimension uniformity (CDU), line edge and line width roughnesses (LER/LWR), and overlay, have to come up with solutions for the industry in device manufacturing. In this study, we developed a metal hard mask and a universal dual hard mask double patterning process and demonstrated 45nm half-pitch in dark field patterning and 32nm half pitch in bright field applications by using a 0.93NA 193nm dry scanner system. By using the optimized hard mask films and Applied Materials' Advanced Patterning Film (APF^TM) as a bottom hard mask, the universal dual hard mask double patterning scheme shows significant improvement in line edge roughness and line width roughness, achieved best results of 2nm LER and 2.5nm LWR at APF hard mask.

As the VLSI technology scales into deep submicron nodes, Double Patterning Technology (DPT) has shown its necessity for the under 45nm processes. However, the litho-related and process-related issues, such as the overlay control for CD uniformity, decomposition, feature stitching technology and some other problems make up the main challenges for the implementation of DPT. Due to Optical Proximity Correction (OPC), the complexity and data volume of DPT increase dramatically, which severely increase the application cost and create manufacturability problems. In this paper, we mainly talk about the interactions between DPT and OPC and propose a new Model-Based OPC methods for the decomposition in DPT procedures. To address the printing problems with cutting sites for feature split, we introduce an overlap correction method on the stitching locations. For any re-cut and/or redesigned pattern after verification, we categorize DP decompositions and introduce a new Adaptable OPC (Ad-OPC) algorithm by reusing post OPC layout to speed up the correction and improve its convergence according to environment surrounding. The method can be easily incorporated into existing MB-OPC framework. To test this method, total Edge Placement Error (EPE) and runtime are calculated in our experiments. Results show that over 90% runtime can be saved compared with conventional OPC procedure. It increases the robustness and friendliness of pattern correction as well as stitches features back satisfactorily.

There has been an ongoing request to make semiconductor devices smaller and smaller. The cellblock size of SRAM is predominated by both a gate-to-contact space and a poly-to-poly space. The gate-to-contact space is defined by the leakage value from the poly electrode. So we focused on the poly-to-poly space for all shrinkage. We have been studying connected line splitting techniques. We named it ELS (end of line splitting) technology. A critical issue is to control gaps between two narrow gate-poly's line-ends or between a narrow gatepoly's line-end and a neighboring wire-poly line due to lower contrast in low-k1 lithography. In the case of standard cells, especially, the patterning of narrow gate-poly projected to wire-poly is easy to shorten. To prevent this electrical short, designers avoid keeping a narrow gap and small chip size. In order to realize a narrower gap, a splitting technique, well-known and adopted in poly's line-ends of SRAM that are regularly arrayed, is effective. We are investigating how to extend this technique as ELS technology for random logic of poly toward creating a 32-nm node. In this paper, the authors focus on the following topics: 1) data preparation technique, and 2) experimental results. Then this technology for the poly layer of random logic LSI devices is compared with result of conventional single exposure and double pattering technology. In addition, the result that overlay control issue for ELS technology is not severe compared with pitch doubling technology is described. ELS technology can help the designer and our lithographer to reduce the gap and reduce the array grid size of standard cells.

Recently, in order to increase the number of transistors in wafer by small feature size, optical lithography has been changed to low wavelength from 365nm to 193nm and high NA of 0.93. And further wavelength is aggressively shifting to 13.5nm for more small feature size, i.e., Extreme Ultra Violet Lithography(EUVL), a kind of Next Generation Lithography(NGL)¹. And other technologies are developed such as water immersion(193nm) and photo resist Double Patterning(DP). Immersion lens system has high NA up to 1.3 due to high n of water(n=1.44 at 193nm), the parameter k1 is process constant, but 0.25 is a tough limit at a equal line and space, if we use immersion lens with 193nm wavelength than limit of resolution is 37nm. Especially, Double Exposure Technique(DET) process is widely studied because of the resolution enhancement ability using a same material and machine, despite of process complication. And SADP(Self Aligned Double Patten) is newly researched for overlay and LER(Line Edge Roughness) enhancement. In this paper, we illustrate the feasibility of the shift double pattern for 65nm-node flash using a 193nm light dipole source and the possibility of decrease minimum feature size using a property of silicon shrinkage during thermal oxidation process.

We have successfully developed a self-limiting chemical dry etch process, associated equipment, and process flow featuring no use of plasma and no mask bending. In this process and process flow, the system performs mask trimming for critical dimension (CD) adjustments after hard-mask formation. First, the CD as defined in lithography is directly transferred by reactive ion etching (RIE) to silicon oxide film that is to become the hard mask. Next, reactive gas is deposited on the surface of the silicon oxide film at low temperatures and the reaction product is evaporated at high temperatures. With this process flow, there is no need to trim a mask made of organic materials. As a result, there is no mask bending and the amount of hard-mask trimming can be set by the amount of gas flow and pressure in the chemical dry etch process enabling detailed CD control to be performed. The proposed technology means that even higher aspect ratios in masks and finer CD control can be achieved for processes such as double patterning (DP) and sidewall transfer (SWT).

We have developed a cost-effective critical dimension (CD) shrink technique that allows all-in-one processing of CD shrinking, BARC etching, hard mask etching, and resist stripping in a reactive ion etcher (RIE) for the double patterning (DP) required in the formation of contact and via hole masks with the most critical exposure margins. This CD shrink technique was successfully applied to achieve a CD shrinkage of 60 nm and a CD uniformity of within 3 nm at 3 sigma over the wafer surface. We also determined that the CD shrink technique that employs RIE differs from CD shrink by resolution enhancement lithography assisted by chemical shrink (RELACS) [1] and low-temperature molecular layer deposition (MLD) in having an effect of expanding the lithography process window. We successfully applied our technique to form a 30-nm CD hole pattern with a duty ratio of 1:1.

Double patterning is the best technique which allows 193nm immersion lithography to anticipate the 32 nm node, before EUV lithography. The final device pattern is formed by two independent patterning steps where the dense pitch is doubled. This allows printing each patterning step with higher k1 imaging factor. In this paper we present the overlay and CD budget applied to a double patterning (DP) technique for the definition of a 32nm technology node device, using an immersion scanner tool. A balance among different factors which affects the final CD of the device is necessary to optimize the imaging and the alignment performances of the exposure tool. A preliminary activity is also necessary to choose the most suitable mask splitting strategy. Adopting a single mask, which is exposed twice with the appropriate shift - the final pitch - , makes the overlay between the two exposures less critical than splitting the complementary layouts on two different masks. Finally, the CD uniformity of the pooled distributions from the two exposures is evaluated in order to define the requested tool performances in terms of overlay, CD control and metrology.

As SRAM arrays become lithographically more aggressive than random logic, they are more and more determining the lithography processes used. High yielding, low leakage, dense SRAM cells demand fairly aggressive lithographic process conditions. This leads to a borderline process window for logic devices. The tradeoff obtained between process window optimization for random logic gates and dense SRAM is not always straightforward, and sometimes necessitates design rule and layout modifications. By delinking patterning of the logic devices from SRAM, one can optimize the patterning processes for these devices independently. This can be achieved by a special double patterning technique that employs a combination of double exposure and double etch (DE2). In this paper we show how a DE2 patterning process can be employed to pattern dense SRAM cells in the 45nm node on fully integrated wafers, with more than adequate overlap of gate line-end onto active area. We have demonstrated that this process has adequate process window for sustainable manufacturing. For comparison purpose we also demonstrate a single exposure single etch solution to treat such dense SRAM cells. In 45nm node, the dense SRAM cell can also be printed with adequate tolerances and process window with single expose (SE) with optimized OPC. This is confirmed by electrical results on wafer. We conclude that DE2 offers an attractive alternative solution to pattern dense SRAM in 45nm and show such a scheme can be extended to 32nm and beyond. Employing DE2 lets designers migrate to very small tip-to-tip distance in SRAM. The selection of DE2 or SE depends on layout, device performance requirements, integration schemes and cost of ownership.

The current optical photolithography technology is approaching the physical barrier to the minimum achievable feature size. To produce smaller devices, new resolution enhancement technologies must be developed. Double exposure lithography has shown promise as potential pathway that is attractive because it is much cheaper than double patterning lithography and it can be deployed on existing imaging tools. However, this technology is not possible without the development of new materials with nonlinear response to exposure dose. The performance of existing materials such as reversible contrast enhancement layers (rCELs) and theoretical materials such as intermediate state two-photon (ISTP) and optical threshold layer (OTL) materials in double exposure applications was investigated through computer simulation. All three materials yielded process windows in double exposure mode. OTL materials showed the largest process window (DOF 0.137 μm, EL 5.06 %). ISTP materials had the next largest process window (DOF 0.124 μm, EL 3.22 %) followed by the rCEL (0.105 μm, 0.58 %). This study is an analysis of the feasibility of using the materials in double exposure mode.

Argon ion implantation has been investigated as a means of achieving resist stabilization, such that a second resist layer may be patterned without attacking the 1st layer. The viability of such an approach has been investigated for double printing. Potential benefits include resist feature shrinkage and Line Width Roughness (LWR) improvements. Line shrinkage benefits the lithographic process window as features can be printed larger, while improvements in LWR, is a further valuable attribute. We report on the role played by ion implant dose, its impact on both lateral and vertical resist shrinkage, LWR as well as its impact on organic BARC reflectivity. The performance of such masks during dry etching of a gate layer has been additionally evaluated.

Double patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double patterning process is discussed for 30nm half-pitch interconnect structures, using 1.2 NA immersion lithography combined with the Motif^TM CD shrink technique. An adjusted OPC calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by successfully transferring a 30nm half-pitch pattern into the MHM.

With 32nm and 22nm feature size node in the near future, Double patterning type processing will be in mainstream device manufacturing in most cutting edge Fabrication facilities. These type of processes requires cooperation between the litho cell and the other processing modules. In a collaboration between ASML and TEL we have developed a integrated solution to image 30nm Contacts. We describe a novel technique to achieve a geometric shrink from a starting geometry of 65nm down to the final feature size of 30nm for each of the two contact images Processing 2 images separately could produce two distinct populations for alignment and critical dimensions. We will show the ability to image 65nm contacts on a 130nm pitch with acceptable process windows and then apply the novel CD shrink process to shrink the 65nm contacts to 30nm final dimension. The second level of contacts is imaged in between the 1st set of contacts allowing us to image a 32nm ½ pitch contact pattern. We show the ability to Image 2 separate sets of contacts using a split clip layout with a single distribution for critical output parameters. We address the following process challenges: 1) Overlay capability across the slit and across the field. 2) Critical Dimension capability across the slit and across the Field. 3) Sidewall angle integrity with acceptable process window. Using the novel CD shrink process TEL has developed and imaging capability of the an ASML 1700i TWINSCAN, we can achieve a double pattern contact process with acceptable process capability.

A hyper-NA lithography tool is used in production of the latest devices. In the next generation immersion lithography, issues that had so for neglected had to be considered because NA of illumination optics is larger than conventional tools. Here, items were listed up for accurate prediction of imaging by optical simulation. These were transmittance of illumination rays to the mask, mask induced effects such as polarization and aberration, and pellicle induced effect. These were depending on incident angle. Therefore consideration of angle dependency of these effects was necessary for more accurate imaging simulation. We presented the requirements for simulation to facilitate discussion of the imaging performance of below 40 nm hp pattern node immersion lithography.

When projected with a scanner, the latent image intensity in the photoresist has a slope that can be much lower than with an interferometer. To study finely the lithographic process and to be predictive, the Normalized image slope of 193 nm immersion interferometer built at LETI has to be controlled. The exposure latitude (EL), the Normalized Image Log Slope (NILS) and the interference contrast are closely related.

ArF water immersion systems with a numerical aperture (NA) of over 1.3 have already introduced for the node up to 45- nm half-pitch production. For the next generation of lithography, we focus on ArF immersion lithography using high-index materials. At present, LuAG (n=2.14) is the most promising candidate as a high-index lens material. Second-generation fluids (n=1.64) have the sufficient performance as a high-index immersion fluid. The combination of LuAG and a second-generation fluid can enhance the NA up to 1.55 and the exposure system would be available for the 34-nm half-pitch node when k1 is 0.27. Although high-index immersion lithography is attractive since it is effective in raising resolution, there are some issues not encountered in water immersion system. The issues of LuAG are its availability and the intrinsic birefringence. Fluid degradation induced by dissolved oxygen or laser irradiation, lens contamination, and residual fluid on a wafer are the specific issues of the immersion system. In this article, we introduce the current status for the above issues and discuss the feasibility of ArF immersion system using high-index materials.

The practical extendibility of immersion lithography to the 32nm and 22nm nodes is being supported on immersion microsteppers installed at SEMATECH in Albany, New York. As the industry pushes the limits of water-based immersion technologies, research has continued into developing alternative materials to extend optical lithography for upcoming device generations. High index materials have been the primary focus of investigation, including optical lens materials such as lutetium aluminum garnet (LuAG with n=2.14) and barium lithium fluoride (BaLiF3 with n=1.64), high index fluids (Gen 2 and Gen 3 with n>=1.64), and resists. On a parallel and potentially complementary path, double patterning and double exposure technologies have been proposed. For high index materials research, the Amphibian XIS has demonstrated imaging at 1.50NA (32nm half-pitch) with high index fluids. A prism module is also available to enable imaging with potential BaLiF₃ and LuAG prisms. The Exitech MS193i has demonstrated performance and imaging capability at 38nm hp with k₁=0.256 at 1.30NA. Modifications at the mask plane now provide a double exposure capability, offering an imaging platform to investigate experimental classes of nonlinear materials and enabling double exposure imaging below k_1eff=0.25. In this paper, we will discuss recent developments in these research areas supported by the toolset at SEMATECH.

Optical lithography in the deep ultraviolet (DUV) region is being pushed to reach the limits of printing resolution. The effort required to achieve the 32 nm structure with this technology puts very hard conditions and requests on the illumination optics. Different kinds of illumination modes are combined to get into a regime of extreme numerical aperture (hyper NA). Arrays of refractive micro-optics have been and continue to be the ideal solution for high transmission homogenizing elements for several tool generations. Illumination of the masks with high numerical aperture is critical for achieving the smallest structure on the semiconductor material. Exposure tools use different illumination modes to get better imaging of certain mask structures. The beam shaping necessary to create these illumination modes is achieved mostly with diffractive elements. Most of the currently used modes can also be created with arrays of refractive micro-optics, manufactured from fused silica and calcium fluoride. The advantage over the diffractive optical elements lies in efficiency, which comes close to 90%. An important prerequisite for these special types of optical elements is LIMO's unique production technology which can manufacture free form surfaces on monolithic arrays exceeding 200 mm edge length with high precision and reproducibility. These homogenizing elements in the illumination optics can provide a custom designed intensity distribution, and offer the possibility to correct the failure of other optical elements. Each lens can be designed individually and can also be shaped asymmetrically. Thus unusual lens sizes and shapes can be produced, and various far fields such as rectangles, lines, hexagons or multi-poles can be achieved. In this paper we present novel refractive micro-optical elements which create rectangular dipole illumination. They can also be combined in such a way as to create a quadrupole with variable intensity ratio between the vertical and horizontal poles. The huge advantage of such a multipole illumination is polarization control and variable intensity in poles. Working on this combination, the resolution can be enhanced even further.

For 45 nm Node logic devices, we have investigated the impact of laser bandwidth fluctuation on Optical Proximity Effect (OPE) by evaluating variation in through-pitch critical dimension (CD) performance. In addition, from these results we have calculated the Iso-Dense Bias (IDB), and determined the sensitivity to laser bandwidth fluctuation. These IDB results also enable us to present the laser bandwidth stability that is required to maintain a constant OPE. And finally, we introduce results from an investigation into OPE-matching between different generations of exposure tools, whereby in addition to laser bandwidth control, tilt-scan methodology was employed.

BaLiF₃ single crystal has been studied as the candidate for the last lens material of the next generation high index immersion lithography system. Although the refractive index of BaLiF₃ is 1.64 at 193nm which is not sufficient for the requirement, other optical properties such as 193nm transparency and laser durability fulfill the requirement. It is estimated that the cause of both high SBR part and inhomogeneity of refractive index of BaLiF₃ seems to present along the faces of slip planes which are observed by crossed Nicol observation. As a result of comparative study of various direction perpendiculars to the growth axis, good crystallinity with less slip planes has been obtained by shifting the growth axis from <100> which is adequate for the last lens production. MgF₂ single crystal studied as the polarizer material for high power ArF laser oscillator, and crystal with excellent laser durability and large diameter (>100mm) has been developed by CZ technique. In addition crystals oriented along both c-axis and a-axis were successfully grown.

We present advancements in the manufacture of high-performance diffractive optical elements (DOEs) used in stepper/scanner off-axis illumination systems. These advancements have been made by employing high resolution lithographic techniques, in combination with precision glass-etching capabilities. Enhanced performance of DOE designs is demonstrated, including higher efficiency with improved uniformity for multi-pole illumination at the pupil plane, while maintaining low on-axis intensity. Theoretical predictions of the performance for several classes of DOE designs will be presented and compared with experimental results. This new process capability results in improved performance of current DOE designs, and enables greater customization including control of the output spatial intensity distribution for future designs. These advancements will facilitate continuous improvements in off-axis illumination optimization required by the end user to obtain larger effective lithographic process windows.

Lens heating due to absorbed UV laser radiation can diminish the achievable spatial resolution of the lithographic process in semiconductor wafer steppers. At the Laser- Laboratorium Göttingen a measurement system for quantitative registration of this thermal lens effect was developed. It is based upon a strongly improved Hartmann-Shack wavefront sensor with extreme sensitivity, accomplishing precise online monitoring of wavefront deformations of a collimated test laser beam transmitted through the laser-irradiated site of a sample. Caused by the temperature-dependent refractive index as well as thermal expansion, the formerly plane wavefront of the test laser is distorted to form a rotationally symmetric valley, being equivalent to a convex lens. The observed wavefront distortion is a quantitative measure of the absorption losses in the sample. Thermal theory affords absolute calibration of absorption coefficients.

Increasing productivity demands on leading-edge scanners require greatly improved light source availability. This translates directly to minimizing downtime and maximizing productive time, as defined in the SEMI E10 standard. Focused efforts to achieve these goals are ongoing and Cymer has demonstrated significant improvements on production light sources. This paper describes significant availability improvements of Cymer light sources enabled by a new advanced gas management scheme called Gas Lifetime eXtensio^TM (GL^TM) control system. Using GLX, we have demonstrated the capability of extending the pulse-based interval between full gas replenishments to 1 billion pulses on our XLA light sources, as well as significant extension in the time-based interval between refills. This represents a factor of 10X increase in the maximum interval between full gas replenishments, which equates to potential gain of up to 2% in productive time over a year for systems operating at high utilization. In this paper, we provide performance data on extended (1 billion pulse) laser operation without full gas replenishment under multiple actual practical production environments demonstrating the ability to achieve long gas lives with very stable optical performance from the laser system. In particular, we have demonstrated that GLX can provide excellent stability in key optical performance parameters, such as bandwidth, over extended gas lives. Further, these stability benefits can be realized under both high and low pulse accumulation scenarios. In addition, we briefly discuss the potential for future gas management enhancements that will provide even longer term system performance stability and corresponding reductions in tool downtime.

The Argon Fluoride (ArF) immersion lithography is now shifting to mass production phase for below 45nm node. For a laser light source in this node, narrower and more stable spectrum performance is required. We have introduced GT61A ArF laser light source (60W/6kHz/10mJ/0.35pm) with spectrum E95 stabilization system which meets these requirements. The narrow and stabilized spectrum performance was achieved by developing an ultra line narrowing module and Bandwidth Control Module (BCM). It contributes to the reduction of differences of the spectrum during exposure over a wafer, wafer to wafer, during machine lifetime and machine to machine for every light source. Stable laser performance is obtained for mass production. The GT61A integrated on a common and already reliability-proven GigaTwin (GT) platform, and its inherited reliability is proved with the availability over 99.5% in the field.

ArF immersion technology is spotlighted as the enabling technology for below 45nm node. Recently, double exposure technology is also considered for below 32nm node. We have already released an injection lock ArF excimer laser with ultra-line narrowed and stabilized spectrum performance: GT61A (60W/6kHz/ 10mJ/0.35pm) to ArF immersion market in Q4 2006. The requirements are: i) higher power ii) lower cost of downtime for higher throughput iii) greater wavelength stability for improved overlay and iv) increased lifetimes for lower operation costs. We have developed high power and high energy stability injection lock ArF excimer laser for double patterning: GT62A (90W/6000Hz/15mJ/0.35pm) based on the technology of GT61A and the reliability of GigaTwin (GT) platform. A high power operation of 90W is realized by development of high durability optical elements. Durability of the new optics is at least 3 times as long as that of the conventional optics used in the GT61A. The energy stability is improved more than 1.5 times of performance in the GT61A by optimizing laser operational conditions of the power oscillator. This improvement is accomplished by extracting potential efficiency of injection lock characteristic. The lifetime of power oscillator, which is one of the major parts in cost of ownership, is maintained by using higher output of the power supply.

In this paper, we show that uniaxial crystals and sapphire in particular, can be used as a lens material for high-index immersion lithography. Although uniaxial crystals are birefringent and anisotropic for unpolarized light, under certain conditions they are fully isotropic for transverse electric (TE) polarizations. The strong birefringence of the uniaxial crystal defocuses the residual TM polarization relative to the TE mode so that its image does not reach the photoresist but rather creates a small background. To manifest this property, a combination of pupil-fill polarization constraints, mask design rules and crystal alignment requirements must be satisfied. Sapphire is a well-known industrial optical material featuring high optical quality and homogeneity. Its refractive index of 1.928 at 193 nm, along with its high thermal conductivity and moderate absorption, are close to industry requirements. An implementation of sapphire under these conditions is proposed, suggesting a path to the continued scaling of 193 nm lithography numerical aperture.

Illumination for SRAM device pattern with peripheral circuit is optimized applying OPC during optimization. At first the memory cell is targeted, next library patterns that represent the peripheral circuit are added as the targets one by one, and it is investigated how the optimized illumination varies. As optimized targets ILS and dose-focus window are used. For the case of ILS the optimized illumination shapes become milder as more patterns are evaluated and the OPC result becomes weaker correspondingly. For the case of window the tendency is similar but not so intense. The illuminations optimized by ILS and window are different. The optimized illuminations by optical and resist simulation are a little different. As practical application illumination defined by functions such as annular is evaluated, where the information of actual scanners are applied. At first 1/4 divided polarization plate is used instead of tangential polarization. Secondly illumination is searched in the solution space that consists of hardware design instead of numerical expression. By introducing the information the optimized illuminations are varied. From these results it turns out that the optimization tool should handle the information of actual scanners properly. And we have developed the solution tool (k1-TUNE).

Acceptance of Sub Resolution Assist Feature (SRAF) has been widely recognized in lithography patterning. In general, with the insertion of SRAF in optically adjacent space area of design main feature, the aerial image intensity profiles of the corresponding main features are apparently being either constructively or destructively alternated at imaging plane [Figure 1]. From lithography patterning perspective, the optimized or better pattern imaging process requires constructive SRAF. Such SRAF is inserted into available space for main feature to obtain optimal or better image contrast, better imaging resolution and depth of focus (DOF) which is similar or close to optimal focus latitude. However, the complementary destructive SRAF insertion can adversely occur in certain circumstances. In this paper, we study the theoretical understanding of the constructive and destructive effects against design main features imaging associated with the efforts to include SRAF (it's either driven by rule, model or mishap). In addition, an evaluation scheme is developed and being explored in many aspects in order to describe the constructive and destructive response of inserted SRAF. Such evaluation scheme has derived an application to detect the degree of SRAF insertion coverage accuracy, impact on manufacturing, and most usefully, to access potential layout required optimization in design space based on these complementary effects mechanism throughout several off-axis illumination conditions. eature

As semiconductor technologies move toward 90nm generation and below, contact hole is one of the most challenging features to print in the semiconductor manufacturing process. There are two principal difficulties in order to define small contact hole pattern on wafer. One is insufficient process margin besides poor resolution compared with line & space pattern. The other is that contact hole should be made through pitches and sometimes random contact hole pattern should be fabricated. Therefore advanced ArF lithography scanner should be used for small contact hole printing with RETs (Resolution Enhancement Techniques) such as immersion lithography, OPC(Optical Proximity Correction), PSM(Phase Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant Feature), mask biasing and thermal flow. Like this, ArF lithography propose the method of enhancing resolution, however, we must spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF. In this paper, we suggest the method of contact holes patterning by using KrF lithography tool in 90nm sFlash(stand alone Flash)devices. For patterning of contact hole, we apply RETs which combine OAI and Model based OPC. Additionally, in this paper we present the result of hole pattern images which operate ArF lithography equipment. Also, this study describes comparison of two wafer images that ArF lithography process which is used mask biasing and Rule based OPC, KrF lithography process which is applied hybrid OPC.

As the pattern size shrinking down below 1/4 of the exposure wavelength, the NA of exposure tool has to be increased proportionally. The use of hyper NA and immersion exposure system for improving image quality may result in a small workable process window. Hence, resolution enhancement technology (RET) becomes a necessity for semiconductor manufacturing. Previous studies have demonstrated many RETs, such as CPL, DDL, IML and DPT etc. can improve the process window for different applications.1,2,3,4 In this work, we show manufacturing implementation of a 32nm node SRAM cell with different RET approaches. The diffusion, poly, contact, and metal layers were chosen as the target design. The process development project starts from the wafer exposure scheme setting, which includes the multi-exposure, illumination shape and mask type. After the RET has been specified, the process performance indexes, such as MEEF, PW, and CDU are characterized by using both simulation and empirical data. The mask design and OPC is implemented After the mask data preparation step, we then optimize exposure parameters for best printing performance and follow it by verifying actual wafer data. The mask making spec and DFM design rule constrains have been assessed and recommended for 32nm node manufacturing. Also, we have examined the immersion process defect impact and control methodology for production environment. In this paper, we report the result of optimizing RET process (including mask data generation, reticle making specifications, and wafer printing) for 32nm SRAM. With 193nm ultra high NA immersion exposure scanner (such as ASML /1900), it is capable of meeting 32nm SRAM manufacturing requirement.

Printing random Contact Holes (C/H) is one of the most difficult tasks in current low-k1 lithography. Different approaches have been proposed and demonstrated successfully. One approach is the use of extensive Resolution Enhancement Technique such as sub-resolution assisting features, focus drilling and interference mapping lithography in combination with strong off-axis illumination. These techniques often lead to enhanced complexity at the OPC and mask making side. In order to keep the complexity low, soft illumination modes have been proposed like Soft-Annular (bull'seye) and Soft-Quasar type illumination [1]. It has been shown that the minimum k₁ for the latter route is k₁=0.41 using experimental results up to 0.93 NA. In this paper we demonstrate that the latter route can be extended to 45nm C/H at a minimum pitch of 120nm when using 1.35 NA. In order to achieve this we additionally applied a CD sizing technique to create the very small C/H.

At 45 and 32 nm nodes, one of the most critical layers is the Contact one. Due to the use of hyper NA imaging, the depth of focus starts to be very limited. Moreover the OPC is rapidly limited because of the increase of the pattern density. The limited surface in the dark field region of a Contact layer mask enforces the edges movement to stop very quickly. The use of SRAF (Sub Resolution Assist Feature) has been widely use for DOF enhancement of line and space layers since many technology node. Recently, SRAF generated using inverse lithography have shown interesting DOF improvement1. However, the advantage of the ideal mask generated by inverse lithography is lost when switching to a manufacturable mask with Manhattan structures. For SRAF placed in rule based as well as Manhattan SRAF generated after inverse lithography, it is important to know what their behavior is, in term of size and placement. In this article we propose to study the placement of scatter-trenches assist features for the contact layer. For this we have performed process window simulation with different SRAF sizes and distance to the main OPC. These results permit us to establish the trends for size and placement of the SRAF. Moreover we have also take a look of the advantages of using 8 surrounding SRAF (4 in vertical - horizontal and 4 at 45°) versus 4 surrounding SRAF. Based on these studies we have seen that there is no real gain of increasing the complexity by adding additional SRAF.

In development of optical proximity correction (OPC) for new technology nodes, optimization of assist features requires multiple placement scenarios for each line/space or hole combination. Additionally, illumination and process conditions are varied to determine the optimal process window. Under some illumination and process conditions, optimal printing of the desired features is attained; however, undesired printing of sidelobes or sub-resolution assist features (SRAFs) also occurs. Currently, CD sizes are measured for the desired feature and images are hand checked for unwanted features (sidelobe or SRAF printing). This takes a large amount of time, given the hundreds to thousands of CDSEM measurements required to generate a given OPC model. This problem is multiplied if several passes of data collection are needed to optimize each OPC model and each layer. An automated method has been developed to quickly screen a large number of SEM images for unwanted features, and if they exist, flag the measurement point so it can be easily identified as an undesirable area of the process window. This method employs edge placement measurement capabilities available with automated SEM recipe generation software to identify the presence of an unwanted feature within a given image. A simple Boolean filter is used to exclude this process area as SRAF or sidelobe printing process space so it may be excluded from the OPC model and from the operational process space. This automated method for identification of SRAFs or sidelobes provides significant engineering time savings and allows characterization of the onset of undesirable features to assist in optimization of OPC within a given process window.

Attenuated PSM (Phase Shift Mask) has been widely adopted in contact lithography to enhance the resolution and process latitude. While the main drawback associated with the use of attenuated PSM is the side lobe printing, which yields unwanted resist erosion of area among patterned holes. Side lobes, if etched and filled in the following semiconductor processing, can cause electrical shorting, chip failure and device reliability problem, hence any side lobes are extremely undesirable. Usually, the side lobe detection for simple layouts can be conducted manually through the help of lithography simulation tools, but the detection of potential side lobe printing becomes far more challenging for full-chip production layouts. An efficient side-lobe detection approach was demonstrated in this study, with the use of assistant ring, polygon-based simulation instead of grid-based simulation has been enabled for full-chip side lobe detection. Furthermore, a model-based method for side lobe suppression was also demonstrated in our flow.

A novel RET, which enables on-grid sub-50 nm hole pattern formation with ArF immersion lithography, has been developed. One of the authors has found quasi-iso-focal point image generation at the center of square area of high transmission embedded attenuating phase shift mask (EA-PSM), where four small openings are laid out at the corners of the area, utilizing an optimized quadrupole illumination. As an extension of continuous configuration, checker-board like mask pattern arrangement is created. In the mask, small openings and opaque pads are arranged like as checkerboard, whose base pitch is around resolution limit of targeted optical system. The mask pattern arrangement is named as "Checker-Board PSM (CB-PSM)". By eliminating any one opening from "checker-board", very fine point image is generated at the place. Because four openings around the eliminated one are necessary for the fine imaging characteristic, minimum distance between the point images is about the double of that for resolution limit. After simulation study of imaging, experiments are carried out to prove the fine imaging performance utilizing ArF immersion optics with NA=1.07 and a tri-level resist system. As a result, sub-50nm isolated hole is successfully formed with DOF larger than 200 nm. Simultaneously, ~ 60 nm semi-dense hole with pitch of 240 nm is printed with over 200 nm DOF. Moreover, application of conventional mask pattern arrangement, ultimately dense hole of 140nm pitch is well formed. As a conclusion, we believe that CB-PSM is a promising candidate for hole pattern formation at 32 nm node and beyond.

Resolution enhancement technology (RET) refers to a technique that extends the usable resolution of an imaging system without decreasing the wavelength of light or increasing the numerical aperture (NA) of the imaging tool. Offaxis illumination (OAI) and a phase shift mask (PSM) are essentially accompanied by optical proximity correction (OPC) for semiconductor device manufacturing nowadays. A chromeless PSM (CLM or CPL) is compared to an attenuated PSM (att.PSM) to make 45 nm dense line and space pattern. To obtain the best possible resolution, a proper OPC is required with CPL and the most common application of OPC technique is the use of space bias. The optical system with a high numerical aperture (NA), a strong OAI, and a proper polarization can decrease the k1 value well below 0.3. CPL has various advantages over alternating PSM such as no necessity of double exposure, small pattern displacement, and no CD error caused by the intensity imbalance. But CPL has some disadvantages. In the case of 100 % transmittance pure CPL, there is no shading material that is usually deposited on the line pattern for both att.PSM and alternating PSM to control the line width. Because of no shading material for CPL, the required resist critical dimension (CD) has to be obtained by using phase only and it is difficult to control the resist CD through pitch. As expected, CPL needs smaller dose than att.PSM to make the desired 45 nm CD with 0.94 NA. Our simulation results showed that 10 nm negative bias is optimum for CPL mask. We demonstrated that CPL mask and att.PSM technology can be used to make 45 nm node by the negative space bias.

It is well-known that the available depth of focus (DoF) tend to decrease for each advancing technology node. Moreover the leveling control on wafer topography has become a challenge to affect the focus control on exposure tool capability, especially for the critical hole-structure layer of the back end of line (BEoL). In this study, we used the via layer from the real products as an example of optimizing the exposure tool's leveling system to reduce process-related influences to improve the intra-field focus control range. First, the focus-exposure matrices (FEMs) were applied to a wafer in different leveling modes. Then, patterns' critical dimension (CD) in different locations within the same field were measured to produce the Bossung curves required to determine the best focus. The same steps were repeated on a bare wafer to illustrate how the process reduced the common depth of focus range. We also introduced the non-optical leveling sensor, which measured the wafer by the use of physical methods. Since it does not interact with the film stack or the pattern density, the measurement accuracy will be insensitive to process variation. Therefore, it can be used to compensate the optically induced errors from the optical leveling system and to expand the useful depth of focus for improving CD uniformity. Finally, we briefly summarize the improvement ratio achieved of the common DoF using these optical and non-optical leveling systems with different leveling modes.

In this paper, a study on customized illumination shape configurations as resolution enhancement for 45nm technology node will be presented. Several new source shape configurations will be explored through simulation based on 193nm immersion lithography on 6% Attenuated Phase Shift Mask. Forbidden pitch effect is commonly encountered in the application of off axis illumination (OAI). The illumination settings are often optimized to allow maximum process window for a pitch. This is done by creating symmetrical distribution of diffraction order on the pupil plane. However, at other pitch, the distribution of diffraction order on the pupil plane results in severe degradation in image contrast and results in significant critical dimension (CD) fluctuation. The problematic pitch is often known as forbidden pitch. It has to be avoided in the design and thus limited the pitch range to be imaged for particular illumination. An approach to modify off axis illumination to minimize the effect of forbidden pitch is explored in this study. The new customized shape for one dimensional line and space pattern is modified from current off axis illumination. Simulation study is done to evaluate the performance some customized shapes. The extent of CD fluctuation and CD through pitch uniformity is analyzed to determine the performance enhancement of the new illumination shapes. From simulation result, the proposed modification have significantly improved the through pitch performance and minimized the effect of forbidden pitch.

As the semiconductor industry continues progressing toward increasingly complex and unforgiving processes of device shrinkage and shorter duration of device development, many industry participants from photo-lithography are taking interest in material and structure of the photolithography mask. Due to shorter wavelength of the source laser and device technology ranging around the order of magnitude for the source laser wavelength (ArF), the difference in mask material and structure shows greater performance difference then larger technology node. Especially around 50nm and beyond, many industry followers are reporting better performance from different types of mask then previously used. In this study, we will analyze the effect of the photo lithography mask material for sub 50nm device, in development perspective. Two major types of mask will be evaluated on the scale of device development. Effects such as Mask Error Effect Factor (MEEF), Depth of Focus (DOF), Exposure Latitude (EL) and Critical Dimension Uniformity (CDU) will be analyzed for both binary and attenuated phase shifted mask under different process condition. Also, we will evaluate the comparison result for application on development of sub 45nm device.

HTPSM (High-Transmission Phase Shift Mask) is one of the most promising mask technologies for photolithography resolution enhancement. However, it s well known that the use of HTPSM frequently results in unwanted patterns due to inevitable pinching effects, particularly in spacious areas. Although pinching effect can be effectively suppressed by the application of additional Cr patterns at the problematic locations, it is a critical challenge to systematically detect and automatically correct the complicated patterns in most of realistic cases. We demonstrated remarkable photolithography process window improvement by the use of HTPSM (A type and above) with the focus on the development of a systematic methodology for automatic detection and correction of abnormal patterns due to optical pinching effect. Regular optical rules check (ORC) with specific modifications was employed to precisely locate the potential pinched areas, whereas enhanced design rules check (DRC) was applied subsequently to generate the required additional Cr patterns for final mask fabrication. A variety of photolithography variables, such as wavelength and numerical aperture (NA) were extensively investigated against optical pinching effect to confirm the feasibility and accuracy of the proposed detection/correction methodology for HTPSM application.

Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology.

We discussed to KrF process extension for 90 nm technology node. The continuous shrinkage of critical dimensions on sub 130 nm devices becomes a key point to improve process margin with pattern resolution problem for lithography. Recently, according to development demand of high density and high integration device, it is tendency that the shrink rate of design rule is gradually accelerated. It is difficult to develop with image contrast problem around k1=0.25 which is a theoretical process limit region. We need to technology development which is available to having resolution for sub 90nm line and space by using KrF lithography not by using ArF lithography. In generally, KrF have not been used in nano-process such as 90nm technology. In this study, however, we can apply the KrF in 90nm technology by means of minimizing the error range in the nano-process, optimizing the process, and extending the process margin. This Application of KrF in 90nm technology results in elimination of additional investment for development of 90nm technology. Finally, we will show which simulation and experimental results such as normalized image log slope, pupil plane, image of focus variation, process window, top view image, photo resist and etch profile, and pitch linearity.

The ever increasing NA to meet the stringent requirements on pitch and litho target does not come without a price. In particular for the printing of contact layers, the toll is taken in terms of decreased process latitudes and CD uniformity. Depending on the specific contact layer design, it has become increasingly important to choose the most adequate resolution enhancement technique. At the ultimate NA of 1.35, depth of focus through pitch has become a key factor, and values in the order of 100-120nm are the painful truth imposed by physics. In this paper, the attention goes to through-pitch contact imaging, with the attempt to achieve half pitches around 60nm. Thereby, the main focus lies on the relation between source shape and minimum achievable k₁. In addition, the pro's and con's of two options for throughpitch process latitude enhancement are considered. These options are firstly the effect of assist feature placement in combination with off-axis illumination, and secondly the application of the Focus Drilling technique. Finally, the different contributions to contact hole CD non-uniformity are addressed.

Immersion Lithography is the most important technique for extending optical lithography's capabilities and meeting the requirements of Semiconductor Roadmap. The introduction of immersion tools has recently allowed the development of 45nm technology node in single exposure. Nevertheless the usage of hyper-high NA scanners (NA > 1), some levels still remain very critical to be imaged with sufficient process performances. For memory devices, contact mask is for sure the most challenging layer. Aim of this paper is to present the lithographic assessment of 193nm contact holes process, with k₁ value of ~0.30 using NA 1.20 immersion lithography (minimum pitch is 100nm). Different issues will be reported, related to mask choices (Binary or Attenuated Phase Shift) and illuminator configurations. First phase of the work will be dedicated to a preliminary experimental screening on a simple test case in order to reduce the variables in the following optimization sections. Based on this analysis we will discard X-Y symmetrical illuminators (Annular, C-Quad) due to poor contrast. Second phase will be dedicated to a full simulation assessment. Different illuminators will be compared, with both mask type and several mask biases. From this study, we will identify some general trends of lithography performances that can be used for the fine tuning of the RET settings. The last phase of the work will be dedicated to find the sensitivity trends for one of the analyzed illuminators. In particular we study the effect of Numerical Aperture, mask bias in both X and Y direction and poles sigma ring-width and centre.

The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

Including etch-based empirical data during OPC model calibration is a desired yet controversial decision for OPC modeling, especially for process with a large litho to etch biasing. While many OPC software tools are capable of providing this functionality nowadays; yet few were implemented in manufacturing due to various risks considerations such as compromises in resist and optical effects prediction, etch model accuracy or even runtime concern. Conventional method of applying rule-based alongside resist model is popular but requires a lot of lengthy code generation to provide a leaner OPC input. This work discusses risk factors and their considerations, together with introduction of techniques used within Mentor Calibre VT5 etch-based modeling at sub 90nm technology node. Various strategies are discussed with the aim of better handling of large etch bias offset without adding complexity into final OPC package. Finally, results were presented to assess the advantages and limitations of the final method chosen.

Within the past several years, IC design and manufacture technology node transits rapidly from 0.13um to 65nm and 45nm. Whatever the technology node is, the same goal that both the designer and the manufacturer put most of their effort on is how to improve the chip yield as high as possible. A bunch of evidences have shown that the final yield is extremely related to the pattern transfer from design to wafer. But with the critical dimension shrinks, the largest challenge that the whole industry meets is how to keep high fidelity while transferring the patterns. Since the process window is now very limited even with the assistance of kinds of resolution enhancement technology, a tiny process deviation may cause large critical dimension variation, which will result in significant device character change. Micro-lithography combined with Optical proximity correct is supposed to be the most critical stage in pattern transfer stage. But conventional OPC always use nominal model, which will not take random process variation into account during applying OPC. This work will demonstrate our experiment in OPC with process window model, which is then proved to have obvious improvement in pattern fidelity.

The lithographic processes and resolution enhancement techniques (RET) needed to achieve pattern fidelity are becoming more complicated as the required critical dimensions (CDs) shrink. For technology nodes with smaller devices and tolerances, more complex models and proximity corrections are needed and these significantly increase the computational requirements. New simulation techniques are required to address these computational challenges. The new simulation technique we focus on in this work is dense optical proximity correction (OPC). Sparse OPC tools typically require a laborious, manual and time consuming OPC optimization approach. In contrast, dense OPC uses pixel-based simulation that does not need as much manual setup. Dense OPC was introduced because sparse simulation methodology causes run times to explode as the pattern density increases, since the number of simulation sites in a given optical radius increases. In this work, we completed a comparison of the OPC modeling performance and run time for the dense and the sparse solutions. The analysis found the computational run time to be highly design dependant. The result should lead to the improvement of the quality and performance of the OPC solution and shed light on the pros and cons of using dense versus sparse solution. This will help OPC engineers to decide which solution to apply to their particular situation.

As tolerance requirements for the lithography process continue to shrink with each new technology node, the contributions of all process sequence steps to the critical dimension error budgets are being closely examined, including wafer exposure, resist processing, pattern etch, as well as the photomask process employed during the wafer exposure. Along with efforts to improve the mask manufacturing processes, the elimination of residual mask errors via pattern correction has gained renewed attention. The portfolio of correction tools for mask process effects is derived from well established techniques commonly used in optical proximity correction and in electron beam proximity effect compensation. The process component that is not well captured in the correction methods deployed in mask manufacturing today is etch. A mask process model to describe the process behavior and to capture the physical effects leading to deviation of the critical dimension from the target value represents the key component of model-based correction and verification. This paper presents the flow for generating mask process models that describe both shortrange and long-range mask process effects, including proximity loading effects from etching, pattern density loading effects, and across-mask process non-uniformity. The flow is illustrated with measurement data from real test masks. Application of models for both mask process correction and verification is discussed.

We formulate the mask modeling as a parametric model order reduction problem. We then apply a robust reduction technique to generate the compact mask model. Since this model is based on first principle, it naturally includes diffraction, polarization and couplings, important effects that are poorly handled by the modified thin-mask model (MTMM). The model generation involves only a few sampling solves of the governing equation, much fewer than that needed to generate MTMM. Though the model evaluation takes marginally more CPU time than MTMM, the accuracy and the robustness of the new model are based on much more rigorous theoretical foundation.

Resolution enhancement technologies (RET), such as optical proximity correction (OPC) help us develop sub- 100nm technology node by using photolithography equipments and materials for 130nm photolithographic process. Because the resolution of scanner and materials has arrived almost at their limit, small patterns below resolution limit are more sensitively affected by very small tolerance of various factors which were not considered by major process parameters such like lens flare, reticle haze, reticle critical dimensional (CD) errors, etc. As patterning small ones under resolution limit directly means large MEEF (mask error enhancement factor) in photo process, reticle CD errors are actually magnified on wafer. Therefore, reticle CD errors should be tightly controlled when we try to define small patterns under resolution limit. As the feature size shrinks down, the importance of OPC model accuracy grows up for the purpose of ensuring high pattern fidelity. In conventional process of OPC model generation, we don't concern how mask database CDs are exactly matched with real reticle CDs, since the specification of reticle CD is enough tight to ignore CD variation on the reticle such as 1-dimensional CD difference, linearity CD uniformity. But in the process with large MEEF, OPC model with incorrect CD information of reticle has a bad influence to prediction pattern fidelity. In this paper, we describe the effect of reticle CD errors on the OPC model accuracy. To quantify that effect, we compared two cases of OPC model generation. One is making OPC model by using mask database CDs themselves, the other is by using mask real CDs in 110nm node for poly and metal 1 (damascene) layers. As a consequence of the test, we can achieve the accuracy OPC model calibrated with reticle CD errors which better predicts wafer CDs and 2- dimensional images than the model, calibrated by original database CDs.

The concept of focus blur encompasses the effect of laser bandwidth longitudinal chromatic aberration and scanner stage vertical vibration. The finite bandwidth of excimer laser source causes a corresponding finite distribution of focal planes in a range of 100nm or larger for the optical lithography system. Similarly, scanner vertical stage vibration puts the wafer in a finite distribution of focal planes. Both chromatic aberration and vertical stage vibration could introduce significant CD errors, hence can no longer be ignored in current lithography processes development and OPC development that require CD control within a few nanometers. We developed several methodologies to model the laser chromatic aberration and vertical stage vibration in OPC (Optical Proximity Correction) modeling tool. Extensive simulations were done to calculate chromatic aberration and vertical stage vibration focus blur's impact on lithography patterning for a variety of test structures. Chromatic aberration and vertical stage vibration focus blur effect was further included as an regression term in experimental OPC model calibration to capture its impact on litho patterning, and significant benefit to OPC model calibration was observed.

Flare has become a significant problem for low K₁ lithography process.[1] It is generally divided into three parts: long-, local-, short-range. Long-range flare is scattering over a scale of tens of microns, come from reflections within the projection lens. Short-range is scattering over a scale of about 1 micron or less, come from lens aberrations. And localrange flare is scattering over about 1 to 10 microns, comes from inhomogenieties within glass and local pattern density. Especially, local-range flare causes the printed width to vary or degrade printing accuracy. Normally, the local-range flare effect is increase by local pattern density. Therefore the local flare effect can be reduced if the effect of local pattern density within die is compensated effectively. In this paper, we discussed full chip compensation for local flare effect using OPC/DRC method. First of all, we investigated relationship between local flare and pattern density using test pattern and extracted OPC model according to pattern density and also analyzed within chip pattern density distribution using DRC. We separated original layout to OPC target layout according to local pattern density, applied different OPC model to each separated layout. We will show within chip CD variation was improved after local flare effects reduction.

When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will be below the k1 limit of 0.25. If EUV technology is not ready for mass production, double patterning technology (DPT) is one of the solutions to bridge the gap between wet ArF and EUV platforms. DPT technology implies a patterning process with two photolithography/etching steps. As a result, the critical pitch is reduced by a factor of 2, which means the k1 value could increase by a factor of 2. Due to the superimposition of patterns printed by two separate patterning steps, the overlay capability, in addition to image capability, contributes to critical dimension uniformity (CDU). The wafer throughput as well as cost is a concern because of the increased number of process steps. Therefore, the performance of imaging, overlay, and throughput of a scanner must be improved in order to implement DPT cost effectively. In addition, DPT requires an innovative software to evenly split the patterns into two layers for the full chip. Although current electronic design automation (EDA) tools can split the pattern through abundant geometry-manipulation functions, these functions, however, are insufficient. A rigorous pattern split requires more DPT-specific functions such as tagging/grouping critical features with two colors (and hence two layers), controlling the coloring sequence, correcting the printing error on stitching boundaries, dealing with color conflicts, increasing the coloring accuracy, considering full-chip possibility, etc. Therefore, in this paper we cover these issues by demonstrating a newly developed DPT pattern-split algorithm using a rule-based method. This method has one strong advantage of achieving very fast processing speed, so a full-chip DPT pattern split is practical. After the pattern split, all of the color conflicts are highlighted. Some of the color conflicts can be resolved by aggressive model-based methods, while the un-resolvable conflicts, known as native conflicts, require a change in the design to achieve a DPTfriendly design. A model-based stitching boundary correction is then used after the color conflicts are corrected. Finally the OPC treatment is implemented on both split layouts. The OPC challenges are highlighted by examining the printed image from both exposures. The key concepts described above with additional full chip requirements have been successfully implemented onto Brion's Tachyo^TM system. The efficiency and accuracy of the DPT pattern split method were evaluated on a full-chip layout. The results show that the algorithm proposed in this paper is a viable solution for the DPT pattern split.

An important step in today's Integrated Circuit (IC) manufacturing is optical proximity correction (OPC). In model based OPC, masks are systematically modified to compensate for the non-ideal optical and process effects of optical lithography system. The polygons in the layout are fragmented, and simulations are performed to determine the image intensity pattern on the wafer. Then the mask is perturbed by moving the fragments to match the desired wafer pattern. This iterative process continues until the pattern on the wafer matches the desired one. Although OPC increases the fidelity of pattern transfer to the wafer, it is quite CPU intensive; OPC for modern IC designs can take days to complete on computer clusters with thousands of CPU. In this paper, techniques from statistical machine learning are used to predict the fragment movements. The goal is to reduce the number of iterations required in model based OPC by using a fast and efficient solution as the initial guess to model based OPC. To determine the best model, we train and evaluate several principal component regression models based on prediction error. Experimental results show that fragment movement predictions via regression model significantly decrease the number of iterations required in model based OPC.

Various resolution enhancement techniques have been proposed in order to enable optical lithography at low k1 imaging, e.g. alt-PSM (phase shift mask), chromeless phase lithography (CPL), double exposure technique (DET) and double dipole lithography (DDL). In spite of its low throughput in production, DDL technique is a very attractive solution for low k1 process because of the relatively low cost of binary or attenuated phase shift masks, which can be combined with strong dipole illuminations and flexible SRAF rule to enhance the process window. Another attraction of DDL is that dry scanner still can be used for 45nm node instead of expensive immersion lithography process. In this paper, two aspects for DDL application have been focused on. The first one is OPC optimization method for DDL, which includes SRAF optimization, mask decomposition and pixel-based OPC. The whole flow is optimized specifically for DDL to achieve satisfactory pattern results on wafer. The second is the overlay issue. Since two DDL masks are exposed in turn, the overlay variation between two masks becomes dominant factor deteriorating pattern quality. The effect of overlay tolerance is also studied through process window simulation. DDL has been demonstrated to be capable of 45nm node logic with dry scanner. The pattern fidelity and process window of 45nm node SRAM & Random Logic are evaluated for active/gate layer and dark field metal layer.

At 65 nm and below, full-chip verification of OPC is done for nominal dose and focus, as well as for process corners representing a two-to-three sigma deviation from the manufacturing setpoints. Such an approach interrogates the intersection of design layout with process variation to elucidate specific locations which will tend to be yield-limiting in manufacturing. With vanishingly small margins between allowable process windows and real in-fab variability, it is of utmost importance to optimize the critical exposure parameters such as projection optic numerical aperture, illumination source mode and sigma, and source polarization. The traditional approach to optimizing these exposure conditions has involved selecting representative feature test patterns (such as 1D lines at multiple pitches, or memory cells), placing simulation cutlines across selected locations, establishing allowable CD tolerances, and calculating overlapping process windows for all cutlines of interest. Such approaches are to first order effective in coarse tuning exposure conditions, but underutilize the rich information content which is available from today's rapid large-area post-OPC simulation engines. We report here on the use of full-chip post-OPC simulation and error checking in conjunction with illumination optimization tooling to provide a more thorough and versatile statistical analysis capability. It is shown that the new method proposed here results in a more robust process window than that which would be obtained by the conditions selected using the traditional optimization method.

Optical proximity correction (OPC) of contact-hole printing is challenging since its two dimensional shapes requires through understanding of lithographic processes compared to one dimensional line and space pattering. Moreover, recently, it is common to use "elongated contact holes" with large contact area, rather than simple circular ones, for small electrical resistance. These elongated contact holes make it even more difficult to generate a good OPC model than the circular ones because the elongated contact-hole patterning causes the asymmetric process effects. For example, impacts of mask CD error, resist diffusion and resist development are different depending on the orientation of the elongated contact holes. This paper presents how the OPC model for the elongated contact-hole can be improved as the mask CD error compensation, accurate resist diffusion model and a new Variable Threshold Model (VTM) are applied for the asymmetric process effects.

Recently, there have been many studies on the mask topography effect on patterning. Most of existing papers report generally focused on the difference of the aerial image between the thin mask approximation and the rigorous topographic mask models. In this paper, the mask topography effect was analyzed from an OPC modeling perspective. We compared the accuracy of two types of the virtual OPC model of contact patterns that one model used the virtual test patterns generated by the lithography simulator based on the thin mask approximation model and the virtual test patterns of another model were made by the rigorous topographic mask simulation based on FDTD (Finite Difference Time Domain) method. All conditions of lithography simulations and OPC modeling between two models were same except the mask topography parameters in generating virtual test patterns. Differences in model accuracy and convergence values of regression parameters of each models indicated that current OPC modeling tool based on the thin mask approximated optical simulation did not sufficiently cover the mask topography effect, and 3D mask effect should be considered more carefully.

Test pattern data set filtering based on the concept of parameter sensitivity is proposed to reduce OPC time-to-model requirements. The concept of parameter sensitivity-based filtering is discussed briefly, followed by a methodology to apply the filtering to test pattern sets prior to data measurement along with a number of potential data filtering algorithms. The proposed methodology is then applied to an experimental data set targeted for a 32nm logic process. Qualitative observations are made on the initial data filtering, followed by quantitative metrics based on best-fit models for each of the data filtering algorithms. Results demonstrate that a comparable model is achievable using the proposed data filtering methods and one of the filtering algorithms.

As the patterning of IC manufacturing shrinks to the 32-nm node and beyond, high-NA and immersion lithography are required for pushing resolution to its physical limit. To achieve good OPC performance, various physical effects such as polarization, mask topography, and mask pellicle have to be considered to improve the model accuracy. The attenuation and the phase variation of TE and TM wave components induced by the pellicle would impact optical qualities in terms of resolution, distortion, defocus shift, and high-order aberrations. In this paper, the OPC model considering pellicle effects is investigated with Jones pupil. The CD variation induced by the pellicle effect can be predicted accurately. Therefore, the improvement on model accuracy for 32-nm node is demonstrated.

OPC models have been improving their accuracy over the years by modeling more error sources in the lithographic systems, but model calibration techniques are improving at a slower pace. One area of modeling calibration that has garnered little interest is the statistical variance of the calibration data set. OPC models are very susceptible to parameter divergence with statistical variance, but modest caution is given to the data variance once the calibration sequence has started. Not only should the calibration data be a good representation of the design intent, but measure redundancy is required to take into consideration the process and metrology variance. Considering it takes five to nine redundant measurements to generate a good statistical distribution for averaging and it takes tens of thousands of measurements to mimic the design intent, the data volume requirements become overwhelming. Typically, the data redundancy is reduced due to this data explosion, so some level of variance will creep into the model-tuning process. This is a feasibility study for treatment of data variance during model calibration. This approach was developed to improve the model fitness for primary out-of-specification features present in the calibration test pattern by performing small manipulations of the measured data combined with data weighting during the model calibration process. This data manipulation is executed in image-parameter groups (Imin, Imax, slope and curvature) to control model convergence. These critical-CD perturbations are typically fractions of nanometers, which is consistent with the residual variance of the statically valid data set. With this datamanipulation approach the critical features are pulled into specification without diverging other feature types. This paper will detail this model calibration technique and the use of imaging parameters and weights to converge the model for key feature types. It will also demonstrate its effectiveness on realistic applications.

Low K1 photolithography process increases the complexity of RET applications in IC designs. As technology node shrinks, pattern density is much denser along with much smaller geometry dimensions. Model-based OPC (Optical Proximity Correction) and post-OPC verification require more complex models and through process window compensated approaches, which significantly increase computational burden. Both lithographical challenges and computational complexity associated with 45nm process and below create a need for advanced capabilities on commercial OPC tools. To answer those challenges, hardware-accelerated OPC solution made a debut to solve runtime bottleneck issues, but they came in with very expensive price tags. As today, there are no explorations on the linkage between design styles and layout pattern OPC reusability. This paper introduces a new OPC flow with pattern-centric approach to leverage OPC knowledge of repeated design cells and patterns to achieve fast full chip OPC convergence, shorter cycle time, better OPC quality, and eventually lead to high manufacturing yields. In this paper, the main concepts of pattern-based OPC flow are demonstrated in 65nm customer memory designs. Pattern-based OPC is a natural extension of Anchor's pattern-centric approaches in DFM (Design for Manufacturing) domain.

We establish criteria to recognize extreme OPC corrections and discuss their difference from the traditional corrections. Then we present new proximity correction methods for rigorous bi- and tri- tone mask optimization that cast problem as a constraint minimization over the space of piecewise constant or continuous functions. The primary optimization objective is stated as a contour integral over the target. The constraints on image amplitude form convex functionals for dark areas and non-convex functionals for bright areas. A Lagrangian of this constrained problem is minimized. This delivers extreme, aggressive mask corrections, which are not confined by the fragmentation schema or the orientation of its sites. We analyze performance of these corrections under challenging process conditions and evaluate fidelity benefits.

The low k1-factor challenge in current photolithography has made OPC (Optical Proximity Correction) indispensable for critical patterning layers, and more efforts are needed in the development and calibration of OPC model. One of the key factors that affect the accuracy of wafer result is the accuracy of OPC model, and usually, only a few nanometers' fitting residual of OPC model is tolerable. So, several methods have been reported for improving the accuracy of OPC modeling, but the model fitting becomes more complex as the increase of fitting parameters accordingly. In this paper, the variable loading kernel to manipulate the behavior of OPC modeling was reported. The variable load kernel can be modified by space domain, and it also can be the combination of many load kernels, such as K_load= a₁*_Kload1 + a₂*_Kload2 + ...... + a_n*_Kloadn. By combining of different variable load kernels, the resultant load kernel can be more flexible to manage the model behavior in different line widths and pitches. In the example of OPC fitting residuals of linearity patterns, it is obvious that the different models with different loading kernels yielded different residuals. The use of variable loading kernel achieves the satisfied small residuals for both small and large patterns simultaneously. Accordingly, easier OPC modeling with smaller fitting residual is anticipated by variable load kernel method.

CD control specifications for poly gate patterning are becoming tighter and tighter: latest revisions of International Technology Roadmap for Semiconductors require a CD control in the range of 2.2nm (3σ) for the 65nm technology node. In this scenario model-based Optical Proximity Correction methodologies, traditionally developed to address optical and resist development effects, had to face the challenge to correct post-resist processing steps with the aim to guarantee a final effective CD control within expected specifications. Complex 1D rule-based corrections, applied in the past, are no more adequate to capture complex 2D effects becoming relevant starting from 90nm node; only a more comprehensive 2D model-based approach can correctly predict, and so compensate, complex physical and chemical etch phenomena inducing CD variations. In this paper we experimentally study the impact of medium and long range etch effects on poly gate patterning, trying to identify their nature and impact on intra-die CD variations. Different innovative model-based approaches for lithography and etch effects compensation are evaluated and compared on Flash memory circuitry (90, 65 and 45 nm node) with the aim to reduce intra-die CD dispersion component. Finally the impact of local and global pattern density on etch behavior is studied in relation to different dummy placement strategies.

Model-based Optical Proximity Correction (MBOPC) has become one of the most important resolution enhancement technologies (RETs), which can effectively improve the image fidelity and process robustness. MBOPC is performed by iteratively shifting the polygon edges of mask patterns until convergence requirements are achieved. In this paper, we specifically discuss the design of feedback controllers to improve MBOPC convergence. Effective controller design rules are derived from the OPC results of several circuit layouts. Meanwhile, resist models also significantly affect MBOPC convergence. Two kinds of resist model have been proposed for MBOPC such as constant threshold resist model (CTRM) and variable threshold resist model (VTRM). We propose a novel CTRM, called pattern-based optimal threshold determination (PBOTD). By normalized mean square error (NMSE) formulation, appropriate threshold values with minimum NMSE can be determined to improve image fidelity, and effectively decrease iterations required. The effectiveness of applying both optimized controller and PBOTD is demonstrated on a 90-nm SRAM cell.

Flare is unwanted light arriving at the wafer and light causing negative impact on pattern formation. It is caused by scattered light from lens surfaces, problem on lens design, or problem on lens manufacture. The impact of flare varies printed line widths or drops CD uniformity accuracy in full chip. And, It is an added incoherent background intensity that will degrade OPC(Optical Proximity Correction) accuracy[1]. In this paper, we discussed CD variation, MEEF (Mask Error Enhancement Factor) and OPC accuracy by the flare effects. Flare is bound up with local pattern density. Local pattern density influences background intensity by flare or stray light. So we studied CD variation, MEEF, OPC modeling data with local pattern density by several experiment. Also, in this study, we will discuss test pattern drawing for OPC modeling data, analyze CD difference between OPC test pattern with considering flare effect and test pattern with regardless flare effect and MEEF value by flare effect. MEEF is main factor that influences lithography process margin. This paper will show test pattern optimization in OPC modeling.

The development of efficient resist models for optical and process proximity correction (OPC) is a problem of particular importance in microlithography. A resist model is considered efficient if it is fast and accurate and properly accounts for the transfer of latent image patterns into resist shapes. Here we study the runtime-accuracy tradeoff of the Compact Model 1 (CM1) resist model. The model is represented as a linear combination of the aerial image, orthogonal basis functions, and other terms designed to mimic various effects such as acid and base diffusion, slope, maximum and minimum local intensity, etc. Clearly, the greater the number of terms involved the more flexible and accurate the model becomes. On the other hand, adding too many terms to the model substantially increases the OPC runtime and may lead to overfitting. Our goal is to find model forms that are optimal with respect to both runtime and accuracy. This is achieved using a consecutive descent method for multi-objective optimization that seeks so-called Pareto optimal solutions. We found that model forms which include the diffused acid term and orthogonal basis functions almost always represent a reasonable compromise between fitness and performance.

To avoid expensive immersion lithography and to further use existing dry tools for critical contact layer lithography at 4Xnm DRAM nodes the application of altPSM is investigated and compared to attPSM. Simulations and experiments with several test masks showed that by use of altPSM with suitable 0°/180° coloring and assist placement 30nm smaller contacts can be resolved through pitch with sufficient process windows (PW). This holds for arrays of contacts with variable lengths through short and long side pitches. A further benefit is the lower mask error enhancement factor (MEEF). Nevertheless 3D mask errors (ME) consume benefits in the PW and the assist placement and coloring of the main features (MF) put some constraints on the chip design. An altPSM compatible 4Xnm full-chip layout was realized without loss of chip area. Mask making showed very convincing results with respect to CDU, etch depth uniformity and defectiveness. The printed intra-field CD uniformity was comparable to attPSM despite the smaller target CDs. Room for improvement is identified in OPC accuracy and in automatic assist placement and sizing.

Patterning trench-hole type of structures with CD in nanometer dimension is very challenging in optical lithography due to limited depth of focus (DOF) and exposure latitude (EL). We have proposed an integration process to convert sub- 100nm line/post type of structure to trench/hole type of structure. The proposed method as well as its variations may have various potential applications, such as formation of plated perpendicular magnetic writer pole, bottom-up nanointerconnect, nano-wires and other out-of-plane nano-structures. We have shown the feasibility for formation of nanotrenches in various sub-100nm dimensions. Magnetic writer pole with 50nm critical dimensions (CD) and wellcontrolled sidewalls was demonstrated by using this approach. The minimum CD of the starting isolated line/post feature determines the minimum CD of the trench/hole structure.

The extension of optical lithography to 32nm and beyond is dependent on double-patterning (DP) at critical levels. DP integration strategies result in added degrees of freedom for overlay variation. In particular, overlay control requires assessment of error among various mask/level combinations. The Blossom overlay metrology approach minimizes the size of the overlay marks associated with each mask/level while maximizing the density of marks within the overlay metrology tool's field of view (FOV). We examine Blossom enabled use cases in DP lithography control; specifically, within-field and multiple mask/level sampling.

In modern photolithography as the feature sizes reduce, the simulation of manufacturing process calls on more and more accurate grasp of various effects in the process. While the optical simulation is calculated precisely by both firstprinciple simulators and optical proximity correction (OPC) model simulator, an accurate and computational inexpensive resist model has yet to be developed. After the exposure, resist parameters change the resist part of the proximity effects by either moving the "optical image" or responding differently to varying image qualities. By inspecting the wafer data, one can only see the results after development, which is the mixture of optical and resist effects. To isolate the effect contributed by resist, it is necessary to separate the optical component and resist component. In this paper, a novel method is proposed to determine the resist bias from the iso-focal structure, the critical dimension (CD) of which was measured under different defocus conditions. The results extracted from experiments indicate that a constant CD bias can catch most of resist effect at the first order of approximation.

The impact of bottom reflection on critical dimension (CD) processing window is intensively investigated with a simulation using a full diffraction model (FDM) in which the effective reflectivity is calculated from standing wave amplitude. Most importantly, the optical phase shift of the reflection is used as a design criterion and was found to be the primary factor that affects the UV distribution, and, hence, has a strong impact on exposure latitude and depth of focus. Foot exposure (FE) is introduced as a new metric to characterize the phase shift. Some single-layer and dual-layer bottom anti-reflective coating (BARC) designs were implemented with an Exitech MS-193i immersion micro-stepper (NA=1.3) for 45-nm dense lines at the Resist Test Center (RTC) at International SEMATECH, Albany, New York. The experimental results show that FE is closely related to the CD processing window. In contrast to conventional BARC usage, a small amount of substrate reflection with a controlled optical phase shift dramatically improves CD processing window.

In this paper, it is described in great details how we perform DOE (Design Of Experiments), simulations, narrowing the candidates down, and optimizing them to achieve low COO and large process window RET in 65 nm node nested-hole patterning. We are trying to find best condition of 65 nm tech node nested hole with dry ArF lithography process, regarding porcess cost redcution and easy access to RETs.

The industry is facing a major challenge looking forward on the technology roadmap with respect to overlay control. Immersion lithography has established itself as the POR for 45nm and for the next few nodes. As the gap closes between scanner capability and device requirements new methodologies need to be taken into consideration. Double patterning lithography is an approach that's being considered for 32 and below, but it creates very strict demands for overlay performance. The fact that a single layer device will need to be patterned using two sequential single processes creates a strong coupling between the 1st and 2nd exposure. The coupling effect during the double patterning process results in extremely tight tolerances for overlay error and scanner capabilities. The purpose of this paper is to explore a new modeling method to improve lithography performance for the 32nm node. Not necessarily unique for double patterning, but as a general approach to improve overlay performance regardless of which patterning process is implemented. We will achieve this by performing an in depth source of variance analysis of current scanner performance and project the anticipated improvements from our new modeling approach. Since the new modeling approach will involve 2nd and 3rd order corrections we will also provide and analysis that outlines current metrology capabilities and sampling optimizations to further expand the opportunities of an efficient implementation of such approach.

Self-aligned double patterning (SADP) is a patterning technique that uses CVD spacers formed adjacent to a core (template) pattern that is defined by conventional lithography. After stripping the core (template) material, the spacers serve as a hardmask with double the line density of the original lithographically defined template. This integration scheme is an alternative to conventional double patterning for extending the half-pitch resolution beyond the current lithography tool's half-pitch limit. Using a positive tone (spacer as mask) approach, we show capability to create 22nm line and space arrays, on 300mm wafers, with full wafer critical dimension uniformity (CDU) < 2nm (3 sigma) and line edge roughness (LER) < 2nm. These 22nm line and space results stem from template lithography using 1.2NA 193nm water immersion lithography. In this paper, we also demonstrate lot to lot manufacturability, the patterning of two substrate types (STI and silicon oxide trench), as well as demonstrate the formation of gridded design rule (GDR) building blocks for circuit design.

Scaling of designs to the 45nm and future nodes presents challenges for block level lithography. Shrinking distances between devices drive aggressive resist placement tolerances, challenging the ability to control critical dimension (CD). In particular, the potential variation in shallow trench isolation oxide may result in variation of resist profile and CD, thereby affecting edge placement accuracy. Potential sources of this include wafer-to-wafer or within-wafer STI trench depth variations, and STI CMP variations that may be induced by active area pattern density fluctuations. Some other potential sources of CD fluctuation include oxide sidewall variation, and implant level overlay or CD errors modulating the proximity to the oxide sidewall. Depending on the actual variation of isolation oxide and the exposure latitude of the resist, the CD variations simply from oxide variation may consume a large portion of the CD budget. Several examples are given of variations in resist profile and CD arising from these substrate effects. The CD uniformity of a test structure was shown to decrease dramatically with the addition of a BARC to the resist stack, most likely due to the suppression of substrate reflectivity variations. Simulations performed using Panoramic Technologies software demonstrated the potential sensitivity of the factors outlined above on CD and profile errors. A comparison of simulated vs. experimental results is made for a case of intentional overlay error, showing the failure mode of the resist profile as the mask edge passes from STI to the active area. The simulations using a full physical model provided with the simulation software predict a resist foot forming over the active area, which was confirmed experimentally.

The pattern deformation such as photoresist lifting after lithography due to not enough photoresist adhesion to substrate is become critical issue when aspect ratio is much higher than what photoresist adhesion can support. This aspect ratio is getting higher when our design rule of device requests smaller feature size in lithography process. The BARC (Bottom Antireflective Coating), which advanced lithography is using, is very good layer to improve adhesion of photoresist since they are same kind of chemical. However, BARC needs extra etching process before main etching which is step to remove substrate. Sometimes, this BARC etching step generated defects which makes yield loss. Especially, lithography step for metallization with aluminum likes without BARC process to be free from those defect. We think that adhesion of photoresist on metal substrate such as aluminum or TiN is very important to develop lithography process without BARC. The adhesion change between photoresist and metal substrate will be changed as function of how we apply pretreatments for metal substrate. The typical pretreatments before patterning are dry ash, wet cleaning and HMDS treatment. In this paper, we study that adhesion changes as function of pretreatments and their mechanism. To understand the interaction between photoresist and substrate, we analyze surface change of wafers which prepared with several different experimental conditions using XPS (X-ray photoelectron spectroscopy) and Dynamic Contact Angle Analyzer. The results will explain how photoresist adhesion may be changed with different pretreatment conditions and how we can optimize process condition to improve photoresist adhesion without BARC.

As feature size continuously decreasing new techniques to improve quality of wafer are developed. Hence a lot of new problems in semiconductor industry arise. Strict control of quality of wafer during production process is very important as many factors can influence on it, but the main contribution gives scanner error and mask. Thus at least impact of mask should be reduced. In this work we apply rigorous model to predict impact of microstructures to pattern fidelity on wafer. Such microstructures are commonly generated in quartz layer to control transmittance distribution on photomask. It is shown that effect from microstructures is not only changing of mask transmittance but also distortion of the pattern fidelity on wafer. Rigorous modeling gives us possibility to calculate aerial image and CD on wafer in case of presence of microstructures in the quartz. We vary optical parameters, such as refractive indexes, number, size and location of these elements in order to reduce the distortion of pattern fidelity on wafer. Our result allows prediction of the impact of microstructures in photomask on wafer pattern fidelity instead of doing set of experiments. Moreover, the best conditions for experiment are found and discussed.

With the introduction of the TWINSCAN XT:1900Gi the limit of the water based hyper-NA immersion lithography has been reached in terms of resolution. With a numerical aperture of 1.35 a single expose resolution of 36.5nm half pitch has been demonstrated. However the practical resolution limit in production will be closer to 40nm half pitch, without having to go to double patterning alike strategies. In the relentless Flash memory market the performance of the exposure tool is stretched to the limit for a competitive advantage and cost-effective product. In this paper we will present the results of an experimental study of the resolution limit of the NAND-Flash Memory Gate layer for a production-worthy process on the TWINSCAN XT:1900Gi. The entire gate layer will be qualified in terms of full wafer CD uniformity, aberration sensitivities for the different wordlines and feature-center placement errors for 38, 39, 40 and 43nm half pitch design rule. In this study we will also compare the performance of a binary intensity mask to a 6% attenuated phase shift mask and look at strategies to maximize Depth of Focus, and to desensitize the gate layer for lens aberrations and placement errors. The mask is one of the dominant contributors to the CD uniformity budget of the flash gate layer. Therefore the wafer measurements are compared to aerial image measurements of the mask using AIMSTM 45-193i to separate the mask contribution from the scanner contribution to the final imaging performance.

As the Rayleigh equations already tell us, improvements in imaging resolution often come at the price of a depth-offocus loss. Often we balance the resolution versus DoF dilemma without regard of the imaging layers location in the overall film stack. E.g. often several via or metal layers are processed with the same optical settings despite facing different amount of depth-of-focus requirements. In actuality, however, substrate induced focus variation can vary greatly from layers at the bottom of a film stack to the layers higher up in the film stack. In the age of super-low k1 lithography this variance needs to be taken into account on a layer specific basis when evaluating the resolution versus DoF tradeoff. We have studied substrate induced focus variation for a 45nm technology test-site as function of film stack sequence and spatial frequency, combining various measurement techniques into an overall topography spectrum. These techniques include data extraction from the exposure tools optical leveling sensor, a mechanical air gauge to calibrate the former and interferometric profiling tools. As a result, we can quantify our DoF requirement for a given layer and product and use this information to optimize our process design on a layer-by-layer basis. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities

According to the ITRS roadmap, low k1 imaging requires extremely tight control of Critical Dimension (CD). Maintaining the same performance from one exposure to another for new imaging requirements has become increasingly important, particularly for matching dry and wet systems. Tool to tool CD matching depends on many factors, for example, lens aberrations, partial coherence, laser spectral bandwidth and short range flare. We have performed a detailed study of laser bandwidth effects on tool CD matching for typical 65nm node structures exposed on immersion ArF scanners. A high accuracy on-board spectrometer was used to characterize the lithography Laser bandwidth, allowing measurements of both the FWHM and E95 parameters of the laser spectrum. Spectral bandwidth was adjusted over a larger range than normally experienced during wafer exposures using Cymer's Tunable Advanced Bandwidth Stabilization device (T-ABS) to provide controlled changes in bandwidth while maintaining all other laser performance parameters within specification. Measurements of both Lines and Contact Holes on 65nm node structures through all pitches were made and correlated with bandwidth to determine the sensitivity of IDB and C/H to bandwidth variation. We demonstrated that bandwidth can be adjusted for CD matching on different tool using the T-ABS function.

In this paper we performed an analysis of various data collection preformed on C045 production lots in order to assess the influence of STI oxide layers on the CD uniformity of implant photolithography layers. Our final purpose is to show whether the DOSE MAPPER^TM software option for interfiled dose correction available on ASML scanners combined with a run-to-run feed-forward regulation loop could improve global CD uniformity on C045 implants layers. After a brief presentation of the C045 implants context the results of the analysis are presented : swing curves, process windows analysis, and intra-die CD measurements are presented. The conclusion of the analysis is that it is not possible, in the current C045 industrial environment, to use a robust and general method of interfield dose correction in order to achieve a better global CD uniformity.

Use of specially designed reticle SMIF pods (RSPs) - with unique purge flow, internal dual-capture mechanism purifiers and an ultra-low humidity CDA purging system- have provided a practical solution to eliminate reticle haze for the useful life of the reticle in production environments. Prior publications, Kishkovich et al., described newly understood mechanisms of reticle haze formation based on chemical modification of quartz and chrome surfaces and have proposed solutions based on continual purge of the reticle environment with ultra-low humidity purified air [1]. In further publications they reported successful application of this solution in the field on single reticle-pod purge systems. [2] In this paper we provide guidance and advice for high volume manufacturing haze control practitioners, describing some challenges and solutions implemented on reticle stocker equipment, including considerations for materials of construction, purge flow levels and regulation, in-pod moisture/chemical purifiers, and on-tool flow measurement techniques.

The immersion fluid in the lens - wafer gap of advanced lithography scanners has the propensity to be a transport media for imaging defects. A great deal of effort has been devoted to understanding and eliminating the root causes of patterned defects in immersion lithography. Characterization of patterned and unpatterned defects on the wafer top surface has helped to drive improvements in lithography equipment, processes and materials design that subsequently enabled immersion defect density levels to be commensurate with dry lithography. This has enabled the insertion of immersion lithography into mainstream manufacturing. However, the "ever improving" yield impetus drives the need to search for and eliminate defect sources beyond the conventional top surface. This paper describes progress in extending these efforts to and beyond the wafer's edge.

Nowadays, high end photomasks are usually patterned with electron beam writers since they provide a superior resolution. However, placement accuracy is severely limited by the so-called charging effect: Each shot with the electron beam deposits charges inside the mask blank which deflect the electrons in the subsequent shots and therefore cause placement errors. In this paper, a model is proposed which allows to establish a prediction of the deflection of the beam and thus provide a method for improving pattern placement for photomasks.

With the push toward the 32nm node, OPC modeling must respond in kind with additional accuracy enhancements. One area of lithographic modeling that has basically gone unchecked is mask fidelity. Mask linearity is typically built into the OPC model since the calibration data contain this information, but mask pattern fidelity is almost impossible to quantify for OPC modeling. Mask fidelity is the rounding and smoothing of the mask features relative to the post-OPC layout intent, and there is no robust metric available to quantify these effects. With the introduction of contour-based model calibration, mask fidelity modeling is possible. This work evaluates techniques to quantify mask modeling and methods to gauge the accuracy improvement that mask fidelity modeling would project into the lithographic process using contour-based mask model calibration.

To enable development of novel signal processing circuits, a high-speed surface-channel charge coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of 1 GHz while maintaining high charge transfer efficiency (CTE). Both the CCD and CMOS gates are formed using a single-poly process, with CCD gates isolated by a narrow phase-shift-defined gap. CTE is strongly dependent on tight control of the gap critical dimension (CD). In this paper we review the tradeoffs encountered in the co-integration of the CCD and CMOS technologies. The effect of partial coherence on gap resolution and pattern fidelity is discussed. The impact of asymmetric bias due to phase error and phase shift mask (PSM) sidewall effects is presented, along with adopted mitigation strategies. Issues relating to CMOS pattern fidelity and CD control in the double patterning process are also discussed. Since some signal processing CCD structures involve two-dimensional transfer paths, many required geometries present phase compliance and trim engineering challenges. Approaches for implementing non-compliant geometries, such as T shapes, are described, and the impact of various techniques on electrical performance is discussed.

Making a sub-32 nm line and space pattern is the most important issue in semiconductor process. Specially, it is important to make line and space pattern when the device type is NAND flash memory because the unit cell is mostly composed of line and space pattern. Double patterning method is regarded as the most promising technology for sub-32 nm half-pitch node. However, double patterning method is expensive for the production and heavy data split is required. In order to make cheaper and easier patterning, we suggest a resist reflow process (RRP) method for 32 nm 1:1 line and space pattern. It is easier to make 1:3 pitch than 1:1 pitch line and space in terms of aerial image, and RRP can make 1:3 pitch aerial image to 1:1 resist image. We used home-made RRP simulation based on Navier-Stokes equation including surface tension effect. Solid-E is used for optical simulation, and e-beam lithography is used for the experiment to check the concept.

In principle, the dose should not be changed to make the same linewidth if a perfect anti-reflection coating (ARC) is used for all the sublayers underneath the resist. However, the optimum dose for different sublayers and thicknesses are different even though perfect ARC is used. The post exposure bake (PEB) process of a chemically amplified resist is one of the key processes to make very small features of semiconductor device. The photo-generated acid makes the deprotection of protected polymer, and this deprotection highly depends on the PEB temperature and time. The diffusion length of acid is also strongly dependent on PEB temperature and time. As the linewidth of the device decreases, smaller diffusion length is required to reduce the roughness of the line edge and width. One of the key factors to determine the deprotection and acid diffusion is the initial temperature rising and the final real temperature inside the resist. The unpredictable temperature rising to the pre-set temperature mainly causes the variation of linewidth and the optimum dose. In order to predict the accurate PEB temperature and time dependency of the linewidth and dose, the heat transfer from the hot plate to the resist on the top of the multiply stacked sublayers over the silicon wafer has to be known since the reaction and diffusion occur inside the resist, not on the top of the bare silicon wafer. We studied heat transfer from the hot plate to the top of the resist including conductivity and thickness of each sublayer. For this purpose, a novel numerical approach incorporated with analytic method was proposed to solve the heat conduction problem. The unknowns for temperature are located only at the interfaces between layers, so that it is fast and efficient. We calculated the time that is consumed for the resist to attain the prescribed PEB temperature for the different multi stacks and thicknesses. Calculation shows that the temperature rising is different and final temperature on top of the resist is also different for various sublayers and thicknesses of theirs including resist itself. Experiment by us and others also clearly show that there is a definite temperature difference between on top of the bare wafer and on top of the resist. The effects for the different layer stacks and thicknesses are investigated to obtain proper dose and linewidth control due to different actual resist PEB temperature.

New concepts about transistor structure are being introduced for sub-50nm memory products. As the memory cell design is shrinking down, conventional transistor of planar structure can not guarantee safe transistor operation. Newly introduced transistor has to ensure robust transistor operation characteristics and process stability simultaneously. One of the candidates which are being developed recently is vertical transistor. The basic layout to integrate vertical transistor include very dense 2-dimensional features. The new memory cell based on dense structure can also contribute to reduction of cell area compared to conventional memory cell such as 8F2 planar cell. While new memory structure enables the reduction of chip size, its 2-dimensional structure limits resolving performance of optical lithography inevitably. It is very challenging to build 4F2 dense features of sub-50nm node by single exposure technology using hyper NA ArF lithography before the EUV era. In this paper, the feasibility of 2-dimensional dense structure at 50nm node is presented and various techniques are introduced to realize new memory scheme as next generation memory cell structure.

As the industry extends immersion lithography to the 32 nm node, the limits of image and resist contrast will be challenged. Image contrast is limited by the inherent numerical aperture of a water based immersion lithography system. Elements of resist design and processing can further degrade the final deprotected image contrast^1,2. Studies have been done to understand the effects of image contrast on line width roughness (LER) for dry 193 nm lithography³. This paper focuses on the impacts of image and resist contrast on the formation of defects and LER in an immersion lithography process. Optical and resist simulations are combined with experiments to better understand the relationship between image quality, resist design, scanner/track processing and defect formation. The goal of this work is to develop a relationship between resist contrast metrics and defect formation for immersion processes.

This paper describes the qualification work performed on a state-of-the-art immersion cluster and shows results for an immersion process for the 45nm node. These results demonstrate full compliance with all lithographic parameters, including CD control and defectivity. Qualification was performed on an RF^3iTM wafer track from Sokudo Co., Ltd. and a 1.2NA immersion scanner. A three-layer material stack was engineered using 820Å BARC / 1800Å ArF photoresist covered by 900Å immersion top-coat. After verification of tool and process cleanliness and testing the robustness of the material stack for use in the immersion scanner, resulting photo cell monitor (PCM) defect density on a 65nm memory device was evaluated. Critical dimension was verified using both CD-SEM and optical CD metrology. Results on a 45nm L/S pattern showed 0.55nm WIW 3sigma CD uniformity using optical CD metrology. Lot to lot CD control was tested for being below 1.5nm 3sigma. As special Soak-units were used prior to post exposure bake (PEB), the influence of post exposure delay (PED) on the CD performance was studied and quantified. All immersion-related modules were optimized and qualified on both 65nm products and 45nm prototypes. Additionally, comparison data for immersion and dry lithography will be presented.

The traditional Hopkins based microlithography aerial image simulation methods most likely require expensive 4D Singular Value Decomposition operations to obtain mutually incoherent kernels. This is often a problem when the requirement of resolution is high especially when sub-resolution assist features are present. During the process development and model fitting, kernels are required to generate frequently. In this paper, we demonstrate that it is not necessary to perform this expensive task to generate those kernels. By taking advantage of several classical matrix theories, we are able to directly extract kernels without resorting to 4D Singular Value Decomposition operations. The accuracy and efficiency will be extensively studied in the experimental results.

Coupled eigenmode (CEM) theory for TM polarized illumination is presented and applied to the 3D modeling of a linespace reticle. In this approach, the electric and magnetic field inside a line-space reticle is described in terms of an orthogonal set of eigenmodes of Maxwell's equations. The diffraction of light by the reticle can then be expressed as a coherent sum of diffraction orders produced by each eigenmode independently. Fresnel transmission, overlap of eigenmodes with diffraction orders and propagation through the mask are shown to be the interactions that determine the complex amplitude of the diffraction orders produced by each mode. We further shown that only a small number of eigenmodes are needed to accurately calculate image contrast under TM polarized illumination.

Rigorous computer simulations of propagating electromagnetic fields have become an important tool for optical metrology and design of nanostructured optical components. A vectorial finite element method (FEM) is a good choice for an accurate modeling of complicated geometrical features. However, from a numerical point of view solving the arising system of linear equations is very demanding even for medium sized 3D domains. In numerics, a domain decomposition method is a commonly used strategy to overcome this problem. Within this approach the overall computational domain is split up into smaller domains and interface conditions are used to assure continuity of the electromagnetic field. Unfortunately, standard implementations of the domain decomposition method as developed for electrostatic problems are not appropriate for wave propagation problems. In an earlier paper we therefore proposed a domain decomposition method adapted to electromagnetic field wave propagation problems. In this paper we apply this method to 3D mask simulation.

In the case of hyper-NA (NA>1) imaging with the lens magnification keeping 1/4, the angle of light incidence on pellicle becomes bigger. For example, it is up to 19 degrees for NA=1.3 lens. It is already known that the effect of multiple reflections of the light inside the pellicle film becomes obvious, in that the effect contains transmission variation across the light incidence angle on the pellicle. For normal pellicle, transmission of oblique incidence light is lower than the normal incidence light and the difference is about 10% as intensity changes. And pellicle thickness error affects the transmission characteristics. Thus, pellicle thickness error causes change of iso-dense bias (or optical proximity effect; OPE) and dense line CD variation. Specs for CD uniformity in below half pitch (hp) 45nm imaging become tighter, and therefore, pellicle should not be a new root cause of CD error. The solutions for the issue are (1) tighter specs for pellicle thickness or (2) selection of optimal pellicle thickness. The latter is more effective for suppressing CD variation across the exposure field than the former. In our paper, we describe the pellicle effect for through-pitch imaging including below hp45 nm dense L/S using hyper-NA lens. We discuss pellicle thickness optimization for better CD uniformity and the results of simulation for some pellicle conditions.

The introduction of double patterning and double exposure technologies, especially in combination with hyper NA, increases the importance of wafer topography phenomena. Rigorous electromagnetic field (EMF) simulations of two beam interference exposures over non-planar wafers are used to explore the impact of the hardmask material and pattern on resulting linewidths and swing curves after the second lithography step. Moreover, the impact of the optical material contrast between the frozen and unfrozen resist in a pattern freezing process and the effect of a reversible contrast enhancement layer on the superposition of two subsequent lithographic exposures are simulated. The described simulation approaches can be used for the optimization of wafer stack configurations for double patterning and to identify appropriate optical material properties for alternative double patterning and double exposure techniques.

In this paper, we demonstrate how a direct coupling of a lithography simulation program and a semiconductor device simulation tool can be used to investigate the impact of lithographic process variations on nano-scaled CMOS devices. In contrast to conventional evaluation criteria such as process windows, mask error enhancement factor (MEEF), or CD (critical dimension) uniformity, the lithography process is regarded in a more holistic fashion as a means to an end. As a consequence, the ultimate figure of merit is determined by the performance of the device. Lithography simulations are conducted using a rigorous EMF solver for the computation of the mask nearfield. TCAD process and device simulations are performed for an ultra thinned body fully depleted silicon on insulator (UTB FD-SOI) nMOSFET, with a physical gate length of 32 nm. Electrical parameters such as on- and off- current, threshold voltage, sub-threshold slope, gate-capacitance, and contact resistances are computed and extracted. The impact of lithographic process variations on the electrical behavior of the target device is surveyed and illustrated. Moreover, we present an adjusted lithography process window defined by the electrical behavior of the device. In addition to a discussion of the obtained results, this paper also focuses on the software design aspects of interfacing a lithography simulation environment with a device simulator. The steps involved in extracting parameters and transferring them from one program to the other are explained, and further automation capabilities are suggested. Moreover, it is illustrated how this approach can be extended towards an integrated litho/device process optimization procedure.