This PDF file contains the front matter associated with SPIE Proceedings Volume 6520, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and the Conference Committee listing.

Microlithography patterning employs one of three media; electron, ion, and photon. They are in a way like horses, racing towards the mainstream. Some horses such as electrons run fast but repel each other. Ion beams behave like electron beams but are less developed. The photon beam is the undisputed workhorse, taking microlithography from the 5-&mgr;m minimum feature size to 32-nm half pitch. This paper examines the history of microlithography in pattern generation, proximity printing, and projection printing, then identifies the strong and weak points of each technology. In addition to ion-beam and e-beam lithography, the coverage of optical lithography spans the wavelength from 436 to 13.5 nm. Our learning from history helps us prevent mistakes in the future. In almost all cases, making or using the mask presents one of the limiting problems, no matter the type of beams or the replication method. Only the maskless method relieves us from mask-related problems. A way to overcome the low throughput handicap of maskless systems is to use multiple e-beam direct writing, whose imaging lens can be economically and compactly fabricated using MEMS techniques. In a way, the history of microlithography parallels that of aviation. Proximity printing is like the Wright-Brothers’ plane; 1X projection printing, single-engine propeller plane with unitized body; reduction step-and-repeat projection printing, multi-engine commercial airliner; scanners, jet airliners. Optical lithography has improved in many ways than just increasing NA and reducing wavelength just as the commercial airliners improving in many other areas than just the speed. The SST increased the speed of airliners by more than a factor of two just as optical resolution doubled with double exposures. EUV lithography with the wavelength reduced by an order of magnitude is similar to the space shuttle increasing its speed to more than 10 times that of the SST. Multiple-beam direct write systems are like helicopters. They do not need airports(masks) but we need a lot of beams to carry the same payload.

The development of CMOS technology has been, and will remain, driven by system needs. Traditionally, these needs have been met quite satisfactorily by simply reducing the physical size of the transistors as guided by the MOSFET scaling theory and increasing the chip-level integration density as anticipated from "Moore’s Law." Now that CMOS has reached its scaling limits, continued progress has to come from innovations beyond the traditional development paths, guided by anticipating and addressing system designers' concerns and needs. In this talk, we examine several opportunities for extending current CMOS technology to continue satisfying the needs of system designers.

Optical lithography has been the dominant patterning process for semiconductor fabrication for over 40 years. The patterning process evolved initially from methods used in the printing industry, but as integrated circuits became more complex, and as device geometries shrank, sophisticated new imaging methods evolved. Today’s optical lithography systems represent the highest resolution, most accurate optical imaging systems ever produced. This remarkable evolutionary process continues to this day, paced by "Moore's Law". The evolutionary development of lithography systems over the last 40 years is reviewed along with a brief discussion of options for the future.

This paper discusses the current performance and the evolution of five generations TWINSCAN immersion scanning exposure tools. It is shown that production worthy overlay and focus performance can be achieved at high scan speeds. The more critical part for immersion tools is related to defects, but also here improvements resulted in production worthy defect levels. In order to keep the defect level stable special measures are needed in the application of wafers. Especially Edge Bead Removal (EBR) design and wafer bevel cleanliness are important.

High index immersion lithography (HIL) is one candidate for the next generation lithography technology following water immersion lithography. This technology may require only moderate changes of chip making processes and result in lower cost of ownership (CoO) compared with other technologies such as double processing, extreme ultra violet lithography (EUVL), and nano-imprinting, and other technologies. In this paper, the current status of high index lens material and immersion fluid development compared with our requirements is discussed considering microlithographic lens design feasibility and attainable NA.

Semiconductor manufacturers work hard to shrink critical dimensions in their device architectures and are in the midst of the 45nm node development. Generally, for the 65nm node, critical layers are processed using 193-nm scanners with numerical apertures up to 0.85 and non-immersion technology. It is clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) need to be examined, especially as the industry turns its attention towards the 45-nm technology generation. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. In this paper, we report on the progress of development for the 45nm device level lithography with imaging systems >1NA at the Crolles 2 Alliance. Our continued focus is the insertion of an immersion lithography process into an established pilot manufacturing line to support 45nm process development. We will present immersion resist performance, OPC feasibility, process integration, and defectivity comparisons. Finally, conclusions will be made as to the overall readiness of immersion to support 45nm node processing.

Immersion lithography was applied to 45nm node logic and 0.25um² ultra-high density SRAM. The predictable enhancement of focus margin and resolution were obtained for all levels which were exposed by immersion tool. In particular, the immersion lithography enabled to apply the attenuating phase shift mask to the gate level. The enough lithography margin for the alternating phase shift mask was also obtained by using not only immersion tool but also dry tool for gate level. The immersion lithography shrunk the minimum hole pitch from 160nm to 140nm. Thus, the design rule for 45nm node became available by using immersion lithography.

In this paper we demonstrate the many benefits of using immersion lithography that go beyond depth of focus (DOF) improvement by comparing several key features of dry and immersion lithography. Immersion lithography improves critical dimension uniformity (CDU) as well as avoiding the necessity for strong resolution enhancement techniques (RET) as compared with dry lithography. Thus it is possible to significantly reduce the burden of optical proximity correction (OPC) work with immersion lithography. With respect to imaging, we studied the sensitivity of the lithographic performances to aberrations and light source spectral bandwidth E95 fluctuations to highlight the benefits of immersion lithography. The significant improvements that have been seen in the last year in overlay accuracy, defect control and focus & leveling accuracy have been considered to be challenges to the realization of immersion lithography in mass production. Now these challenges have been met for the manufacturing requirements of 55 nm logic devices. The achievements of immersion lithography include overlay accuracy within 10 nm on resist-to-resist wafers and within 20 nm on production wafers, fewer than 10 defects per wafer, and errors of less than 40 nm in focus & leveling on full wafers. We have established a top-coat resist process. In conclusion, immersion lithography is the most promising manufacturing solution for 55 nm node logic devices, providing advantages in CDU control, and equivalent overlay performance and focus & leveling accuracy to dry ArF, without an increased level of defects. NEC Electronics has completed development and preproduction of the 55 nm logic device "UX7LS" using immersion lithography and has established the lithography technology for mass production of the UX7LS this year.

As immersion lithography is extended to ever increasing resolution, the resulting propagation angles in the materials involved become closer to grazing than to normal incidence. Classical laws of refraction and reflection cannot be used with either assumption however, as a collection of angles may exist across the entire range. Fresnel reflection at these angles becomes large enough that small disparities in refractive indices at material interfaces may lead to adverse effects. As an example, when water is used at numerical apertures approaching its refractive index, reflection effects are greater than the constraints imposed by refraction or absorption. This will limit the maximum NA value allowed by any given material to values sufficiently lower than its refractive index. Additionally, we have grown accustom to expanding the application of the Snell-Descartes Law to materials with low absorption, assuming that the contribution of the imaginary component of the refractive index is negligible. This is not the case for photoresists, fluids, or glasses, which can not strictly be considered as non-absorbing media. We have expanded the Snell-Descartes Law for absorbing media, with some interesting consequences. We will show that there is no real limit on the numerical aperture into a material, so long as its extinction coefficient is not zero. The relationship that lithographers have been using recently where NA< min[n_glass, n_fluid, n_resist] will be shown to be inadequate and imaging at numerical apertures up to 1.85 will be demonstrated using materials with significantly lower (real) refractive index values.

In this paper, we will present experimental results on 45nm node patterning of DRAM and some technical issues for polarized illumination in hyper NA imaging. First, practical k1 limit of 1.2NA ArF immersion system is investigated through experiment. Process window and mask error enhancement factors are measured with respect to various design rules, i.e., different k1 levels at fixed NA. Reasonable process window and MEEF value of around 3 are achieved in DRAM gate and isolation layers at around 0.28 k1 regime. It is obvious that feasibility of this lowered k1 was realized by the help of polarized illumination when we compared the results with that of 60nm patterning at 0.93NA tool - corresponding k1 is 0.29 - without polarized illumination. Then consideration about degree of polarization state must come next to the benefit of polarized illumination. Input polarization state is changed by birefringence of lens or mask materials but it is very difficult to correlate the birefringence level and critical dimension of patterns experimentally. Double exposing method was contrived to measure the effect of degree of polarization on DICD. And we also measure the polarization dependent transmittance of light on mask by using 1.2NA immersion scanner. As a result, birefringence and mask feature interaction with light seems not to be a serious issue for 45nm hyper NA polarized imaging.

The introduction of polarized illumination has enabled the extension of low-k1 processes well below a k1-factor of 0.3. Previously, it has been demonstrated by simulations and early exposure results that properly polarized illumination leads to an increase of contrast and exposure latitude, resulting in reduced MEEF and better CD control. The gain of polarization is most pronounced in the hyper-NA regime of high-end immersion tools (NA > 1.0), but also 'dry' high- NA scanners (NA = 0.93) benefit significantly from polarized illumination. For volume production, polarized illumination must be fully compatible with all requirements for a lithographic step and scan system: full throughput, overlay and focus control, flexibility and ease-of-use are essential features. This is realized by employing polarization-conserving optics, and by automated in-line metrology to optimize and control the system for any selected polarization state. In this paper, experimental results will be shown demonstrating the gain of using polarized illumination on high- and hyper-NA exposure tools, of both dry and immersion types. The various imaging relevant parameters (MEEF, EL, DOF, LWR) will be addressed in relation to the use of polarization exposure conditions. The effect of polarization control on imaging performance will be presented in relation to CD control at low k1. Finally, the viability to extend the k1-value to 0.28 for a bi-directional process and 0.27 for a uni-directional process when using polarized illumination will be demonstrated.

We present a comprehensive modeling study of polarization effects for the whole optical chain including exposure tool and mask, with strong emphasis on the impact of the Jones Matrix of the projection lens. First we start with the basic of polarization and then the polarization effect of each components of the optical chain will be discussed. Components investigated are source polarization, rigorous EMF effect, mask blank birefringence, pellicle effect and projection lens. We also focus on comparing the relative merits of different types of representation of Jones matrix of the projection lens and outlined ways to decompose the Jones Matrix. Methodologies such as Pauli matrix, PQM, Jones-Zernike expansion and IPS-Zernike expansion are among the ones investigated. The polarization impact on lithography and OPC on realistic 45nm and 32nm node process levels is discussed. Issues in OPC modeling with Jones Matrix is highlighted. Concerns regarding the standardization of the implementation of Jones Matrix in the lithography community are considered and a standard has been proposed and received wide acceptance. Last we discuss the challenge of using polarization and some novel ideas to deal with polarization in hyper NA era. Throughout the paper the resist component is not included so as to isolate the effect of resist from that of the other components.

To meet the imaging resolution requirements, driven by the evolution of IC design rules, leading-edge scanners incorporate projection lenses with hyper-NAs. Moreover, immersion scanners are being introduced into IC manufacture. Both dry and immersion tools explore the lens design regimes of unprecedented complexity. The need to predict, to analyze and to control the IC pattern CDs is met by various photolithography simulators. The continuing demand for simulation accuracy is reflected by the requirement to quantify the scanner projection lens fingerprints, i.e. projection lens infinitesimal excursions from the ideal performance. The scanner engineering community has been relying on photolithography simulators to analyze the impact of the projection lens fingerprints on the imaging characteristics. However small, these excursions are always present in the projection tools and they control important imaging characteristics such as overlay, CD uniformity, across-field exposure latitude, to name but a few. Customarily, phase front aberrations and lens pupil apodization signatures have been used to predict the scanners imaging responses. Of course, the need to design, to manufacture and to deploy scanners of ever improving quality resulted in dramatic reductions of these non-ideal imaging excursions. The evolution of IC designs and imaging tools complexity escalate the requirements for imaging simulation accuracy. Simultaneously, predicting scanner imaging response has become a key mission in the Deign For Manufacture arena. In view of these developments, it necessary to pose a question if the conventional equipment engineering and imaging simulation methodologies predict scanner imaging responses with the accuracy required by the IC design rules. Differently put, the question is: what is necessary to provide simulation accuracy required by the current IC design rules? This report attempts to address these questions.

The continuous implementation of novel technological advances in optical lithography is pushing the technology to ever smaller feature sizes. For instance, it is now well recognized that the 45nm node will be executed using state-of-the-art ArF (193nm) hyper-NA immersion-lithography. Nevertheless, a substantial effort will be necessary to make imaging enhancement techniques like hyper-NA immersion technology, polarized illumination or sophisticated illumination modes routinely available for production environments. In order to support these trends, more stringent demands need to be placed on the lithographic optics. Although this holds for both the illumination unit and the projection lens, this paper will focus on the latter module. Today, projection lens aberrations are well controlled and their lithographic impact is understood. With the advent of imaging enhancement techniques such as hyper-NA immersion lithography and the implementation of polarized illumination, a clear description and control of the state of polarization throughout the complete optical system is required. Before polarization was used to enhance imaging, the imaging properties at each field position of the lens could be fully characterized by 2 pupil maps: a phase map and a transmission map. For polarized imaging, these two maps are replaced by a 2x2 complex Jones matrix for each point in the pupil. Although such a pupil of Jones matrices (short: Jones pupil) allows for a full and accurate description of the physical imaging, it seems to lack transparency towards direct visualization and lithographic imaging relevance. In this paper we will present a comprehensive method to decompose the Jones pupils into quantities that represent a clear physical interpretation and we will study the relevance of these quantities for the imaging properties of lithography lenses.

We present results from investigating critical challenges of pitch doubling through Double Patterning to meet manufacturing requirements for 32nm ¹/₂ pitch on 1.2NA lithography system. Simulations of lithography alternatives identified manufacturable Dose-Focus latitudes for a dual-line positive process option which led to an experimental setup based on a single hardmask process. Key challenges of the selected process relate to the presence or absence of the hardmask layer during 1^st or 2^nd patterning step. This has an effect on wafer topography, process setup, etch bias and wafer litho-to-etch CDU offsets, which will create two final CDU populations. Therefore, there are two metrology challenges, separation between the two CD populations and overlay-at-resolution using CDSEM. They were addressed by designing appropriate CD and overlay targets and by implementing an adequate dense sampling allowing modeling of wafer and field CD distributions. We introduced a new CDU model to calculate double patterning budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns within 2*Pitch distance. For a single line and 1.35NA system, the model predicted 3.1nm variance with mask CDU and etch bias being the major contributors. We achieved an experimental resolution of 32-nm ¹/₂ pitch on 1.2NA system, which equals 0.20k1. Experimental results at 32-nm resolution were confirmed in a pre-manufacturing environment on a full lot of 24 wafers, with raw CDU of 6nm (3s). After modeling and correcting for interfield (wafer) and intrafield spatial distributions, CDU was improved to 2.5nm (3s). Best overlay results equaled scanner SMO capability of ~7nm (mean+3s).

Double patterning lithography has been one of the candidates for sub-40nm patterning era, and has a lot of process issues to be confirmed. Last year, we presented the issues in double patterning lithography with a real flash gate pattern. Process flow was suggested and CD uniformity due to overlay was analyzed. And the layout decomposition and the two types of double patterning of positive and negative tone were studied with 1-dimensional pattern. In this paper, the implementation to DRAM patterns is examined, which consist of 2-dimensional patterns. Double patterning methods and the selection of their tone for each layer are studied, and the difficulties from the randomness of core pattern are also considered. As a result, DRAM patterns have more restrictions on the double patterning method and selection of tone, and the aggressive layout decomposition should be designed to solve the difficulty in core patterning. Therefore, 37nm DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles.

A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-litho-etch approach on metal hard mask (MHM). Since an 0.85NA immersion scanner is used, the small pitch of 100nm is obtained by DP, the small trenches are made by a Quasar exposure followed by a shrink technique. The RELACS^® process is used, realizing narrow trenches with larger DOF and less LER. For mask making, a design split is carried out, followed by adjustments of the basic design to make the patterns more litho-friendly. Assist features are placed next to isolated trenches to ensure sufficient DOF. Furthermore, an adjusted OPC calculation is carried out, taking into account proximity effects of both the exposure and the subsequent shrink process. After mask fabrication, this DP process is used for a single damascene application, with BDIIx as low-k material and TaN or TiN as MHM. Various problems are encountered, such as CD gain of the trenches during both MHM etch steps, poisoning and BARC thickness variations due to topography during the second litho step. For all these problems, solutions or work-arounds have been found, After the second MHM-etch, the 50nm half-pitch pattern is transferred successfully in the underlying low-k material.

Double patterning (DP) appears to be the most probable patterning technology for initial 32 nm node manufacturing. This work explores how it may be accurately simulated. In the first instance, the process is approximated using two planar exposures in a commercial lithographic simulation package. This work is then followed up by more accurate calculations using a prototype simulator (based of Rigorous Coupled Wave Analysis propagation techniques) which allows the topography generated from the first exposure pass to influence the light propagation in the second exposure. The accuracy of the prototype simulator is demonstrated by validating its' output against the vector model in PROLITH V10, for the planar topography case. Results from the RCWA simulations show that for an example poly gate double patterning process, the presence of the topography enhances the process window of the second exposure, in terms of both exposure and focus latitude. The topography simulator is also used to study the robustness of the second exposure process window to fluctuations in the CD printed during the first exposure pass and of the influence of misalignment between the two passes.

The back-end-of-line metallization of a state-of-the-art CMOS process is the most critical level regarding the final density of the chip. While the gate level requires the most emphasis on linewidth control and critical dimension uniformity (CDU) of all lithography steps, the smallest pitch in the process is typically printed on the first metallization level. For this reason, a natural starting point for application of dipole lithography is not the gate level, which in many cases can be printed with quadrupole and other off-axis schemes with good process latitude, but the metal level with pitches that are typically between 10 and 25% smaller than the gate pitch. If the same generation exposure tool is used for both gate and metallization levels, then a more aggressive off-axis illumination is needed for the metal level. In this paper, we investigate the application of double dipole lithography on the first metallization level (M1). We propose a simple bias to account for EMF effects compared to the thin mask approximation which is used in optical proximity correction. We discuss resist and BARC processes that are required at this pitch, and describe process windows. Using a 1.2 NA lithography system, we investigate the performance of this lithography technique at a pitch of 100 nm.

Scatterometry techniques are used to characterize the CD uniformity, focus and dose control, as well as the image contrast of a hyper-NA immersion lithography scanner. Results indicate very good scanner control and stability of these parameters, as well as good precision and sensitivity of the metrology techniques.

We derive a physical model to describe the dependence of pattern dimensions on dose, defocus and blur. The coefficients of our model are constants of a given lithographic process. Model inversion applied to dimensional measurements then determines effective dose, defocus and blur for wafers patterned with the same process. In practice, our approach entails the measurement of proximate grating targets of differing dose and focus sensitivity. In our embodiment, the measured attribute of one target is exclusively sensitive to dose, whereas the measured attributes of a second target are distinctly sensitive to defocus and blur. On step-and-scan exposure tools, z-blur is varied in a controlled manner by adjusting the across slit tilt of the image plane. The effects of z-blur and x,y-blur are shown to be equivalent. Furthermore, the exposure slit width is shown to determine the tilt response of the grating attributes. Thus, the response of the measured attributes can be characterized by a conventional focus-exposure matrix (FEM), over which the exposure tool settings are intentionally changed. The model coefficients are determined by a fit to the measured FEM response. The model then fully defines the response for wafers processed under "fixed" dose, focus and blur conditions. Model inversion applied to measurements from the same targets on all such wafers enables the simultaneous determination of effective dose and focus/tilt (DaFT) at each measurement site.

An important outcome of the 90nm and 65nm device generations was the realization that new methods for predicting and controlling patterning were required to ensure successful transfer for all design rule compliant features through the required process window. This realization led to a strong increase in the use of CD-based and process window aware post-optical proximity correction (OPC) verification in production mask tapeouts. Accurate post-OPC verification is a necessity but many patterning issues could have been detected and removed earlier in the product development lifecycle. Of course, the 45nm and 32nm device generations are only expected to further strain the ability of device manufacturers to predict process control requirements, robust patterning design rules and first-time right reticle enhancement technology (RET) recipes. Therefore, improvements to the traditional process, OPC and design rule prediction/evaluation steps are needed. In this paper we propose a patterning and CD control prediction methodology which incorporates not only the traditional dose, defocus and mask variation parameters but also implements RET parameter variations such as layout edge discretization, model inaccuracy, metrology error and assist feature placement. This methodology allows a more accurate prediction of process control requirements, worst case CD control layout geometries and RET subsystem accuracy/control requirements. Lithography engineers have long operated with specific (if not always fully understood) dose and focus control success requirements. To efficiently determine real worst design situations, we utilize a new methodology for quickly verifying the RET-ability of a lithography process + design rule set + OPC correction recipe based on coupling iterative layout generation with OPC testing. Our aim in this paper is to provide additional engineering rigor to the traditional experience-based OPC success requirements by looking at the total Litho + RET + metrology patterning problem and analyzing the individual component control needs.

Deviations from paraxial image models are significant at numerical apertures (NA) planned to support immersion lithography. Apodization and rotation of polarization by high numerical optics are well-characterized phenomena. Similar behaviors follow from intrinsic properties of photomask patterns at high spatial frequencies. Diffraction efficiencies differ from values predicted using Kirchhoff boundary conditions, and depend on polarization. Pellicles also apodize diffraction patterns because reflection losses depend on angle of incidence and polarization. These effects are large enough to influence contrast, critical dimension and depth of focus of images thru pitch. These vectorial effects may degrade image quality, or invalidate models for optical proximity correction (OPC) that do not properly comprehend them. What matters for the image is the cumulative contribution of mask pattern, pellicle and optics. The objective in this study is to provide a systematic and unified mapping the optical landscape of mask patterned film and pellicle membrane materials as well as their impacts to vectorial imaging performance. We conclude that to optimize image performance, it is essential to balance the diffraction beam's angle, phase and amplitude. And there are non-unique reticle (mask scatter and pellicle membrane) material solutions to enable high (NA) immersion lithography.

We provide an expanded description of the global algorithm for mask optimization introduced in our earlier papers, and discuss auxiliary optimizations that can be carried out in the problem constraints and film stack. Mask optimization tends inherently to be a problem with non-convex quadratic constraints, but for small problems we can mitigate this difficulty by exploiting specialized knowledge that applies in the lithography context. If exposure latitude is approximated as maximization of edge slope between image regions whose intensities must print with opposite polarity, we show that the solution space can be approximately divided into regions that contain at most one local minimum. Though the survey of parameter space to identify these regions requires an exhaustive grid search, this search can be accelerated using heuristics, and is not the rate-limiting step at SRAM scale or below. We recover a degree of generality by using a less simplified objective function when we actually assess the local minima. The quasi-binary specialization of lithographic targets is further exploited by searching only in the subspace formed by the dominant joint eigenvectors for dark region intensity and bright region intensity, typically reducing problem dimensionality to less than half that of the full set of frequency-domain variables (i.e. collected diffraction orders). Contrast in this subspace across the bright/dark edge will approximately reflect exposure latitude when we apply the standard fixed edge-placement constraints of lithography. However, during an exploratory stage of optimization we can define preliminary tolerances which more explicitly reflect constraints on devices, e.g. as is done with compactor codes for design migration. Our algorithm can handle vector imaging in a general way, but for the special case of unpolarized illumination and a lens having radial symmetry (but arbitrary source shape) we show that the bilinear function which describes vector interference within the film stack can be expressed in terms of three generic radial functions, enabling rapid numerical evaluation of the Hopkins kernel. By inspection these functions show that one can in principle recover classical scalar-like imaging even at high NA by exposing a very thin layer spaced above a reflective substack. The reflected image largely restores destructive interference in TM polarized fringes, if proper phasing is achieved. With an ideal reflector, the first-order azimuthal contrast loss term vanishes in all TCC components, and complete equivalence to scalar imaging is obtained in classical two-beam imaging.

As device geometries shrink, tolerances for critical dimension, focus, and overlay control decrease. For the stable manufacture of semiconductor devices at (and beyond) the 65nm node, both performance variability and drift in exposure tools are no longer negligible factors. With EES (Equipment Engineering System) as a guidepost, hopes of improving productivity of semiconductor manufacturing are growing. We are developing a system, EESP (Equipment Engineering Support Program), based on the concept of EES. The EESP system collects and stores large volumes of detailed data generated from Canon lithographic equipment while product is being manufactured. It uses that data to monitor both equipment characteristics and process characteristics, which cannot be examined without this system. The goal of EESP is to maximize equipment capabilities, by feeding the result back to APC/FDC and the equipment maintenance list. This was a collaborative study of the system's effectiveness at the device maker's factories. We analyzed the performance variability of exposure tools by using focus residual data. We also attempted to optimize tool performance using the analyzed results. The EESP system can make the optimum performance of exposure tools available to the device maker.

A new framework has been developed to model 3D thick mask effects for full-chip OPC and verifications. In addition to electromagnetic (EM) scattering effects, the new model also takes into account the non-Hopkins oblique incidence effects commonly found in real lithography systems but missing in prior arts. Evaluations against rigorous simulations and experimental data showed the new model provides improved accuracy, compared to both the thin-mask model and the thick-mask model based on Hopkins treatment of oblique incidence.

Pushing optical microlithography towards the 32nm node requires hyper-NA immersion optics in combination with advanced illumination, polarization, and mask technologies. Novel approaches in model-based optical proximity correction (OPC) and sub-resolution assist feature (SRAF) optimization are required to not only produce correct feature shapes at the nominal process condition but also to maintain edge placement tolerances within spec limits under process variations in order to ensure a finite process window. In addition, it is becoming increasingly important to consider interactions between multiple layers when performing correction in order to ensure electrical viability. In this paper we discuss the application of a model based process-window-aware and interlayer-aware integrated OPC system on 32nm node patterns. Process window awareness will be demonstrated for main feature correction by taking into account image-based modeling at multiple defocus and dose conditions. In addition, interlayer-awareness will be demonstrated by correction that takes into account the effects of active width on gate CD and of contact overlap with metal, gate, and active. The results show an improvement over "non-aware" OPC in gate CD control, in contact overlap, and in overall process margin. In addition, PW aware correction is demonstrated to prevent potential catastrophic failures at extreme PW conditions.

Boundary Layer Model (BLM) is applied to OPC for typical memory-device patterning processes for 3D mask topographic effect. It is observed that this BLM successfully accounts for the 3D mask effect as reducing OPC model error down to sub-50 nm node. BLM improves OPC-modeling accuracy depending on specific process conditions such as mask type and pattern geometry. Potential limit of BLM, i.e., how accurately BLM could predict the 3D mask effect is also investigated with respect to CD change: BLM also compared with rigorous simulation for various features and a good match is obtained as small as below 0.5 nm. Some practical issue in OPC modeling such as determination of the phase of boundary layer is addressed, which can be critical for prediction of defocus behavior.

Optical proximity correction (OPC) and phase shifting mask (PSM) are resolution enhancement techniques (RET) used extensively in the semiconductor industry to improve the resolution and pattern fidelity of optical lithography. In this paper, we develop generalized gradient-based RET optimization methods to solve for the inverse lithography problem, where the search space is not constrained to a finite phase tessellation but where arbitrary search trajectories in the complex space are allowed. Subsequent mask quantization leads to efficient design of PSMs having an arbitrary number of discrete phases. In order to influence the solution patterns to have more desirable manufacturability properties, a wavelet regularization framework is introduced offering more localized flexibility than total-variation regularization methods traditionally employed in inverse problems. The proposed algorithms provide highly effective four-phase PSMs capable of generating mask patterns with arbitrary Manhattan geometries. Furthermore, a double-exposure optimization method for general inverse lithography is developed where each exposure uses an optimized two-phase mask.

A method has been developed for mapping and analyzing the impact of each local region of the illumination distribution (i.e. "illumination source point"). The method makes directly visible the imaging impact/result for each one of those local regions. In this way, the entire available illumination region can then be broken down generally into regions of "good light" and "bad light" for each pattern under consideration. It is possible to then further subdivide the impact of each source point/local region into 'categories of impact' that can be each then independently evaluated (e.g. contrast/intensity modulation, Normalized Image Log Slope, CD range through a fixed focus region, CD change due to a given dose change, aberration sensitivity, etc.). By applying the method and analyzing the full superset of all available source points for all mask patterns being considered, the optimization of the illumination distribution becomes a straightforward matter of finding the best combination of source points to deliver whatever is described as the target of the optimization. An example of the application of the method will be provided and discussed, with highlights on key learning steps arising from this case study that might be applicable more generally. By becoming familiar with the contributions of the various regions within the potential illumination region, one can begin to see both: i. those regions which contribute only less than optimally to the imaging of any of the specified critical patterns, and: ii. those regions which show positive contribution to the imaging (via analysis of NILS or CD/Focus, etc.) Various methods to extract, analyze, and apply these results and knowledge, and turn them into a prescription for an optimized illuminator source design will be discussed.

LER (line edge roughness) is becoming increasingly critical for manufacturers and efforts to understand and control it have given disappointing results. We propose that LER is due to a combination of coherent optical effects, mask LER, and chemical processes during exposure, PEB (post exposure bake) and development. Different sources of LER have similar scaling laws and PSD (Power spectral density) distribution, and the causes of LER are easily misidentified. High sensitivity, thin resist, and low image log-slope generally give more LER. No single-effect model is going to be adequate to give quantitative predictive guidance how to reduce LER. Since LER is shared between chemistry, optics and metrology, a cross-disciplinary model is needed. We propose such an LER budget model with a unified analysis of the metrology and consequences of LER, but with models for source effects plugged in by experts from the relevant domains.

Polarized illumination is a viable technique for improving the image quality and process latitude of hyper-NA lithography. On investigation of polarization effects, it is often assumed that the lens system can maintain the polarization state through optical path, which may not be the case with actual lenses. These polarization changes may cause CD variations and pattern placement errors. In this paper, we investigated a method of polarization analysis across the pupil and showed some examples of polarization aberrations. Also, we analyzed CD sensitivity and pattern placement errors from polarization aberrations. Specific terms of the Pauli Zernike representation have effects on CD and pattern placement errors, like the Zernike representation of conventional aberrations. The Pauli-Zernike representation is intuitive and useful for understanding and specifying polarization aberrations.

With decreasing critical dimension (CD) budgets and smaller k1 values the need for perfect focus control becomes paramount. Among the individual contributors to the overall focus budget, the accuracy of the leveling system on a process wafer and the focus setting accuracy for the individual layers are two major contributors. In our study we discuss the usage of a new non-optical leveling system and its measurement capability of wafer topography. By exposing focus-exposure matrices (FEMs) and measuring them on multiple points in the field, we demonstrate the systematic and random focus variation across the scanner exposure field for several layers. Critical back end of line (BEoL) layers in particular show considerable impact of topography, thus resulting in the across field focus variations shown. By using the newly developed AGILE leveling system which uses an air-gauge focus sensor we demonstrate a more accurate best focus determination across field, resulting in better overall focus performance. This AGILE system is expected to be independent on any process variation, since there is no (optical) interaction between the measurement device and the process layer stack. By the use of multi-point FEMs we show that the intrafield focus range can be reduced by as much as 50%, depending on certain layer and layout characteristics. We discuss the impact of the new sensor in conjunction with the extended FEM scheme on the overall focus budget for critical layers. Finally, we briefly show a possible integration scenario into the overall exposure strategy.

Here we present both simulation and experimental results that show the effect of changes in laser light source bandwidth (E95) on CD Iso-Dense Bias. For the 55nm Technology Node Device, we have shown that E95 stability of less than 0.11pm is required in order to maintain OPE variation to within 2nm. In addition, we also verified another method to adjust for OPE variations that occur when E95 fluctuates. The Contrast Adjustment method is an effective function to adjust for OPE variation due to E95 fluctuation; it has been shown to maintain OPE variation less than 1.5nm. Furthermore, for the 45nm Technology Node Device, we have demonstrated that E95 stability of less than 0.07pm is required to maintain OPE variation to within 1nm. The bandwidth performance of the latest laser light source exhibits E95 stability less than 0.03 pm, thereby showing that the OPE variation due to E95 can be kept to under 1nm.

193-nm immersion lithography is the only choice for the 45-nm logical node at 120-nm half pitch and extendable to 32- and 22-nm nodes. The defect problem is one of the critical issues in immersion technology. In this paper, we provided a methodology to trace the defect source from optical microscope images to its SEM counterparts after exposure. An optimized exposure routing was also proposed to reduce printing defects. The average defect count was reduced from 19.7 to 4.8 ea/wafer.

The imaging of an immersion lithography system has different sensitivities to optical errors such as reticle non-flatness, image plane deviation and laser bandwidth when compared to traditional dry imaging systems. The immersion sensitivities mentioned above are further amplified when higher fluid index is used. The resultant effect of these enhanced sensitivities leads to degraded focal plane flatness centering on wafers and may also lead to larger ACLV and machine to machine CD matching errors than expected. In this paper, we demonstrate the increased sensitivity factors both mathematically and experimentally. We perform a detailed error component analysis to single out an immersion related factor and its impact to CD control. For this purpose we independently quantify the reticle non-flatness directly on the mask. We also identify possible compensation solutions, such as reticle shape correction, improved focal plane setup methodology and the incorporation of focus blur into an OPC model, in order to alleviate an adverse effect of immersion on ACLV and CD stability over time and over different tool sets.

Water-based immersion technology has overcome various obstacles and is approaching the mass production phase. Canon is in the process of developing an ArF immersion exposure tool, FPA-7000AS7 (NA>1.3), to meet both mass production of the 65nm HP and development of the 45nm HP, which starts in 2007. In the Canon immersion nozzle, there is little influence of vibration on the lens and the stage, and particle generation from the nozzle during treatment of the nozzle in the manufacturing process has successfully been prevented. We evaluated contamination due to leaching and cleaning technology with a test bench. Contamination due to PAG (Photo-acid Generator) leaching from resist to water could be completely eliminated by dipping it into a cleaning fluid. With periodic cleaning, it is possible to keep the projection lens clean and to prevent particle generation from the immersion nozzle. The defect was evaluated with FPA-6000AS4i (NA0.85) that had the same type of immersion nozzle as that of FPA-7000AS7. The level of defect density was stable in a continuous exposure process of 25 wafers with a developer-soluble topcoat. The defect density was 0.030/cm2 with a topcoat-less resist.

C045 node (65nm half pitch) technology processes are driving the development of immersion lithography techniques and infrastructures and C032 node (45nm half pitch) is following in its tracks. As semiconductor development enters the arena of low leakage, high-performance devices using immersion lithography, the 45nm hp technology adds more pressure of decreasing pitches and feature sizes using the most cost effective method available. The Crolles2 Alliance is in the first phases of the push for very low k1 193nm lithography for our technology development. Many resolution enhancement techniques are being explored to fill the low k1 realm; including implementation of these techniques and more aggressive integrations to support the device parameters. However, the early development of 45nm hp node along with the need for better focus and dose control algorithms, imaging of pitches to allow for the packing density will present significant challenges to photolithography even when considering super hyper-NA immersion lithography. Reflectivity variations, thin film interference through the complex film stacks, and increased sensitivity to feature size is posing a challenge for maintaining good and consistent features. This paper discusses an analysis and early results covering the beginning development of 45nm hp with >1NA immersion lithography. Specifically, parameters such as illumination and enhancement techniques, processing capability, application of OPC at a very low k1, process integration, mask effects, and defectivity as discussed.

ArF immersion lithography has become accepted as the critical layer patterning solution for lithography going forward. Volume production of 55 nm devices using immersion lithography has begun. One of the key issues for the success of volume production immersion lithography is the control of immersion defectivity. Because the defectivity is influenced by the exposure tool, track, materials, and the wafer environment, a broad range of analysis and optimization is needed to minimize defect levels. Defect tests were performed using a dedicated immersion cluster consisting of a volume production immersion exposure tool, Nikon NSR-S609B, having NA of 1.07, and a resist coater-developer, TEL LITHIUS i+. Miniaturization of feature size by immersion lithography requires higher sensitivity defect inspection. In this paper, first we demonstrate the high sensitivity defect measurement using a next generation wafer inspection system, KLA-Tencor 2800 and Surfscan SP2, on both patterned and non-patterned wafers. Long-term defect stability is very important from the viewpoint of device mass production. Secondly, we present long-term defectivity data using a topcoat-less process. For tool and process qualification, a simple monitor method is required. Simple, non-pattern immersion scanned wafer measurement has been proposed elsewhere, but the correlation between such a non-pattern defect and pattern defect must be confirmed. In this paper, using a topcoat process, the correlation between topcoat defects and pattern defects is analyzed using the defect source analysis (DSA) method. In case of accidental tool contamination, a cleaning process should be established. Liquid cleaning is suitable because it can be easily introduced through the immersion nozzle. An in-situ tool cleaning method is introduced. A broad range of optimization of tools, materials, and processes provide convincing evidence that immersion lithography is ready for volume production chip manufacturing.

An important step in today's Integrated Circuit (IC) manufacturing is optical proximity correction (OPC). While OPC increases the fidelity of pattern transfer to the wafer, it also significantly increases IC layout file size. This has the undesirable side effect of increasing storage, processing, and I.O. times for subsequent steps of mask preparation. To alleviate the growing volume of layout data, a new layout data format, Open Artwork System Interchange Standard (OASIS), was introduced in 2001 by SEMI's Data Path Task Force. Even though OASIS results in a more efficient representation than the previous industry standard format GDSII, there is still room for improvement by applying data compression techniques. In this paper, we propose two such techniques for compressing layout data, including OPC layout, while remaining complaint with existing industry standard formats such as OASIS and GDSII. Such compliance ensures that the resulting compressed files can be viewed, edited, and manipulated by industry standard CAD viewing and editing tools without the need for a decoder. Our approach is to eliminate redundancies in the representation of the geometrical data by finding repeating groups of geometries between multiple cells and within a cell. We refer to the former as "inter-cell sub-cell detection (InterSCD)" and latter as "intra-cell sub-cell detection (IntraSCD)". We show both problems to be NP hard, and propose two sets of heuristics to solve them. For OPC layout data, we also propose a fast compression method based on IntraSCD which utilizes the hierarchical information in the pre-OPC layout data. We show that the IntraSCD approach can also be effective in reconstructing hierarchy from flattened layout data. We demonstrate the results of our proposed algorithms on actual IC layouts for 90nm, 130nm, and 180nm feature size circuit designs.

The last six years have seen the increasing advance of computational and algorithmic complexity to compute mask patterns that retain sufficient lithographic fidelity to print and yield well enough to maintain the advances in circuit density that are the engine of the semiconductor economy. New Computational Lithography techniques such as Optical Proximity Correction (OPC), Scattering Bars (SB), Phase Shift Masks (PSM), and Lithography Verification (LV) constitute a significant transformation of the design. Initially applied only to the most critical portions of the most critical layers such as gate poly and active, they are now considered de-rigueur for almost every layer through and including the topmost metal layers. These new Computational Lithography applications have become one of the most computationally demanding steps in the design process. Compute farms of hundreds and even thousands of CPUs are now routinely used to run these applications. This paper will examine the evolution of these techniques and the computing systems to run them. A variant of Amdahl's law and an example COO equation to compute cost of ownership for the hardware platforms are developed. The practical aspects of the infrastructure needed to support such extensive compute farms including power, support, and cooling will be examined. Newly emerging High Performance Computing (HPC) techniques that hold the promise of checking this unbridled growth in computational requirements will be reviewed and contrasted including multi-core processors, Field Programmable Gate Arrays (FPGAs), The Cell Broadband Engine (CBE), Digital Signal Processors (DSPs), and Graphics Processing Units (GPUs) will be considered.

Lithography models for leading-edge OPC and design verification must be calibrated with empirical data, and this data is traditionally collected as a one-dimensional quantification of the features acquired by a CD-SEM. Two-dimensional proximity features such as line-end, bar-to-bar, or bar-to-line are only partially characterized because of the difficulty in transferring the complete information of a SEM image into the OPC model building process. A new method of two-dimensional measurement uses the contouring of large numbers of SEM images acquired within the context of a design based metrology system to drive improvement in the quality of the final calibrated model. Hitachi High-Technologies has continued to develop "full automated EPE measurement and contouring function" based on design layout and detected edges of SEM image. This function can measure edge placement error everywhere in a SEM image and pass the result as a design layout (GDSII) into Mentor Graphics model calibration flow. Classification of the critical design elements using tagging scripts is used to weight the critical contours in the evaluation of model fitness. During process of placement of the detected SEM edges of into the coordinate system of the design, coordinate errors inevitably are introduced because of pattern matching errors. Also, line edge roughness in 2D features introduces noise that is large compared to the model building accuracy requirements of advanced technology nodes. This required the development of contour averaging algorithms. Contours from multiple SEM images are acquired of a feature and averaged before passing into the model calibration. This function has been incorporated into the prototype Calibre Workbench model calibration flow. Based on these methods, experimental data is presented detailing the model accuracy of a 45nm immersion lithography process using traditional 1D calibration only, and a hybrid model calibration using SEM image contours and 1D measurement results. Error sources in the contouring are assessed and reported on including systematic and random variation in the contouring results.

Hyper numerical aperture (NA) implemented in immersion exposure system makes the semiconductor business enable to enter sub-45nm node optical lithography. Optical proximity correction(OPC) utilizing SRAF has been an essential technique to control critical dimension (CD) and to enhance across pitch performance in sub-wavelength lithography. Mask lithography, however, is getting more challenging with respect to patterning and processing sub-resolution assist features (SRAFs): the higher aspect ratio of mask structure, the more vulnerable. Mask manufacturing environment for DRAM and Flash becomes harsher mainly due to mask patterning problem especially pattern linearity, which causes pattern broken, inspection issue, and finally CD issue on wafer. When a pattern in relatively isolated pitches has small or large assist features, the assist features may bring unexpected CD or print on wafer. A frequency-preserving assist bar solution is the most preferred one, but it is difficult to realize for opaque assist features due to printability. In this paper, we propose a new type assist feature dubbed "Phase-shifted Assist Bar" to improve process window and to solve the resolution constraint of mask at sub-45nm manufacturing process node. The concept of phase-shift assist bar is applying phase-shift to SRAF realized with trench structure on general mask, such as Binary and Attenuated Phase-Shifted Mask (Att.PSM). The characteristics of phase-shift assist bar are evaluated with rigorous 3D lithography simulation and analyzed through verification mask, which is containing hugely various size and placement of main and assist feature. The analysis of verification mask has been done with aerial image verification tool. This work focuses on the performance of phase-shift assist bar as a promising OPC technique for "immersion era" in terms of resolution enhancement technique, optical proximity correction, and patterning on mask.

The authors will explore the possible contact hole lithography solutions for the future technology nodes, from 90 nm down to 32 nm half-pitch (HP) in this paper. The special emphasis will be on the logic application because of the lack of a strong resolution enhancement technique (RET) for the random hole layouts. The use of illumination optimization, focus drilling can extend the projection optical lithography down to near 60 nm HP. The adoption of pitch split double exposure technique is needed to provide a robust manufacturing process window to further extend to around 50 nm HP. To further shrinking the design rule, a double patterning is need after the pitch split. The pitch split double patterning technique reaches its limit around 40 - 45 nm HP. The desire to not limit the integrated circuit (IC) design requires the lithography process k1 to be as high as possible. The random logic contact hole application is well suited for EUV lithography for 35 nm HP and below because of the high k1 process and a potential for high productivity of a mask based lithography. The pattern density of contact hole masks would not require a stringent mask defect requirement, and moreover, the EUV's relatively higher system flare does not have a significant impact on imaging. Actual EUV data and calibrated simulations will be used to demonstrate that EUV can provide a robust process window.

Double patterning technique using spacer which can avoid CD (Critical Dimension) uniformity problem mainly caused by overlay issue is one of the methods that could be applied to apply to manufacturing of memory devices. Though double exposure and etch technology (DEET) has comparative advantage in the number of process steps, it is required to dramatically improve overlay performance of current exposure tools for the realization of manufacturing. In this study, negative type-double pattering technique using spacer has been developed as the best way for the application of NAND flash memory device from the view point of CD uniformity and the number of mask layers used to complete double patterning. Negative type-double patterning technique using spacer consists of subsequent steps such as formation of poly line, spacer on sidewall of poly line, SOG gap fill into space between poly lines, SOG etch back, removal of spacer, and finally hard mask etch. We have used amorphous carbon as a spacer material to easily remove spacer from poly lines and adopted SOG material to easily fill in space between poly lines. When negative type-double patterning technique using spacer is applied to NAND flash memory device, we can expect that k1 factor of about 0.14~0.20 could be accomplished successfully.

Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from: -Static RAM with very aggressive design rules specially at active, poly and contact -transistor variability control at the chip level -random layouts The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm : -dipole with polarization and regular layout for active level -dipole with polarization, regular layout and double patterning to cut the line-end for poly level. These choices have been made based on the printing performances of a 0.17&mgr;m² SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.

It was shown previously that the Double Line and Space (L&S) Formation Method (DLFM) is superior to other methods for forming a dense contact hole (C/H) resist pattern by simulation and 0.30 k₁ 1:1 C/H resist pattern was formed experimentally. In this paper, a through process of C/H formation from resist patterning to metal filling is presented. The square C/Hs transferred to an oxide film from the resist pattern formed by the DLFM could be filled with metal, although the transferred C/Hs had square corners in comparison with the conventional C/H resist patterning. On the other hand, the combination of the DLFM and the 'Pack and Cover Process' makes it possible to form resist random C/Hs on grids. So, the possibility of forming random C/Hs filled with metal is shown. Moreover, the resolution limit of the DLFM is discussed. 0.29 k₁ (half pitch 65 nm) and 0.27 k₁ (half pitch 56 nm) 1:1 C/H resist pattern could be formed with optimized dipole illumination. So, random C/Hs with k₁ below 0.30 are expected to be formed.

It is challenging to develop 45nm node contact hole using dry ArF lithography process with acceptable lithographic margin due to small process window and large mask error enhancement factor (MEEF). No single process using conventional lithography without resolution enhancement technique (RET) application will meet DOF requirement of 45nm node contact hole. We have developed dry ArF lithography processes for 45nm node contact hole on scanner ASML XT1400E by applying RETs including off-axis illumination, SAFIER (Shrink Assist Film for Enhanced Resolution) process, EFESE (focus scan), etc. The paper will discuss process window through pitches with optimized illumination, and where to separate pitches in case of double exposure with consideration of DOF and OPC model simulation. It will look into the effect of EFESE on DOF improvement, proximity, and MEEF at various pitches. The paper will also discuss OPC modeling strategy for 45nm node contact/via hole. It will analyze the effect of OPC grid size on OPC run time, file size, and edge placement error (EPE). To extend process further to 32nm node, we demonstrated the process capability for 32nm node hole using double patterning technique. We achieved 50nm final hole CD with pitch of 100nm. A hard mask (HM) technique was implemented in the process. The dense feature is designed into two complementary parts on two masks such that the density is reduced by half and minimum pitch is increased by at least a factor of 2^1/2 depending on design. The complete patters are formed with two litho-etch process steps. After the first mask litho process, the HM is etched. Then the second mask litho process is carried out and followed by a second HM etch and main etch.

Hyper-NA lithography with polarized light illumination is introduced as the solution of 45nm or 32nm node technology. In that case, consideration of new characteristics of mask materials and pellicle films has been required. In order to analyze the influence of mask material's optical characteristics, we have proposed to use the AIMS^TM system measuring diffraction intensity balance in previous work. That was enabled by acquiring pupil plane images using the Bertrand lens in the AIMS^TM system to measure selected area's diffracted light. In this study of mask material evaluation, we used same functionality of AIMS^TM system, MonoPole illumination and Bertrand lens, as previous work but other direction's pole is also used on the illumination aperture to cover total diffraction orders of Cross-quad illumination because this illumination is more flexible for x and y patterns. In order to get diffracted light of 45nm half-pitch, hyper-NA e.g. NA=1.35 was applied and the AIMS^TM 45-193i Alpha system was used for this evaluation. The examinations were performed with binary and half tone PSM with half pitch 40 to 150nm on a 1x scale and fixed half pitch 45nm with various mask bias. We confirmed the relation between diffractions' intensity balance and wafer printing performance for each material and we compared them to 3D simulation results. Moreover, by using the same functionality of AIMS^TM system, the transmission change by pellicle film was also examined. We have prepared two different thickness pellicles to compare transmission change and printed CD on the wafer. Intensity profile at pupil plane on the clear region of the mask was acquired with Bertrand lens and conventional large sigma setting for both with and without pellicle film on the mask. By comparing transmission distribution change between with and without pellicle, we could calculate transmission loss by pellicle at large incident angles. For this experiment, NA=1.40 was applied and the AIMS^TM 45-193i Alpha system was also used. The examinations were performed with half tone PSM at half pitch 45nm and 65nm on a 1x scale on linear polarized DiPole illumination. As a result, we have confirmed good agreement between AIMS^TM measurement data and optical 3D simulations. In conclusion, the AIMS^TMsystem is a valuable tool for analyzing diffraction efficiency or intensity distribution on the pupil plane and comparison to wafer printing performance.

Rigorous electromagnetic field (EMF) simulations of light diffraction from the mask in combination with vector imaging simulation are used to explore the impact of the optical mask parameters on the diffraction and imaging performance. Optical mask parameters and mask stack configurations are varied over a wide range and independently from the presently used materials. The results are evaluated in terms of diffraction efficiencies and typical lithographic performance criteria such as iso-dense bias, mask error enhancement factor (MEEF), sidelobe-printability, and (overlapping) process windows. Both local and global optimization techniques are used to identify optimum parameter settings. The results are compared with the performance of standard mask stacks and parameters.

In the exposure using ArF immersion exposure tool, under the conditions in which the mask pattern pitch is smaller than several times the exposure wavelength, diffraction light distribution cannot be predicted correctly by the Kirchhoff approximation mask model, and therefore, rigorous electromagnetic field analysis, or 3D mask model, is required. In particular, in the dense line and space (L/S) formation using oblique illumination and an attenuated phase shifting mask (att-PSM), the intensity of 0th and 1st diffraction lights changes as pitch shrinks. In dense L/S formation, it is necessary to reduce a mask error enhancement factor (MEF) and to obtain sufficient exposure latitude. We consider the following three contrast control "knobs" (CCKs): (1) Mask bias, (2) Transmittance of attenuating mask material (absorber), (3) Thickness of absorber. We also considered the effect of illumination angle of incidence on 3D mask. We performed a simple optimization for exposure latitude of dense L/S pattern, reflecting consideration of the mask 3D model for half pitch (hp) 45nm L&S imaging using att-PSM and oblique illumination. The important image characteristics are normalized image log slope (NILS) and dose- MEF for obtaining sufficient exposure latitude. We carried out an experiment of attenuated PSM exposure using hyper-NA exposure tools and compared the results with the 3D mask simulation. The degree of agreement between the experiment and the 3D mask simulation, and the practical effectiveness of the CCKs are discussed in this paper.

Unpolarized light has traditionally been used for photolithography. However, polarized light can improve contrast and exposure latitudes at high numerical aperture (NA), especially for immersion lithography with an NA > 1.0. As polarized light passes through a reticle, any birefringence (BR) in the reticle material can cause a change in the orientation or degree of polarization, reducing the contrast in the final resist image. This paper shows the effects of reticle BR on dry and immersion imaging for 193nm lithography. The BR magnitude and orientation of the fast axis were mapped across several unpatterned mask blanks, covering a range of BR from 0 to 10 nm/cm. These reticles were printed with a series of open areas surrounded by test structures. The BR was measured again on the patterned reticles, and several locations were selected to cover a range of magnitudes at different orientations of the fast axis. Dry and immersion imaging were evaluated, looking at BR effects on dense lines and contact structures. Mask error enhancement factor (MEEF), line edge roughness (LER), and dose and focus latitudes were studied on line/space patterns. Dose and focus latitudes and 2-D effects were studied on contact patterns. Based upon these results, the effect of reticle BR on CD is minimal, even for BR values up to 10 nm/cm.

The lithography prognosticator of the early 1980's declared the end of optics for sub-0.5&mgr;m imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k₁. Several author have recently discussed manufacturing imaging solutions for sub-0.3k₁ and the integration challenges. Our industry will continue to focus on the most cost effective solution. What continues to motivate lithographers to discover new and innovative lithography solutions? The answer is cost. Recent publications have demonstrated sub 0.30 k₁ imaging. The development of new tooling, masks and even photoresist platforms impacts cost. The switch from KrF to ArF imaging materials has a significant impact on process integration. This paper will focus on the usefulness of beyond water immersion for 22nm logic node. Data will be presented demonstrating the impact of higher refractive index photoresist systems have on the further extension of ArF Immersion.

In this paper we report the status of our feasibility work on high index immersion. The development of high index fluids (n>1.64) and high index glass materials (n>1.9) is reported. Questions answered are related to the design of a high NA optics immersion system for fluid containment and fluid handling, and to the compatibility of the fluid with ArF resist processes. Optical design and manufacturing challenges are related to the use of high index glass materials such as crystalline LuAG or ceramic Spinel. Progress on the material development will be reviewed. Progress on immersion fluids development has been sustained. Second-generation fluids are available from many suppliers. For the practical use of second-generation fluids in immersion scanners, we have evaluated and tested fluid recycling concepts in combination with ArF radiation of the fluids. Results on the stability of the fluid and the fluid glass interface will be reported. Fluid containment with immersion hood structures under the lens has been evaluated and tested for several scan speeds and various fluids. Experimental results on scan speed limitations will be presented. The application part of the feasibility study includes the imaging of 29nm L/S structures on a 2-beam interference printer, fluid/resist interaction testing with pre- and post-soak testing. Immersion defect testing using a fluid misting setup was also carried out. Results of these application-related experiments will be presented and discussed.

To identify the most practical and cost-effective technology after water immersion lithography (Gen1) for sub-45 nm half pitches, the semiconductor industry continues to debate the relative merits of water double patterning (feasible, but high cost of ownership), EUV (difficulties with timing and infrastructure issues) and high index immersion lithography (single-exposure optical lithography, needing a suitable high index last lens element [HILLE]). With good progress on the HILLE, high index immersion with numerical apertures of 1.55 or above now seems possible. We continue our work on delivering a commercially-viable high index immersion fluid (Gen2). We have optimized several fluids to meet the required refractive index and absorbance specifications at 193 nm. We are also continuing to examine other property/process requirements relevant to commercial use, such as fluid radiation durability, last lens element contamination and cleaning, resist interactions and profile effects, and particle contamination and prevention. These studies show that both fluid handling issues, as well as active fluid recycling, must be well understood and carefully managed to maintain optimum fluid properties. Low-absorbing third generation immersion fluids, with refractive indices above 1.7 (Gen3), would further expand the resolution of singleexposure 193 nm lithography to below 32 nm half pitch.

BaLiF₃ single crystal has been studied as the lens material for the candidate of the next generation high index immersion lithography system. Although the refractive index of BaLiF₃ is 1.64 at 193nm which is not sufficient for the requirement, other optical properties such as 193nm transparency and laser durability might fulfill the requirement, and intrinsic birefringence is relatively lower than other candidate materials. It is estimated that the cause of scattering in the BaLiF₃ crystal is aggregation of excess LiF component. The special annealing process to eliminate excess LiF component was applied to improve the transparency. The internal transparency was improved to more than 97%/cm by optimizing growth conditions and annealing conditions.

ArF water immersion exposure systems with a numerical aperture (NA) of over 1.3 are currently being developed and are expected to be used for the node up to 45-nm half-pitch. Although there are multiple candidates for the next generation node, we here focus on ArF immersion lithography using high-index materials. The refractive index of highindex fluids is typically about 1.64 and is larger than that of fused silica (~1.56). In this situation, the NA is limited by the refractive index of silica and is at most 1.45. An exposure system with 1.45 NA is not suitable for 32-nm hp node, but may be used for 37-nm hp node. In spite of this limitation, the system has the advantage of slight alterations from the current system using water as immersion fluid. On the other hand, high-index lens material is effective to increase the NA of projection optics further. At present, LuAG, whose refractive index is 2.14, is most promising as high-index lens material. The combination of high-index fluid and high-index lens material can enhance the NA up to about 1.55 and the exposure system would be available for the 32-nm half-pitch node. Although high-index immersion lithography is attractive since it is effective in raising resolution, such new materials should be examined if these materials can be used for high precision projection optics. Here, we have investigated optical characteristics of high-index materials in order to realize high-index immersion systems.

As the design rule shrinks to its natural limit, reduction in lithography process margin and high Critical Dimension (CD) error gives rise to use of many Resolution Enhancement Techniques (RET). Recently, one the popular RET method to solve the above problem is polarized illumination. It is used to enhance the reduced lithography process margin and enhance CD uniformity. Polarization lithography basically uses one sided polarized light source. Therefore process margin increases for smaller design rule patterns. In this paper, we will present the results for polarized illumination based Optical proximity Correction (OPC) for sub-60nm memory device. First, models for polarization based and un-polarization based method will be compared for its model accuracy. Second, the process margin improvement for polarized and un-polarized illumination will be compared and analyzed for poly layer of sub-60nm memory device. Finally, method for further enhancing CD error within 5% for polarized OPC model will be discussed.

As alternative approaches (i.e. EUV) to pattern smaller device geometries are being explored but none has showed maturity for large volume production, 193nm ArF lithography continues to be the workhorse for semiconductor manufacturing industry. The extension of 193nm lithography heavily depends on the application of Resolution Enhancement Technologies, driving k1 factor closer to the theoretical limit of 0.25. One effective way to drive k1 lower is the combination of dipole illumination with embedded phase-shifting mask (EPSM). However, one of the disadvantages of dipole illumination is the presence of forbidden pitches due to that the illumination conditions are only optimized for the critical pitches. One obvious solution to address this issue is the double exposure strategy. With the critical pitches are patterned using dipole illumination, the looser pitches are addressed by a less aggressive illumination condition. One concern of this double exposure strategy is that the geometries from the first exposure and the geometries from the second exposure need be seamlessly stitched together for certain device designs. This paper discusses the OPC optimization for image stitching. Three stitch OPC schemes are studied to stitch two resist space features together. The results show that the reticle registration tolerance for image stitching depends on how the stitch OPC is done. The registration error tolerance is maximal when the OPC is performed on the low resolution image.

The current ITRS roadmap details the growing complexity of device design and the latest device-manufacturer's techniques for tuning their process for each new design generation. In spite of the current desire to incorporate techniques termed "Design for Manufacture" (DFM) into the sequence, simulations and the design cycle do little more than optimize feature quality for ideal exposure conditions while testing for shorts, opens and overlay problems over process variations. Testing in the DFM simulation is performed by the adaptation of a technique unchanged in the last 30 years, the Process Window analysis. With this, mediocre successes seen in chip-design have not taken their share of the burden of technology advancement. Consequently, process adaptation to each new design has fallen to increasingly complex setup procedures of the exposure toolsets that customize scanner performance for each new device. Design optimization by simulation focuses on feature layout optimization for resolution. Design solutions that take advantage of the full potential spectrum of mask-feature alternatives to increase functional process-space and simplify setup in manufacturing do not exist since there is no method of feedback. A mechanism is needed that can quantify design performance robustness, with mask-contributions, to variations in the user's specific manufacturing process. In this study, a Process Behavior Model methodology is presented for the analysis of feature profiles and films to derive the relative robustness of response to process variations for alternative OPC designs. Analysis is performed without regard to the specific mechanics of the design itself. The design alternatives of each OPC feature are shown to be strong contributors not only to resolution and depth-of-focus but also to the stability of final image response; that is the ability of the feature profile to remain at optimum under varying conditions of process exposure excursion. Several different, 70 nm multi-pitch OPC designs are compared for their response stability to fluctuations of the process. The optimal process corrections on the reticle are shown to be dependent upon not only the final image size at some optimal exposure point but also on the ability of the design to maintain feature size within tolerance across an increasingly large process-space of the target production process. The failure of the classic Process Window analysis to anticipate or provide corrective insight for performance improvement under these conditions is illustrated. Models are presented that allow the extraction of the nonlinear but systematic interactions of several OPC designs with the normal fluctuations experienced across the process exposure space plus those introduced by the toolset and filmstack variation. A method of extracting the systematic component of each feature's design-iteration is derived providing the ability to quantify the specific OPC response sensitivity to changes in the exposure and process films as well as drift introduced by the tools of the exposure set.

Double exposure lithography processes can offer a significant yield enhancement for challenging circuit designs. Many decomposition techniques (i.e. the process of dividing the layout design into first and second exposures) are possible, but the focus of this paper is on the use of a secondary "cut" mask to trim away extraneous features left from the first exposure. This approach has the advantage that each exposure only needs to support a subset of critical features (e.g. dense lines with the first exposure, isolated spaces with the second one). The extraneous features ("printing assist features" or PrAFs) are designed to support the process window of critical features much like the role of the sub-resolution assist features (SRAFs) in conventional processes. However, the printing nature of PrAFs leads to many more design options, and hence a greater process exploration space, than are available for SRAFs. A decomposition scheme using PrAFs was developed for a gate level process. A critical driver of the work was to deliver improved across-chip linewidth variation (ACLV) performance versus an optimized single-exposure process. A variety of PrAF techniques were investigated, including block type features, variable-pitch PrAFs, and constant assist-to-feature spacing (similar to SRAF placement). A PrAF scheme similar to standard SRAF rules was chosen as the optimal solution. The resulting ACLV benefits occurred mainly in the intermediate pitch range. For dense pitches, the ACLV was mostly unchanged, since in that regime neither process used assist features. The PrAF process showed a benefit of 10-44% improvement of ACLV in the mid-range pitches, but up to 18% worse ACLV for isolated pitches. Thus, the optimal double exposure solution was a combination of SRAFs and PrAFs that achieved the ACLV benefits of both.

All models currently used for Optical Proximity Correction and related Resolution Enhancement techniques are comprised of an analytical description of the modeled system with coefficients determined by data collected from the physical process. The analytical model is normally based on the Hopkin's approximation of the system because this approximation allows the reticle to be a variable in the exposure system. The analytical component of the model contains terms such as numerical aperture, partial coherence, and wavelength, all of which are physical parameters that can be directly read from the equipment used to generate the empirical process data. Therefore, these physical parameters can be directly used in the process model and do not need to be modified. One case example of a physical parameter is the illuminator shape. In an annular exposure system, the center of the exposure system is blocked to allow illumination by high order illumination components. The annular shape can be achieved in different manners. The scanner manufacturer can use a shape cut in a metal form to achieve an annular illumination condition or the scanner manufacturer can use a lens system to achieve the same illumination condition. Both of these systems have the same inner and outer diameters, resulting in the same annulus and therefore the same illumination technique. However, experimental data show that for the exact same setting values, the annular illumination shape is detectably different. This is a first order system difference that is the result of different implementation methods. Further differences can be found due to scanner to scanner variations in either lens shape or aperture shape. These differences create a need for physical parameters to be regressed during fitting of empirical data to the analytical model. This paper will discuss the need to regress what initially appear to be constant physical parameters during the model fitting process. The study will use equipment variability information to demonstrate the range of physical constant impact upon the accuracy of a process model.

Nikon released the world's first hyper-NA immersion scanner, the NSR-S609B with NA 1.07 at the beginning of 2006. With the highest NA lens using all-refractive optics, a flexible illumination system, and POLANO^TM polarized illumination, the NSR-S609B is capable of manufacturing devices with better than 55 nm resolution. In addition, Nikon has announced the release of the NSR-S610C. With the world's highest NA lens (NA=1.30), the S610C can comfortably achieve 45 nm critical layer volume production with k1=0.30. Nikon's proprietary catadipotric lens design for the S610C provides the lowest flare and eliminates lens heating, resulting in stable imaging. Because the S609B and the S610C are built on the same platform, a number of advantages can be realized. First, both the S609B and the S610C utilize a tandem stage optimized for immersion lithography. The tandem stage consists of separate exposure and calibration stages. This allows for continuous flow of immersion water, and for calibration of the exposure tool during wafer exchange. As a result, throughput of greater than 130 wph is achieved, evaporative cooling of the stage during wafer exchange is prevented, and focus drift, baseline changes, and other issues with tool stability are eliminated. In this way, the tandem stage can achieve productivity and accuracy at the same time. In addition to the calibration functions described above, the Integrated Projection Optics Tester (iPot) mounted on the calibration stage can manage the long term performance of the projection optics. By measuring the wavefront aberration, the polarization quality of POLANO^TM, and the pupil fill, iPot supports the optimization of the imaging performance. Nikon's polarized illumination system POLANO^TM provides improved contrast with no loss of illumination power. This provides increased process margin for 45 nm volume production using immersion lithography. Finally, Nikon's proprietary local fill nozzle installed on the S609B and the S610C has been shown to eliminate immersion defects from bubbles, watermarks, and particles. Various data showing that the NSR-S609B meets requirements for 55nm and below production and the status of the development of Nikon's newest immersion scanner NSR-S610C are introduced here.

Canon has renewed its platform of exposure tools. The new platform, the FPA-7000, is designed to cover multiple generations. The lens performance of the FPA-7000AS5 achieves less than 6m&lgr;, while that of the AS7 is estimated to be less than 4m&lgr;. The illumination performance meets the target required for the 45nm node. The in-situ aberration monitor, called iPMI, attains the measurement repeatability of 1.45m&lgr;. Focus and overlay units have improved process robustness. A solution tool for optimization is introduced to be connected with the FPA-7000. Moreover, latest studies of immersion, such as nozzle pressure, temperature control and defect inspection result are reported, and we also discuss the possibility of high-refractive-index immersion.

Water based immersion lithography is now widely recognized a key enabler for continued device shrinks beyond the limits of classical dry lithography. Since 2004, ASML has shipped multiple TWINSCAN immersion systems to IC manufacturers, which have facilitated immersion process integration and optimization. In early 2006, ASML commenced shipment of the first immersion systems for 45nm volume production, featuring an innovative in-line catadioptric lens with a numerical aperture (NA) of 1.2 and a high transmission polarized illumination system. A natural extension of this technology, the XT:1900Gi supports the continued drive for device shrinks that the semiconductor industry demands by offering 40nm half-pitch resolution. This tool features a projection lens based on the already proven in-line catadioptric lens concept but with an enhanced, industry leading NA of 1.35. In this paper, we will discuss the immersion technology challenges and solutions, and present performance data for this latest dual wafer stage TWINSCAN immersion system.

Silica glass exhibits a permanent anisotropic response, referred to as polarization induced birefringence (PIB), when exposed to short wavelength, polarized light. The magnitude of the PIB has been empirically correlated with the OH content of the glass. Our recent studies pertaining to PIB have focused on careful characterization of PIB, with particular emphasis on understanding all of the contributions to the measured birefringence signal and finally extracting only that signal associated with birefringence arising from exposure to a polarized light beam. We will demonstrate that a critical contributor to the total birefringence signal is birefringence that comes from exposure beam inhomogeneities. After subtracting beam profile effects we are able to show that PIB is proportional to the OH content of the glass. Polarized infrared (IR) measurements were performed on glasses that developed PIB as a consequence of exposure to polarized 157-nm light. These studies reveal that there is preferential bleaching of a specific hydroxyl (OH) species in the glass with OH aligned parallel to the incident polarization undergoing more bleaching than those perpendicular. Further, we observe a very strong correlation between the measured PIB of these samples and the anisotropic bleaching. From these studies we propose a mechanism that can explain the role of hydroxyl in PIB.

As Argon Fluoride (ArF) lithography moves into high volume production, ArF light sources need to meet performance requirements beyond the traditional drivers of power and bandwidth. The first key requirement is a continuous decrease in Cost of Ownership (CoO) where the industry requirement is for reduction in ArF CoO in line with the historical cost reduction demonstrated for Krypton Fluoride (KrF) light sources. A second requirement is improved light source performance stability. As CD control requirements shrink, following the ITRS roadmap, all process parameters which affect CD variation need tighter control. In the case of the light source, these include improved control of bandwidth, pulse energy stability and wavelength. In particular, CD sensitivity to exposure dose has become a serious challenge for device processing and improvements to laser pulse energy stability can contribute to significantly better dose control. To meet these performance challenges Cymer has designed a new dual chamber laser architecture. The Recirculating Ring design requires 10X less energy from the Master Oscillator (MO). This new configuration enables the MO chamber lifetime to reach that of the power amplifier chamber at around 30Bp. In addition, other optical modules in the system such as the line narrowing module experience lower light intensity, ensuring even longer optics lifetime. Furthermore, the Recirculating Ring configuration operates in much stronger saturation. MO energy instabilities are reduced by a factor of 9X when passed through the Ring. The output energy stability exhibits the characteristics of a fully saturated amplifier and pulse energy stability improvement of 1.5X is realized. This performance enables higher throughput scanner operation with enhanced dose control. The Recirculating Ring technology will be introduced on the XLR 500i, Cymer's fifth-generation dual chamber-based light source built on the production-proven XLA platform. This paper will describe the design details and performance characteristics of the new laser architecture.

In the history of DUV (Deep Ultra Violet) microlithographic lens design, three kinds of leaps have occurred to maintain the progress of technology in the semiconductor industry. The first step is the application of aspherical elements. This allowed us to increase NA up to around 0.9. The second innovation is water immersion. Thanks to the 1.44 refractive index of water, and because the numerical aperture (NA) is defined as the product of the sine of the maximum ray angle on the image plane and the refractive index in the image space, even with a lower maximum ray angle on the imaging plane than dry with a lens, we can achieve NA of 1.07. The latest technological jump is the development of catadioptric lens systems, which are roughly defined as the combined usage of refractive element(s) and reflective element(s). The catadioptric system allows us to achieve a full field 1.3NA projection lens that is used in our scanner NSR-S610C. In this paper we discuss optical design concepts and some challenges for catadioptric lenses. In addition, current lens performance including wavefront, lens flare, and image vibration are shown.

The 65nm and the subsequent 45nm node lithography require very stringent CD control. To realize high-accuracy CD control on an exposure tool, it is essential to reduce wavefront aberrations induced by projection optics design and manufacturing errors and then stabilize the aberrations while the exposure tool is in operation. We have developed two types of new hyper-NA ArF projection optics to integrate into our new platform exposure tool: a dry system and a catadioptric system for immersion application. In this paper, aberration measurement results of these projection systems are shown, demonstrating that ultra-low aberration is realized. In addition, a new projection optical system has been developed which incorporates high degree-of-freedom Aberration Controllers and automatic aberration measuring sensors. These controllers and sensors are linked together through Aberration Solver, a software program to determine optimal target values for aberration correction, thereby allowing the projection optics to maintain its best optical properties. The system offers excellent performance in correcting aberrations that come from lens heating, and makes it possible to guarantee extremely low aberrations during operation of the exposure tool.

In this paper alignment and overlay results of the advanced technology nodes are presented. These results were obtained on specially generated wafers as well as on regular manufacturing-type wafers. For this purpose, a new alignment sensor was integrated and evaluated in three generations of lithography tools, placed in R&D and mass manufacturing facilities. The capability of the sensor to align on marks with varying layout was evaluated. Long term overlay stability less than 11 nm was obtained on two different mark types: a standard ASML calibration mark and a flexible Toshiba mark design. The ability to align on low-contrast marks was validated by a dedicated experiment: typical alignment repeatability values of ~1 nm (3sigma) on shallow etch depth mark features of 25 nm are obtained for various mark designs, including flexible pitch alignment marks. From these results, design directions for improved mark detect ability were defined. The jointly developed mark designs were validated for their alignment robustness by an evaluation of manufacturing wafer alignment performance. On-product overlay results on manufacturing wafers were measured for three different process layers of the current technology node. The used alignment strategies were based on new mark capture and fine wafer alignment mark designs, thereby making optimal use of the mark design flexibility potential of the alignment sensor. Typical on-product overlay values obtained were less than 17 nm for the Active Area process layer, less than 12 nm for the Gate Conductor process layer, and less than 19 nm for the Metal-1 process layer; after applying batch corrections, as determined on a set of 2 send-ahead wafers. All results are based on full batch readout on an offline metrology tool. By applying optimal batch process corrections for linear terms, typical overlay values range between 10-14 nm, depending on the layer measured. Finally the sensor's infrared wavelengths were used to demonstrate a robust alignment solution for wafers containing a semi-transparent hard-mask layer.

The GT61A ArF laser light source with ultra line narrowed spectrum, which meets the demand of hyper NA (NA > 1.3) immersion tool, is introduced. The GT61A aims at improving spectrum performance from value E95 0.5pm of GT60A. The spectrum performance 0.3pm or less was achieved by developing an ultra line narrowing module newly. Moreover, in 45nm node, since it indispensably requires OPC (optical proximity correction) and a narrower process window, improved stabilization of spectrum performances was performed by bandwidth control technology. Newly designed Bandwidth Control Module (BCM) includes high accuracy measurement module which support the narrower bandwidth range and active bandwidth control module. It also contributes to the reduction of the tool-to-tool differences of the spectrum for every light source.

The practical extendibility of immersion lithography to the 45nm half-pitch is being investigated on a 1.30NA immersion projection microstepper installed at SEMATECH North in Albany, New York. Preliminary implementation of various aperture designs and polarization configurations have been used to demonstrate imaging beyond the 90nm pitch. Optical proximity correction (OPC) and other resolution enhancement technique (RET) strategies coupled with resist stack optimization of dual-layer bottom anti-reflective coating (BARC) systems offer a growing platform of materials and illumination configurations for the 45nm node. In this demonstration of a RET strategy, linear-polarized light is selectively rotated at the coherence aperture to simultaneously image sub-90nm pitch features along the x and y axes within the same field. Scanning electron microscope (SEM) images demonstrate the capability of the immersion micro-exposure tool (iMET) to support dual-orientation imaging with resolution down to the 84nm pitch.

As the pattern half pitch on the mask gets shorter than the wavelength by smaller device design rule, 3-D effect of the mask pattern topology becomes greater. The resolution approaches to that of the attenuated Phase Shift Mask (attPSM), when pattern size is smaller than 45 nm node. The binary mask was therefore selected due to the simple fabrication process and the advantage with no-haze, and its performance was evaluated both numerically and experimentally by newly designing the mask structure that may have mask immersion effects. This new mask can be made by depositing transparent oxide materials on a conventional patterned binary mask. When the change of NILS (Normalized Image Log Slope) was checked quantitatively according to duty ratio and oxide thickness, the NILS increased more than 10% on the average from the simulation and about 10-30% from the experiment, when compared with the binary mask. In other words, the mask structure with the transparent oxide layer improves the NILS and has the advantage in the DOF margin. Since only the deposition process is required after the binary mask is made, the manufacturing is relatively simple.

Sub-resolution assist features (SRAFs) have been used to enhance lithographic process window of main features. As the device is scaled down, the SRAF size decreases drastically and the distance between main features and SRAF closes up. The variation of main feature CD and SRAF size from mask production process influences destructively on gate CD control and it makes the device performance degraded. Fabrication of small and uniform-sized SRAFs is one of the key mask technologies because mean-to-target (MTT) and CD uniformity of SRAFs are more difficult to be controlled than those of main features. In addition, for sub-50 nm design nodes, mask topography effects can not be neglected because exposure wavelength is similar to a mask pitch from main feature to SRAF or SRAF to SRAF. In order to consider mask topography effects, all lithographic simulations were performed with a rigorous coupled wave analysis (RCWA) electromagnetic field calculation. In this study, we will demonstrate that SRAF size tolerance is deduced from the effects of SRAF size deviation from the mask production on a main feature CD. To define the SRAF size deviation effects, main feature CD variation is simulated for different SRAF sizes. We will explore SRAF size tolerances for sub-50 nm design nodes. It can be suggested as one of the mask requirements.

ArF is still being used as a main light source for lithography of critical layers due to development delay of alternative light sources. The resolution enhancement is therefore mainly depends on increasing the NA of the projection lens or on decreasing the k1 value. Depth-of-focus is becoming narrower in both the approaches than ever. It has been well-known that properly designed assist-features can improve the process window of lithography, but optimizing assist-features is generally not a simple task, unless the pattern area is small or all the patterns are well isolated so that the proximity effect can be safely ignored. It is challenging to generate assist-features automatically when the pattern area is not small or the patterns are not well isolated, both of which is not a case in today's memory devices. Today's memory chip has such a large pattern area that it easily occupies a large portion of the available imaging field of today's scanner. The proximity effect cannot be safely ignored because k1 factor is low in today's memory devices and the patterns are not isolated even in peripherals. A new method to generate assist-features has been internally developed. This method is based on optical simulation and utilizes the optical characteristic of the exposure tool to maximize the process margin, and is scalable to the full-chip scale. Side-lobes are automatically suppressed well under the imaging threshold. The total processing time is comparable to a usual model OPC processing time. The present paper demonstrates a test case of this new method to a contact layer of full-chip sub-70nm DRAM device and the improvement of depth-of-focus. The increased depth-of-focus was equivalent to 18% reduction of contact CD at the same depth-of-focus.

Chromeless Phase Lithography (CPL) has been used in sub-wavelength lithography resolution enhancement techniques (RET). As the device line width gets smaller toward 45nm technology and beyond, CPL process window optimization plays an important role to extend the limit of current optical lithography. In this study, 4 major areas of process window optimization are performed. Firstly, CPL data handling optimization and three-zone layout splitting are studied. Mask data is split into pure phase, zebra and pure chrome type based on the feature size. At the resolution limit, pure phase mask data type is used because the MEEF is low. Zebra mask data type will be used for feature size that is bigger than 75nm, while pure chrome feature is applied for feature sizes that are bigger than 180nm. Secondly, OAI and customize illumination optimization are studied. The 2D overlap region of the diffraction order within the entrance pupil is analyzed. The investigation shows that process window can be improved through background noise reduction and illumination optimization. Thirdly, polarization impact on high NA application is studied. Simulation results have shown DoF can be improved through the effect of polarization. Lastly, CPL mask quartz depth optimization and the effects of phase variation are studied. The investigation shows 180 degrees phase is not optimized for 193nm lithography. The effective phase for 193nm CPL is at 205 deg. With the above process window optimization, CPL demonstrates reasonable good process window on wafer printing. DoF with more than 0.3um on 65nm line with 160nm pitch has been achieved with using CPL under 0.85NA.

The use of sub-resolution assist features (SRAFs) is a necessary and effective technique to mitigate the proximity effects resulting from low-k1 imaging with aggressive illumination schemes. This paper investigates the application of one implementation of Inverse Lithography Technology (ILT) to determine optimized SRAF placement and size. In contrast to traditional rule-based methods in which SRAF placement and size are typically predetermined and frozen in place, unmodified during OPC, ILT allows for the simultaneous placement and sizing of SRAFs during target inversion to maximize image quality while also maintaining margin against sidelobe printing. Furthermore, ILT enables SRAF placement for random as well as periodic patterns. In this paper, SRAF placement using this approach is studied through simulations. The computed mask and simulation results are shown to illustrate effectiveness of ILT-generated SRAF features.

The existence of pitch range with depth of focus below a sustainable limit is a well known fact in lithography. Such 'forbidden pitch' range limits designers' ability to pack more functionality in a logic chip. One of the ways to increase the process window is to have a careful placement of SRAFs (Sub Resolution Assist Features) that can boost process window across the pitch range. However the standard SRAF strategy that has been followed historically is not always able to increase the process window of these 'forbidden pitches' sufficiently to allow sustainable manufacturing. With shrinking technology node, placement of SRAF is becoming rather difficult due to space limitations between concerned features and mask house's ability to manufacture mask with small assist features and smaller aspect ratios. In many cases the number of SRAF that can be inserted between main features in a symmetrical way is not enough to boost the process window. In this paper we discuss how asymmetrical placement of SRAF can increase process window for critical feature in layouts where such critical features are placed near not-so-critical patterns. We also discuss how such concepts can be extended to an array of critical features, where one SRAF is placed near a critical feature instead of placing them in the center. We finally demonstrate how wafer data confirm process window boost from such asymmetrical placement of SRAFs in gate layer for 65nm. We also show how to determine the optimal placement of SRAF in such cases and recommend some rules that can be used for 45nm node based on such results.

In our previous study, we introduced the method of intensity weighting over various image planes for FLEX (Focus Latitude Enhancement eXposure) process. By higher energy weighting on the best focus image for the approach of triple focal plane exposure, it demonstrated higher contrast over wide focus range than conventional FLEX, accordingly achieved the better performance on DoF (Depth of Focus), EL (Energy Latitude), proximity and CD uniformity. However, this technique limits the production capability by the increased number of images. Thanks for all the technology developments on RET (Resolution Enhancement Technology) with tool functionality, which is related to focus drilling method in scanner system. Hence there have been several papers addressed the focus drilling technique with high frequency illumination source recently, the focus drilling technique enables more continual image planes over focus range on advanced step and scan system while scanning the image with single uniformity energy level over various focus ranges [2-3]. In this paper, the approach combining focus drilling with intensity weighting was introduced to strengthen the potential of process in step and scan system. Since the hardware for focus drilling and intensity weighting is not available in our study, we've only demonstrated the technical concepts through simulation by Prolith Ver. 9.31. To achieve the effect of intensity weighting on the focus range, we've been suggested new idea of application and applied some treatment on data from simulation tool. Simulation result on intensity weighted focus drilling achieved higher EL and DoF than the conventional focus drilling at the same focus range.

Low k₁ lithography poses a number of challenges to the process development engineer. Although polarization and immersion lithography will allow us to create processes at lower k₁ than previous paradigms allowed, the lithographer will quickly be looking for Resolution Enhancement Techniques (RET) to push to the ultra-low k₁ regime, or to extend older generation tools and avoid the aforementioned expensive options. Reticle transmission is a RET that can enable a low k₁ process by increasing image contrast. With work performed in conjunction with our MP Mask facility, we have been able to obtain custom-transmission EAPSM reticles. Reticle transmission optimization can be carried out through simulation. Optimum transmission varies depending on optical parameters and feature size. Moreover, when working with 2D patterns, reticle transmission can be optimized for weaker features, without significantly sacrificing image contrast on primary features. Process improvement by optimizing reticle transmission will be explored for a variety of device types using both 248nm and 193nm lithography. Simulation, custom-transmission reticle fabrication, and empirical wafer results will be presented.

High-transmittance phase shift mask (HTPSM) and high numerical aperture (NA) imaging with polarized illumination have been proposed as one of the solutions of the 65nm technology node and beyond. Both aerial image simulations and experimental exposure results confirm the advantages of the polarized illumination for high NA imaging. However, influence of transmission rate of the PSM status upon imaging performance had not yet been fully investigated. Consequently, the influence of different transmission rate PSM with polarized illumination upon imaging performance including depth of focus (DOF), exposure latitude (EL) and line edge roughness (LER) has been researched in this study. Simulation of normalized intensity log slope (NILS) vs. mask transmission rate for the through pitch line space patterns compared with experimental data are clearly showed. Masks of various transmission rates from 6%~30% have been designed. The print images had been investigated with and without polarized illuminations of 193nm high NA tool. According to the experimental and simulation results, the high transmission rate 15% PSM certainly could enhance resolution for 50nm node and beyond.

Double patterning has become one of the candidates to bring us to the next node of the ITRS-roadmap. As an alternative to immersion lithography with higher index fluids and EUV lithography which both require considerable changes in infrastructure, double patterning makes use of the existing infrastructure. Because of this, double patterning has gained considerable attention during the past few years. It has become a serious candidate to reach the 45 nm node and even the 32 nm node. Most of the currently known double patterning techniques have relatively complex process flows, which may prevent them from being used in production. One of the complicating factors is the use of an etch step in between the two lithography steps. This etch step is necessary to transfer the pattern of the first resist layer into an underlying hard mask before a second exposure can be done. Another complicating element, arising in several known double patterning techniques, is the translation of overlay error in CD-error. This translation occurs when a feature is printed in two exposures, i.e. not features but the spaces between them are patterned, patterning the left and right edge of a feature in different exposures. In this paper, we examine and evaluate a novel double patterning method that does not include transfer etch in between the lithography steps. This method would simplify the double patterning process. Furthermore, each feature is patterned completely in one exposure, for which CD-value is not affected by overlay error. This paper discusses the feasibility of the new double patterning method and compares it to conventional double patterning schemes. Furthermore, an assessment will be made whether the proposed technique has the potential to be used in production.

As the semiconductor fabrication groundrule has reached the 32nm node, in general there are several possible approaches for the photolithography solution such as the double exposure with 1.35 NA immersion, the high refractive index immersion, the extremely ultra violet (EUV) lithography, nanoimprint lithography etc. Among the four, the easiest approach seems to be the double exposure method at an effective numerical aperture (NA) of 1.35. However, there are still challenges in the design and optimization of the process, such as, the use of appropriate illumination condition, the choice of a good photoresist, and the design of an optical proximity correction (OPC) strategy. Besides these considerations, there is a question as whether we really need the double etch process. To study the double exposure mechanism, we have used a 248 nm deep-UV exposure tool and several well chosen photoresist (one is for Space application and the other is for Line application) to study the photo performance parameters in the merge of two photo exposures. At a numerical aperture (NA) around 0.7, the minimum groundrule we can achieve is the one for a 75 nm logic process with minimum pitch around 220 nm. One approach will be that the features with pitches wider than 440 nm are completed in a single exposure, which includes various isolated lines and spaces, line and space ends, two-dimensional structures, etc. This strategy essentially puts the single exposure pattern under the 0.18 um logic like pitches where mild conventional illumination can produce a balanced performance. Under typical illumination conditions, the photolithographic process under 0.18 um like ground rule is well understood and the optical proximity correction is not complicated. The remaining issues are in the dense pitches, where the double exposure kicks in. We have demonstrated that the double exposure with single development can achieve a process window large enough for a 75 nm logic like process and the OPC behavior such as line through pitch is manageable although OPC correction strategy may require substantial improvement to accommodate two individual exposures. In this paper, we will demonstrate the result of our study of the basic photolithographic performance indicators, such as the exposure latitude (EL), the depth of focus (DOF), the CD through pitch, the line edge roughness (LER) and the mask error factor (MEF) for the optimized process. And we will discuss the choice of photoresists for this special application. It seems that a photoresist with a balanced performance for both the line and space is necessary to realize a good double exposure process. In this paper, we will also present our simulation result of effective resist diffusion length to explore the limit of such approach.

With the semiconductor fabrication groundrule approaching the 32 nm node, double exposure or patterning method with 1.35 NA immersion seems to be the primary candidate due to its relative easiness to implement when compared to the other two competitors, the high refractive index immersion and the 13.4 nm extremely ultraviolet (EUV) lithography. However, the splitting of one mask into two is not a trivial task. In this paper, we would like to discuss about the best splitting method for several typical 2D structures, such as the isolated opposing line (or space) end shortening, T-like structures with narrow gaps, etc. From our recent experimental studies, we have found that, for line and space photolithography, the optimized illumination condition has a sigma value very close to 0.5. When compared to the single exposure processes, which will typically use more annular condition, a sigma of 0.5 can generate worse process windows for isolated features. This will put more pressure on the precision of the already challenging optical proximity correction (OPC) because the doubly exposed patterns and singly exposed patterns follow two different models. In our study, we find that the extra degrees of freedom in the double exposure method can be utilized to repair some intrinsic printing deficiency, such as, line end shortening. In this paper, we will analyze each typical 2D structure and, for each splitting method of the typical 2D features we study, we will discuss its capabilities in realizing good process windows, the MEF, and OPC correction easiness.

In order to reduce the overall size of device features, continuing development in the low k1 lithography process is essential for achieving the feature reduction. Although ArF immersion lithography has extended the feature size scaling to 45nm node, investigation of low k1 lithography process is still important for either ArF dry or wet lithography. Double patterning is one procedure pushing down the k1 limit below 0.25. It combines the multilayer hard mask application and resist shrinkage process to get the feature size reduced to quarter pitch of the illumination limit. In recent spin-on hard mask studies, silicon containing bottom antireflective coatings (BARC) have been developed to combine the function of reflective control and great etching selectivity to the photoresist. Trilayer resist including the photoresist, silicon containing BARC and planarizing organic underlay can improve the reflectivity by optical index tuning of dual hard mask layer effectively and reduce photoresist thickness to avoid the pattern collapse with small features. In our study, we found some interesting characteristics of trilayer resist could be used for double patterning technology and made the low k1 process more feasible. This procedure we investigated can make the feature size of half pitch reduce to 37nm and beyond at 0.92NA under ArF dry lithography. Among the resolution enhancement for ArF dry illumination, double patterning scheme, overlay controllability and pattern transfer process by reactive ion etching (RIE) will be discussed in this paper.

An enormous pressure is currently put on Resolution Enhancement Techniques to meet the deadline for the development of high density memory devices. The prevailing conviction is to consider water immersion lithography as the choice for manufacturing 45nm technology node devices. Even if a huge effort to face immersion specific issues has been done (on defectivity, micro-bubbles, contamination, overlay control, hyper NA imaging, birefringence), a technology solution to image the desired features and densities must be available till now in order to anticipate all the steps involved in the process integration before the complete assessment of the immersion infrastructure. Moreover, the forecasted solutions for 32nm and 22nm technology nodes remain uncertain, strongly depending on current and near future development of high index fluids for immersion lithography and EUV availability. These temporal lacks of technology options are forcing scanner suppliers and IC manufacturers to include also double exposure in the group of viable choices for future development. Double patterning (double exposure and double etch) is surely a fascinating solution for overcoming the physical resolution limit of k₁ = 0.25 of imaging systems. Various papers in these last two years demonstrated an increasing interest in the exploration of such kind of technique to extend as much as possible ArF dry exposure tools. Though the concept of this technique is simple and well known, there are various technical issues which must be solved before moving to a real implementation in the manufacturing phase. In this paper we want to present the experimental results of the application of double patterning to the definition of a 45nm technology node Flash memory device, reaching a k₁ ~ 0.20 using 193nm dry lithography. Flash memory design introduces imaging critical points in several levels: active, contacts, and first metallization. For each of these layers, a dedicated study of double exposure has been performed in order to develop a combined litho-etch process to pattern the requested features density. Different issues will be reported, related to process choices (hard mask, resist compatibility), overlay performances, OPC and layout decomposition. Experimental process windows of dedicated test masks with lines and spaces and contact holes are shown. A deep study on overlay performance and possible optimizations has been performed and will be reported. Finally, we will demonstrate that double exposure technique can be used to anticipate process integration of critical lithography steps for high density memory devices at 45nm technology node.

Double patterning has been proposed as a method to extend DUV lithography to 32nm and below. Here, a new form of double, or higher, multiple exposure technique is proposed. This new form of lithography uses a combination of Quantum State Control (QuSC) chemistry, Amplitude Modulation Optical Lithography (AMOL), and multiple micro-stepped exposures, without development between exposures. Further it is proposed to use this form of lithography (called QuSC-litho), to pattern a perfect grating grid, and to trim this grid with an earlier generation lithography tool. QuSC lithography uses short optical pulses to modulate a photochemical pathway while an intermediate is still in a defined vibrational excited state. This is a variation of Stimulated Emission Depletion Microscopy (STED) developed for fluorescence microscopy. With this approach immersion tools that produce 90 nm pitch and 45 nm features should be able to pattern levels with 22 nm features with a 1:1 line-space ratio. This approach is much less sensitive to misalignment than present double patterning approaches. Key to successful deployment of QuSC lithography is defining a resist photochemistry consistent with the QuSC process. There are several approaches to Photo Acid Generator (PAG) - matrix interaction that may be consistent with this approach.

Double exposure is one of the promising methods for extending lithographic patterning into the low k₁ regime. In this paper, we demonstrate double patterning of k_1-effective=0.25 with improved process window using a negative resist. Negative resist (TOK N- series) in combination with a bright field mask is proven to provide a large process window in generating 1:3 = trench:line resist features. By incorporating two etch transfer steps into the hard mask material, frequency doubled patterns could be obtained.

As semiconductor process technology moves to smaller generations (65nm and beyond), the contact pattern printing becomes the most difficult challenge in the lithography field. The reason comes from the smaller feature size and pitch of contact/via pattern printing that is similar to 2D (two-dimensional) patterning. Contact and via patterns need better image contrast than line/space patterns in pattern printing. Hence, contact/via printing needs a higher k1 value than others. In 65nm generation experience, the k1 is ~0.44 on a 0.85 NA exposure tool. A larger NA exposure tool is expensive and developed slower than the motivation of generation. Hence, the process is difficult to achieve by obtaining larger NA exposure tools. The k1 requirement of 45nm (logic) contact pattering (minimum pitch: 140nm) is ~0.34 on a 0.93 NA exposure tool that is available currently. RET (resolution enhancement technology) is necessary to achieve the difficult process goal. Splitting pitch technology is an RET approach to solving 45nm contact pattering. In this paper, we use a 2P1E (2 photo exposure and 1 etching) approach to meet our process requirements. The original layout is split into dense pitch pattern and semi-iso to iso pattern parts by software. Utilizing strong OAI (off-axis-illumination) on dense pattern part and weak OAI on semi-iso to iso pattern part can obtain better process results.

Among the three candidate approaches for 32 nm, the double exposure/patterning with 1.35 NA immersion, the high refractive index immersion, and the extremely ultra violet (EUV) lithography, the easiest approach seems to be the double exposure/patterning method at an effective numerical aperture (NA) of 1.35. However, the design and optimization of the process, such as, the choice of illumination condition, the choice of a photoresist, and the design of an optical proximity correction (OPC) strategy for both the singly and doubly exposed patterns still need to be developed. In this paper, we will focus on the finding of a suitable methodology in the printing of two-dimensional (2D) structures under the double exposure and single development scheme since it is the easiest and there is virtually no overlay concern. We have used a 248 nm exposure tool and a well-chosen photoresist to study the photo performance parameters in the merge of two photo exposures. At a numerical aperture (NA) around 0.7, the minimum ground rule we can achieve is 110 nm, similar to the one for a 75 nm logic-like process with minimum pitch of 220 nm. In the experiment, the single exposure structures are limited to pitches wider than 440 nm. In this paper, we will present a study on main process window parameters, such as, exposure latitude (EL), depth of focus (DOF), and mask error factor (MEF) for a typical 2D structure, the isolated opposing line end. We will demonstrate a nearly analytical method for the description of the line end shortening.

The double exposure technique using alternating phase shift mask (alt-PSM) has been proposed and it is well used for the gate layer of the high performance logic devices as strong resolution enhancement technology (RET). This technique has advantage that the fine resist profile is obtained on wafer with extensive process margin. However, this double exposure technique is very expensive because of the alt-PSM cost. This time, the new double exposure technique without alt-PSM is developed for gate layer of 45 nm node logic devices. In this new double exposure method, attenuated phase shift mask (att-PSM) or binary mask (BIM) is used with dipole illumination. It is thought that this new double exposure method is effective for random logic devices which have various pattern pitches by the optimization of dipole illumination condition and pattern placement. Firstly, the optical contrast and depth of focus (DOF) is calculated. From these results, dipole illumination condition is optimized. It is found that DOF of new double exposure method is wider than that of conventional method. In addition, mask pattern is optimized to obtain wide process margin. For dense pattern, mask biasing is effective and optimization of shifter width is effective for isolated pattern. Furthermore, it is found that assist pattern is very effective for isolated pattern. From experimental results, it is proved that new double exposure method have wider process margin than that of conventional one. The strong design for manufacturing (DFM) rule that required the severe line width control is placed at single direction is proposed to realize the new double exposure method. Finally, it is found that the lithographic performance of new double exposure method has same level as conventional method with alt-PSM for gate layer of 45 nm logic devices.

Multiple paths exists to provide lithography solutions pursuant to Moore's Law for next 3-5 generations of technology, yet each of those paths inevitably leads to solutions eventually requiring patterning at k₁ < 0.30 and below. In this article, we explore double exposure single development lithography for k₁ ≥ 0.25 (using conventional resist) and k1 < 0.25 (using new out-of-sight out-of-mind materials). For the case of k₁ ≥ 0.25, we propose a novel double exposure inverse lithography technique (ILT) to split the pattern. Our algorithm is based on our earlier proposed single exposure ILT framework, and works by decomposing the aerial image (instead of the target pattern) into two parts. It also resolves the phase conflicts automatically as part of the decomposition, and the combined aerial image obtained using the estimated masks has a superior contrast. For the case of k₁ < 0.25, we focus on analyzing the use of various dual patterning techniques enabled by the use of hypothetic materials with properties that allow for the violation of the linear superposition of intensities from the two exposures. We investigate the possible use of two materials: contrast enhancement layer (CEL) and two-photon absorption resists. We propose a mathematical model for CEL, define its characteristic properties, and derive fundamental bounds on the improvement in image log-slope. Simulation results demonstrate that double exposure single development lithography using CEL enables printing 80nm gratings using dry lithography. We also combine ILT, CEL, and DEL to synthesize 2-D patterns with k₁ = 0.185. Finally, we discuss the viability of two-photon absorption resists for double exposure lithography.

A number of new packaging technologies are driving the demand for high performance dual-side alignment (DSA) on 300 mm lithography systems. Advanced system in package (SiP) techniques will require through silicon vias to allow very high density vertical interchip wiring of multiple device stacks. These through silicon vias need to be freely placed in the device which creates a requirement for tight registration of the back-to-front side alignment. In the MEMS area, wafer level packaging is being used for applications where the device must interact with the outside environment without performance restrictions from the packaging. An example is image sensor chips where the charge-coupled device is on the front side and the electrical interconnects to the signal processing die are on the back side. This application requires dual-side alignment on a 300 mm bonded silicon glass sandwich structure. To support these packaging applications a new lithography stepper capable of dual-side alignment on 300 mm wafers has been developed. This stepper employs an innovative and flexible system for back-to-front side alignment to support a wide range of packaging applications. This paper discusses the design and integration of the alignment system on a broad band, low numerical aperture stepper. Experimental target capture for CMOS image sensor applications is shown. Dual-side overlay performance data on multiple wafers and lots is reviewed.

Flare has been important variable to achieve good CD control in low k₁ lithography. Early works on flare have focused on long-range DC and local flare, with an attention on how to measure flare and how flare impact on CD control within theoretical model for ideal situation. As pattern size decreases below 100 nm, however, short-range flare begins to appear prominently beyond that technology node. It has been pointed out that process conditions such as photo resist thickness, substrate film stacks, and even some times photo masks can be important variables for short-range flare but impact of process variables on flare at illumination level has less been understood yet. Recently, Yun et al. have shown that the illumination conditions such as coherence factor and illumination aperture shapes also give impact on short-range flare. They found that the amount of short-range flare, the additional portion of the diffraction image to the ideal one, increases as the illumination aperture size increases but inner radius of the annular illumination apertures affect little on the amount of the short-range flare. In this paper, as the series of the experiments by Yun et al., we will prove detailed relation between illumination aperture shapes and the short range flare by exploring its impact with number of off-axis illumination apertures including multi-pole illumination apertures, in addition to the previous data on partially coherent conventional and simple annular illumination apertures. We utilize the 193-nm scan-and-step exposure tool and evaluate the short-range flare by measuring CD on the 100 nm lines surrounded by clear window having various open ratios. The extended data on various off-axis illumination apertures reveal clarify the impact of illumination aperture shape on the short-range flare.

Optical proximity correction (OPC) plays a vital role in the lithography process for critical dimension (CD) control. With the shrinking of the design rule, CD is more sensitive to lithography process, so the task for OPC becomes more challenging. Flare, or stray light, is an added incoherent background intensity that will detract from lithography system performance, CD control and process latitude. The impact of flare on lithographic imaging and its correction through OPC has been the subject of increased investigation. In this paper, the flare effects on CD variation by changing the total image intensity are discussed. The flare map is obtained by running the flare model on the mask layout. Based on the flare map, flare test patterns are designed and flare test reticle is written. After collecting wafer silicon data with CD SEM, flare model is verified and the flare impacts on the across chip line width variation (ACLV) are presented. With the existence of flare, CD bias across different areas of the cell could be measured. As CD varies by a comparatively wider range than optical proximity range, it could not be corrected by existing OPC model. Based on the analysis of flare model and the experiment results, applications on flare correction are discussed by using OPC.

For many years, we have used a lens aberration controller that works via positioning elements of the projection lens assembly. While this has worked well, its disadvantage is that controllable aberrations are only relatively low order components and not enough for the degree of compensation of thermal aberrations required by leading-edge lithography. We have developed two methods to overcome thermal aberrations specific to dipole illumination exposure. One scheme is process-dedicated aberration control by the conventional aberration controller. The other is aberration control system using infra-red irradiation. This system can compensate uniform astigmatism which is generated by asymmetric setting of illumination light sources, such as dipole illumination schemes. Theses two techniques allow us to increase productivity by reducing pattern imaging performance degradation due to thermal aberrations. These schemes are applicable not only to current systems but also to next generation very low k1 lithography systems with very high throughput.

Telecentricity has long been recognized as an important property of lithography-tool optics. "Shift" telecentricity error, an angular misalignment of the illuminator and projection lens, manifests itself as an unwanted translation of the aerial image through focus. At best focus, no effect is visible. Generally, litho tool acceptance tests measure directly the translation through focus, although it is also possible to use pupil-imaging techniques to observe the error by measuring offset of the pupil fill with respect to the projection lens NA. Even with a perfectly aligned system (i.e. a perfectly centered pupil fill), it is still possible to induce a translation through focus. This arises especially in multipole pupil fill patterns (dipole, quadrupole, etc.) which have one pole brighter than the others. We refer to this effect as "quasi-telecentricity." With the tight pitches and extreme polar illumination patterns coming into increasing use, this effect will become more important in the next few years. We have calculated the size of the effect and placed limits on the illumination patterns that can be used for this type of printing.

Uniform illumination of the mask is a key factor for the lithography process. The requirements of Immersion Lithography make illumination systems even more complex e.g. by adding additional parameters like polarization and improved throughput. Arrays of refractive microoptics are the ideal solution for high transmission homogenizing elements since several tool generations. These arrays can provide very steep intensity profiles (top hat and other profiles), enable lossless polarization control and do not suffer from zero order losses like diffractive elements. Usually refractive microlens arrays are used with macrooptical field lenses in order to illuminate a field very uniformly or with a customized intensity distribution. High numerical apertures create the necessity for aspherical surfaces which leads to significantly higher lens cost especially for the macrooptics. In this paper we present novel microoptical homogenizers which create extremely uniform intensity distributions for high numerical apertures without any field lens or at least only with spherical field lenses. Especially multi-pole off-axis illumination can be improved with less optical components. An important prerequisite for these special types of homogenizers is that LIMO can produce free form surfaces on monolithic arrays larger than 200 mm with high precision and reproducibility. Every lens can be designed individually and can also be shaped asymmetrically. We will present surface test methods and the final UV tests, guaranteeing the performance for the applications. Example data gained with these tests will be shown with regard to: meeting the design parameters, reproducibility over one wafer and reproducibility in large lots. Monolithic elements based on crossed cylindrical lenses provide a fill factor close to 100%. Simulations and measurements prove that microoptic arrays can be produced which provide a uniformity of the homogenized laser light of significantly better than 1% P-V at numerical apertures above 0.35. Refractive microoptic arrays do not change the polarization state of the transmitted light which is an important prerequisite in immersion exposure tools. LIMO homogenizer sets are manufactured from fused silica and Calcium Fluoride thus they are suitable for all DUV wavelengths at highest laser fluxes.

We have developed a solid-state 193-nm laser source operating at 5-kHz that generates a near-diffraction-limited TEM₀₀ beam with 35 mW average power. The frequency spectrum is Gaussian, with a linewidth ~7-pm (FWHM), corresponding to a coherence length of ~2-mm. The output beam also has a very high degree of spatial coherence. This source was used in an interferometric liquid-immersion lithography test stand to produce 40- and 35-nm half-pitch grating structures over a ~0.6-mm field of view with a commercially available chemically-amplified photoresist.

Crystalline calcium fluoride is one of the key materials for 193nm lithography and is used for laser optics, beam delivery system optics and stepper/scanner illumination optics. In comparison to fused silica it shows a much higher laser durability. However, even in pure calcium fluoride the irradiation by ArF excimer laser (193nm) can cause transmission loss and depolarization. Short time and long time tests of radiation induced changes of optical properties of CaF₂ were carried out. Within short time tests initial and radiation induced absorption as well as the measurement of laser induced fluorescence and the measurement of laser induced depolarization are adequate methods for characterization of the material under ArF laser irradiation. Previous investigations were done by Burnett to prevent depolarization caused by spatial dispersion. Nevertheless an important challenge is the prevention of depolarization of the polarized laser beam by CaF₂ laser optics caused by a temperature gradient. The dependence of depolarization on the direction of temperature gradient in comparison to the direction of the laser beam and the orientation of the CaF₂ crystal was investigated. In the present work different paths to prevent or mitigate the depolarization by CaF₂ due to a temperature gradient are discussed resulting in a special chance to mitigate depolarization by a laser window.

Reliable high power 193nm ArF light source is desired for the successive growth of ArF-immersion technology for 45nm node generation. In 2006, Gigaphoton released GT60A, high power injection locked 6kHz/60W/0.5pm (E95) laser system, to meet the demands of semiconductor markets. In this paper, we report key technologies for reliable mass production GT laser systems and GT60A high durability performance test results up to 20 billion pulses.

Increasing throughput demands on leading edge scanners are requiring greatly improved light source availability. This translates directly to minimizing downtime and maximizing productive time, as defined in the SEMI E10 standard. One positive contributor to improving productive time is the minimization of the light source stoppage for entire Halogen gas replenishment. This paper describes availability improvements of Cymer XLA and 7000 series light sources by using advanced gas management schemes to minimize entire gas replenishment impact to productive time. Recent augmented gas control algorithms have demonstrated multiple times extension of gas life through advanced gas replenishment methods and higher performance estimators. Along with these improvements to gas management, major efforts in light source fault reduction, module lifetime extension and optimization of module replacement, will provide significantly increased combined light source\scanner availability.

The rapid advancement in lithography and continuing shrink in feature dimensions demand tighter overlay tolerances for fabrication of memory circuits with higher yields (Refer to table 1 for ITRS overlay requirements). To meet tight overlay tolerances, sources of alignment errors need to be identified and corrected accurately. Alignment errors can be contributed by 3 factors; wafer induced shift (WIS), tool induced shift (TIS) and WIS-TIS interaction. WIS is introduced by wafer processing while TIS is introduced by the alignment tool (i.e. scanner or metrology). This paper introduces methods for improvement of alignment performance at layers that experience WIS. A study on mark reflectivity was done. A number of various alignment mark designs were evaluated. The most robust mark to Tungsten Chemical Mechanical Polishing (WCMP) process, based on experimental results, will be illustrated. The concept of the 'Alignment Parameter Optimizer' to select the best alignment illumination mode for each mark and the best sample shots for alignment within the wafer, taking throughput into consideration, will be discussed. A new alignment algorithm that is able to compensate for asymmetric alignment marks will also be presented in this paper. Finally, production data from a Dynamic Random Access Memory (DRAM) manufacturer with the implementation of the above-mentioned concepts will be illustrated.

In CMOS image sensor, microlens arrays are generally used as light propagation carrier onto photo diode to increase collection efficiency and reduce optical cross-talk. Today, the scaling trend of CMOS technology drives reduction of the pixel size for higher integration density and resolution improvement. Microlenses are typically formed by photo resist patterning and thermal reflowing, and the space between photo resist is necessary to avoid merging of microlenses during thermal reflow process. With the shrinking sizes, microlenses become more and more difficult to manufacture without their merging. Hence, the key of light loss free microlens fabrication is still zero-space between microlenses. In this paper, we report the selection of the optimum shape of microlens by the dead space and the curvature of radius. The improvements of critical dimension and thickness uniformities of microlens are also reported.

An extension of water-based immersion lithography involves replacing water with a higher index transparent oil. Understandably, potential lens contamination is a major concern for an all-organic immersion fluid. We have constructed an experimental system for controlled irradiation of high index fluids, including capabilities for in-situ cleaning of potential deposits. We present results of laser-irradiation of several high index immersion fluid candidates. Using properly developed exposure metrics, we discuss implications for fluid lifetimes in an immersion system, with and without in-situ purification. Using our in-situ metrology, we are able to decouple bulk fluid degradation from window photocontamination for several fluids. We find a significant variation in optics contamination rate depending on the fluid tested. Even the slowest observed contamination rates would require some remediation strategies to remove the built-up deposit from the final element surface. We also present results of irradiation of model hydrocarbon compound fluids. Irradiation of these materials leads to fundamental understanding of underlying photochemistry, and also provides guidance in designing future generation high index fluids.

A solution tool to optimize exposure tool functions has been developed. Shown are examples of pattern matching, maximizing ED-window or NILS considering several patterns simultaneously, and so on. From these results, the following conclusions have been derived. Pattern matching whose accuracy less than 1nm can be attained flexibly by tuning illumination. Ideal illumination for hole patterns through pitches are shown and the results are sensitive to setting of exposure latitude of ED-window. Evaluation conditions such as evaluated locations and their numbers have impact on the optimization results. An optimized illumination of a device pattern varies according to k1 factor. And it is important to apply OPC during illumination optimization in case of optimizing several patterns. A model of resist simulation created by an exposure condition should be available for various exposure conditions during optimization. For this purpose an image log slope and a pattern curvature have strong impact among various characteristics of optical image.

With the recent scaling down of k1 factor, the importance of illumination systems for lithographic exposure tools has been growing rapidly. This paper addresses OPC matching technology and polarized illumination that draw special attention for illuminators for 45nm node lithography applications. In the first half of the paper, OPC matching technology is reported. It is considered that less tolerance will be given to matching errors in the 45nm node and the need for matching of individual errors inherent in exposure tools may arise. In this paper, the MDI method, a method of OPC matching through direct evaluation of the effective light source, is proposed presenting its benefits. This method enables on-site accurate matching. The latter half of the paper reports on polarized illumination which is regarded as a standard technology in hyper-NA lithography regions. We have scrutinized the polarized illumination performance required to obtain excellent printing quality, and clarified polarization performance indicators that need to be assessed and controlled. As a result, it has been found that such indicators to be assessed at the mask level need to include the phase difference between the two orthogonal polarization components as well as the degree of polarization.

Since the last decade many efforts in optical lithography are devoted to the improvement of various system components both in order to enhance the optical resolution and to decrease the printing error. Last year we presented a general (i.e. nonparametric) method of the optimization of the pattern-independent components of partially coherent imaging system, such as both the illuminator and the final lens pupil distributions. Here we present further development of the method for the case when printing at only certain orientations is required. We demonstrate the improvements of both CD linearity and the resolution for two important examples. The first one is an optimized stepper, where printing at one orientation is mainly required. The second case is an SLM-based mask writer with four main rotations, such as 0, 45, 90 and 135 degrees. The first experimental results for the second case are demonstrated to be in agreement with the simulation.

The perfect top hat illumination source never exists but is widely assumed and used in lithography simulations for scanner performance investigation, process development and OPC verification. As line width shrinks below 45nm, the simulation error caused by using this idealized top hat source is no longer negligible in the hyper-NA immersion lithography. In this paper, we aim to make a systematic study of the lithography difference between the realistically smoothed and sloped illumination source (smooth source) and the top hat source. The simulation results consist of two parts. In the first part, we carried out a numeric investigation of the lithographic sensitivity for the commonly assumed source imperfections: center-shift, intensity imbalance, geometric ellipticity and energetic ellipticity. In the second part, we investigated the impact of the slope of smooth sources in both radial and azimuthal direction. A smooth source model was used to generate the smooth and top hat sources with such imperfections, and then imported them into simulation software SOLID E for computations. The CD and pattern shift were calculated through pitch and focus. The simulation results showed that the lithographic sensitivity to illuminator imperfection is pronounced. An error up to 5nm CD difference was observed between smooth and top hat sources. This study demonstrates that the prediction accuracy can be significantly improved by using smooth source in simulations in hyper-NA immersion lithography.

In previous OPC model calibrations, most of the work was focused on how to calibrate a model for the best process conditions. With process tolerance decreasing in coming lithography generations, it is increasingly important to be able to predict pattern behavior through process window. Due to a low k1 factor that leads to a smaller process window, the use of process window models is required for both optical proximity correction (OPC) and Lithography Rule Check (LRC) applications to insure silicon success. In this paper, we would try to calibrate multiple process window models. The resulting models will be verified and judged using additional measurement data to demonstrate the quality.

The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting latent images in the wafer due to exposure of different design layouts. Accurate models can precisely capture the proximity effects for the lithographic process and help RET engineers build the proper recipes to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the lithography environment that we want to model, and metrology data are collected for these geometries. This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist edge) data however model calibration requires EPE data for simulation. To work around this problem, only symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements. In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond. The absence of 2D and asymmetric test structures in the calibration process would require models to interpolate or extrapolate the EPE's for these structures in a real design. In this paper we present an approach to extract the EPE information from both SEM images and contours extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a 55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each of these structures can be individually weighed according to the data variance. Model accuracy is then compared to the conventional method of calibration using symmetrical data only. The paper also illustrates the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to errors compared to the conventional method.

The number of tunable parameters increases dramatically as we push forward to the next node of hyper-NA immersion lithography. It is very important to keep the lithographic process model calibration time under control, and its end result insensitive to either the starting point in the parameter space or the noise in the measurement data. For minimizing the least-squares error of a multivariate non-linear system, the industry standard is the Levenberg-Marquardt algorithm. We describe a distributed computing technique that is natural to the algorithm, and easy to implement in a cluster of computers. Applying this technique to calibrating lithographic process model, we can achieve robust optimization results in nearly constant calibration time.

Since 193 nm ArF lithography is the practical wavelength, the high and hyper numerical aperture technologies prolong and start its lithography ending for further improvement of the resolution. Application of polarization illumination leads to the 25 % increase of depth of focus and exposure latitude. Hence, polarization simulation becomes a key technology for its control and application. In this paper, polarization of numerical aperture is modeled into aerial image by using a vector model as an improved scalar model. In terms of small half pitch nodes, polarized effects are described into aerial and resist images. For high and hyper numerical aperture, the TM polarized degradation of aerial and resist images are severe, so that the reduction of TM polarization is required for below 45 nm half pitch pattern formation. In the comparison with the un-polarized small half pitch formation, the optical proximity effects of TE polarization are similar for dense patterns, but those effects are different for sparse patterns. Hence, the sparse pattern formation of TE polarization is preferred to the optical proximity correction.

The combined impact of longitudinal chromatic aberrations, focus-drilling, and Z-noise on several lithographic performance metrics is described. After review, we investigate an improved method for simulating the lithographic behavior of longitudinal chromatic aberrations stemming from the finite bandwidth of excimer laser pulse-spectra using PROLITH^TM v. 9.3.3. Additionally, we explore two methods for modeling the lithographic improvements related to focus-drilling and new PROLITH functionality for modeling the effects of Z-noise. Our case studies involve reinvestigating the RELAX process and providing a framework for accurate lithographic simulation using machine specific pulse-spectral data, modified Lorentzian, and Gaussian models. After presentation and analysis, we discuss potential applications including methods for improved focus budgets and improved mask design.

This paper introduces Dr.LiTHO, a research and development oriented lithography simulation environment developed at Fraunhofer IISB to flexibly integrate our simulation models into one coherent platform. We propose a light-weight approach to a lithography simulation environment: The use of a scripting (batch) language as an integration platform. Out of the great variety of different scripting languages, Python proved superior in many ways: It exhibits a good-natured learning-curve, it is efficient, available on virtually any platform, and provides sophisticated integration mechanisms for existing programs. In this paper, we will describe the steps, required to provide Python bindings for existing programs and to finally generate an integrated simulation environment. In addition, we will give a short introduction into selected software design demands associated with the development of such a framework. We will especially focus on testing and (both technical and user-oriented) documentation issues. Dr.LiTHO Python files contain not only all simulation parameter settings but also the simulation flow, providing maximum flexibility. In addition to relatively simple batch jobs, repetitive tasks can be pooled in libraries. And as Python is a full-blown programming language, users can add virtually any functionality, which is especially useful in the scope of simulation studies or optimization tasks, that often require masses of evaluations. Furthermore, we will give a short overview of the numerous existing Python packages. Several examples demonstrate the feasibility and productiveness of integrating Python packages into custom Dr.LiTHO scripts.

Solid immersion lithography has been investigated as a successor to liquid immersion lithography as a single exposure option for the 32 nm node. Current demonstrations have been limited to interferometric imaging. We model the solid immersion lithography process rigorously, including the evanescent wave phenomena, in a commercial lithography simulator. The lithographic process space is explored for conditions such as process window, resist thickness, gap width, and gap material. Vector imaging, followed by full resist kinetics and development, is performed for all calculations. Mask error factor, CD through pitch, and other issues significant to lithography are explored.

In the application of model-based optical proximity correction (OPC) to a full chip layout, lithography simulators require fast imaging algorithms to quickly obtain the critical dimensions (CDs) of the printed features. Model accuracy is frequently traded-off for speed in order to shorten the computation time for full chip design. The sum-of-coherent systems approximation represents the current standard for fast image computation. This approximation decomposes the optical system response function in the Hopkins imaging equation into a sum of products of its eigenfunctions, or kernels, via singular value decomposition. The partially-coherent optical imaging system is then represented as a sum of images formed by coherently illuminated optical systems with transfer functions corresponding to the kernels of the optical system response. The eigenvalues usually decay quickly, depending on the properties of the optical system. Current models will typically use the first few dominant kernels since each additional kernel adds to the computational time. However, there is no general guideline that indicates where to cut off the series in order to obtain the necessary accuracy. In this paper, we propose a generally applicable heuristic for choosing the number of kernels. We describe a few heuristics that show how to truncate the number of kernels that are included in a lithography model calibration, resulting in a more efficient model for OPC treatment. The heuristics are based on various eigenvalue measures such as the energy or the degree of coherence and express the CD error as a function of these measures. The heuristics then show the number of kernels needed for a given accuracy.

Our case study experimentally gauges the defocus component induced by a step in the exposure field substrate, with the edge of the step aligned parallel to the scanning slit. Such steps frequently occur at the border of different chiplets or process monitors within one exposure field. A common assumption is that a step-and-scan imaging system can correct for the majority of such topography, since the wafer is dynamically leveled under the static image plane as it is scanned. Our results show that the range of defocus approaches about 85% of the actual step height and thus contributes significantly to the overall focusing variance. This area on the wafer in which defocus can be observed extends by more than 3mm to both sides of the step. In the same area a degradation of imaging fidelity can be observed in the form of exaggerated proximity effects.

Process Bias is traditionally defined as a manufactured offset of the mask-features that induces a photoresist image size to more closely match the nominal or desired circuit design size. The metric is calculated as the difference between the size of the image on the wafer and the mask with image reduction taken into consideration. Optical process corrections (OPC) in the mask design must consider not only the Bias but also the influence of aerial image artifacts such as near-neighbor proximity, polarization and birefringence. The interactions are further complicated by the wavefront's interaction with the imaging media and optical interactions with the translucent film stack on the wafer. With the increased frequency of resolution enhancement (RET) artifacts on the mask, the concept of Bias as a simple scalar becomes less clear. In this study Bias is shown to exhibit the anticipated systematic response to all of the static exposure conditions of the process. Variations across each field-of-exposure however behave nonlinearly with the range of fluctuations encountered within the process-space experienced during device manufacture. A model is developed that allows the Bias response to be comparatively measured for each mask feature-design that characterizes not only the behavior at optimum exposure but also each features stability across process and imaging perturbation sources. The Bias models are applied to profile metrology gathered from matrix exposure data. Fine-structure perturbations in the Bias are extracted comparing their relative variation to process fluctuations that in-turn illustrates a strong individual feature construction-sensitivity. This analysis suggests that individual feature design is a strong contributor to process-stability of a reticle. Even more significant, the Static Bias variation across the exposure field of a reticle is shown to be inversely related to the dose-uniformity map needed to achieve uniform critical features at the process-target size. A new metric is introduced to provide a means of modeling the non-linear local Bias Signature for IntraField feature perturbations as a measure of the Bias Error Enhancement Function (BEEF). The BEEF metric is shown to be relatively insensitive to variations in the manufacturing exposure process-space but strongly responsive to variations in critical feature manufacture or design. The model is then extrapolated to define the relationship between Bias Response and the Mask Error Enhancement Function (MEEF). The base design of a photomask feature is shown to be a strong contributor not only to resolution and depth-of-focus but also to the robustness of image response or it's ability to maintain stable resolution and depth of focus across the process-space. The Proper selection of different feature design alternatives can greatly reduce photomask sensitivity to process variations. The selection process for these designs as well as new reticle validation is simplified using the BEEF metric as an evaluator. "BEEF" is a metric more closely tied to process response of a reticle design than MEEF and is more easily extracted from in-process raw metrology.

The resist blur due to photoacid diffusion is a significant issue for 45-nm half-pitch node and beyond. Furthermore, it has been generally recognized that there is a trade-off between resist resolution and sensitivity. In this paper, we study the influence of the resist blur on resolution and sensitivity in hyper-numerical aperture ArF immersion lithography by utilizing a two-beam interferometric exposure tool. We evaluated the current photoresist performance for some of the latest commercial resists, and estimated their acid diffusion lengths as 8 to 9 nm in sigma assuming Gaussian blur kernel. In addition, we found that the acid diffusion length, that is, the resist resolution was controllable by PAG anion size, polymer resin size, and PEB temperature. We also found that there was the trade-off between resist resolution and sensitivity. Our results indicated that the resist blur is still a concern in order to extend ArF lithography for 45-nm half-pitch node and beyond, however, it will not likely be a showstopper. We consider that total optimization of resists and exposure tools is important in order to achieve ultimate resolution in hyper-NA immersion lithography.

Some practical aspects of integrating a mask modeling solution into the Optical Proximity Correction (OPC) framework are discussed. Specifically, investigations were performed to understand to what degree empirical process models used in OPC can compensate for mask effects when a Kirchhoff mask model is used. It is shown that both Constant Threshold Resist (CTR) models as well as more complex variable threshold process models can both compensate for mask effects at a single plane of focus. However, when looking through process window, neither process model can predict the focal behavior of Electro-Magnetic Field (EMF) simulators. The impact of mask effects will therefore need to be modeled in OPC, since process models cannot fully compensate for their effects. Heuristic approaches to modeling mask effects, like a constant biasing of feature edges, are then investigated and compared to more complex mask modeling solutions like Domain Decomposition Methods (DDM). It is shown that these heuristic approaches can be effective at single planes of focus to partially mitigate mask effects, however, do not provide complete solutions to predict and compensate for mask effects. DDM stands in stark contrast to heuristic methods, correctly predicting the through focus behavior of EMF simulations for the tested pitches and CDs. The impact of optical diameter (periodic boundary conditions) is also investigated to understand how the introduction of mask periodicity effects from optical diameter degrades the benefits derived from mask modeling. It is shown that as much as a 33% reduction in CD predictability is observed from an optical model with a 1um optical diameter compared to a 2.56um optical diameter. Finally, both a Kirchhoff mask model and a DDM mask model are compared to see which mask model more accurately explains experimental CD measurement data from a 65nm process. The DDM model generally reduces the edge placement error (EPE) on the calibrated focal data by 0.3-1.0nm.

A multi-student testchip aimed at characterizing lithography related variations with over 15,000 individually probable test structures and transistors has been designed and a complementary 65nm process flow and data aggregation strategy have also been implemented. Test structures have been strategically designed to have high sensitivities to non-idealities such as defocus, LWR, misalignment and other systematic sources of variation. To enable automated measurement of massive amounts of test structures, Enhanced Transistor Electrical CD (Critical Dimension) metrology has been used as it offers high pattern density and almost no geometrical restrictions. Electrical testing at cryogenic temperatures will be employed to study the impact of Line Width Roughness (LWR) versus Random Dopant Fluctuations (RDF), which will not play a significant role at cryogenic temperatures, 4K. To facilitate data analysis and comparison of results between students, a relational database has been designed and implemented. The database will be web accessible for each student to use and update. It will serve as a collaborative platform for reinforcing conclusions, filtering out confounding data, and involving outside parties that are interested in process variations at the 65nm node. Experimental data was not available at the time this paper was written, so this paper will concentrate on the design and simulation results of test structures.

We propose to use a starburst pattern as a powerful diagnostic tool in optical lithography. A starburst pattern of constant line/pitch ratio versus radius can be used as a quick diagnostic tool for various off-axis illumination techniques, in particular those that have non-isotropic illumination shapes. Because such a starburst features a multitude of pitches at a multitude of angles, a large area of the pupil is sampled. Careful analysis of the image of the starburst gives information on the kind of illumination that is used, the resolution limit for all angles, and can be used to find the best focus position. We perform an analysis of the characteristic regions of a starburst image for a given illumination and interpret the images accordingly. Aerial image simulations of the starburst patterns are analyzed and compared to the experimental results.

According to the ITRS Roadmap, for 45nm Node (as 65nm Half Pitch), the requirement of Gate CD Control is defined as 2.6nm. One of the most challenging CD errors is Iso-Dense Bias (IDB). Assuming 40% of CD errors are dominated by IDB, IDB should be less than 1nm. In general, the majority of IDB is due to: primarily, exposure tool- related factors such as aberrations, flare, and sigma fluctuation, and secondly, the change in photoresist characteristics. However, due to the rapidly increasing usage of ArF exposure tools, Band Width (BW) characteristics of the laser source is an additional factor whose contribution is becoming more critical. Ideally, BW is monochromatic, thereby not affected by chromatic aberration change. However, in reality, the BW exhibits a shape of spectral distribution with a finite width. This study describes experimental and simulation results for E95%, and how performance of both CDs and Laser is dependent on E95% in order to meet 1nm of IDB towards 45nm Node. -IDB vs. E95% -CD at through pitch vs. E95% -Process Latitude vs. E95% -DOF -EL -Pattern shortening vs. E95%

As critical dimensions (CDs) approach (lambda) /two, the use of optical proximity correction (OPC) relies heavily on the ability of the mask vendor to resolve the OPC structures consistently. When an OPC model is generated the reticle and wafer-processing errors are merged, quantified, and fit to a theoretical model. The effectiveness of the OPC model depends greatly on model fit and therefore consistency in the reticle and wafer processing. Variations in either process can 'break' the model resulting in the wrong corrections being applied. Reticle manufacturing variables that effect OPC models are exposure tool resolution, etch process effects, and process push (pre-bias of the fractured data). Most of the errors from these reticle-manufacturing variables are seen during model generation, but there are some regions that are not, and fail to be accounted for such as extremes in the line ends. Since these extreme regions of the mask containing the OPC have a higher mask error enhancement factor (MEEF) than that of the rest of the mask, controlling mask-induced variables is even more important. The phase shift mask (PSM) is one of the most effective approaches to improve ArF lithography performance. MoSi or SiON dry etching technology play an important role to fabricate phase shift masks, such as space bias type Alternating (Alt.) PSM and chrome-less phase shift masks (CPL). The profile of the etched quartz affects the lithography performance. In this paper we evaluate the nominal influences of the MoSi or SiON profiles on pattering and OPC by rigorous electromagnetic field simulations. The influence of the MoSi or SiON profile is investigated by evaluating imaginary masks. In this experiment, we simulated attenuated PSMs with tapered sidewalls, high round and micro-trenches of varying depths. OPC modeling performances of the imaginary masks are measured by the OPC print image CD and model fitting results. I compare the result of print image CD with simulation. I investigate how well the OPC print image CD measurement corresponds to the simulation. Mask CD error and sidewall angle strongly affect the OPC modeling performance. However, micro-trench does not affect the OPC performance. This paper quantifies the effects reticle processing has on the OPC model generation, and also mask CD variations and variable sidewall angles affect the OPC print image CD and OPC model fitting for attenuated PSMs, micro trench depth does not play an important role for OPC print image CD and OPC model fitting.

All OPC model builders are in search of a physically realistic model that is adequately calibrated and contains the information that can be used for process predictions and analysis of a given process. But there still are some unknown physics in the process and wafer data sets are not perfect. Most cases even using the average values of different empirical data sets will still take inaccurate measurements into the model fitting process, which makes the fitting process more time consuming and also may cause losing convergence and stability. The Image quality is one of the most worrisome obstacles faced by next-generation lithography. Nowadays, considerable effort is devoted to enhance the contrast, as well as understanding its impact on devices. It is a persistent problem for 193nm micro-lithography and will carry us for at least three generations, culminating with immersion lithography. This work is to weight different wafer data points with a weighting function. The weighting function is dependent on the Normal image log slope (NILS), which can reflect the image quality. Using this approach, we can filter wrong information of the process and make the OPC model more accurate. CalibreWorkbench is the platform we used in this study, which has been proven to have an excellent performance on 0.13um, 90nm and 65nm production and development models setup. Leveraging its automatic optical-tuning function, we practiced the best weighting approach to achieve the most efficient and convergent tuning flow.

Control of Isolated and Dense line Bias (IDB) and Line End Shortening (LES) in a lithographic process has become increasingly important, particularly for the 65nm node and below. The IDB depends on many factors, for example, focus, lens aberrations, partial coherence and laser spectral bandwidth. This work studies the impact to IDB and LES from changes in laser bandwidth at two sub-micron process nodes. Careful measurements of both FWHM and E95 bandwidth parameters of the laser spectral profile were carried out using two types of spectrometers. The spectral bandwidth was adjusted over a larger range than normally experienced during wafer exposures by carefully varying the laser operating conditions to provide controlled changes in bandwidth while maintaining all other laser performance parameters within specification. Measurements of both linewidth and LES on several substrates were made and correlated with laser bandwidth to determine the sensitivity of IDB and LES to bandwidth variation. The sensitivity of different structures to E95 bandwidth variation was assessed

In-situ aberration measurement often requires indirect methods that retrieve the pupil phase from the measured images and presents unique challenges to the engineers involved. Phase wheel monitor allows such in-situ measurement of aberrations in photolithography systems. The projection lens aberrations may be obtained with high accuracy from images of phase wheel targets printed in photoresist. As a result, the photolithography tool optics can be characterized under standard wafer printing conditions. Resulting features are mathematically analyzed to extract information about the aberrations in optics. We use a detection algorithm and multi-domain modeling to process resist images and determine the image deviation from the ideal shape, which in turn allow the amount of aberration introduced by the optical system to be quantified. Experimental results are shown and multiple measurements on the same tool before and after system corrections are compared.

193nm immersion lithography has successfully enabled numerical aperture (NA) greater than 1.0 which allows rooms for improvement in resolution as well as depth of focus. In this study, critical dimension (CD) and depth of focus (DOF) performance for the 45nm technology node for dry and immersion lithography is compared using commercial available simulation tool. The study is based on one dimensional line and space pattern with pitch vary from 150 to 500nm. The effects of mask transmission and phase angle change on CD through pitch performance and DOF are also presented in this paper. Increase in mask transmission will result in increase of CD through pitch and reduction of DOF. When phase angle for the phase shift mask is less than 180 degree, CD through pitch and DOF drop. Finally, mask defects caused by haze on several locations which include MoSi lines, line edges, and space between line ends are simulated. The influence of these defects on CD and the potential line end bridging problem is presented.

Horizontal-Vertical (H-V) bias is the systematic difference in linewidth between closely located horizontally and vertically oriented resist features that, other than orientation, should be identical. There are two major causes of H-V bias: astigmatism, which causes an H-V bias that varies through focus, and illumination source errors such as telecentricity error. In this paper, the effects of simple dipole source errors upon H-V bias and placement error through focus are explored through simulation.

A novel process of OPC-free on-grid fine random hole pattern formation is developed. Any random hole pattern with ~120nm diameter on 240 nm base grid can be printed by KrF exposure. In this technique, double resist patterning scheme is adopted. Dense hole pattern is delineated with first resist process. Quadrupole illumination is applied with embedded attenuating phase shift mask (EA-PSM) in imaging on this step. As is well known, fine dense hole pattern is formed with very large process latitude. After development of the first resist, hardening of the resist film by Ar ion implantation is carried out so as not to mix with second resist at second coating. This hardening process is very robust such that rework in second resist process can be performed with stripping the resist by a solvent. Then, second resist patterning is carried out. In the second exposure, cross-pole illumination is applied with high transmission EA-PSM. By this imaging, very fine dark spot image is generated. Resultantly, fine random pillar patterns, which plug an underlying hole, are formed in the second resist film. Because function of the pillar is plugging a hole, no precise CD control is required. Moreover, pattern connection between adjacent pillars does not cause any problem. Hence, no OPC is needed in the pillar formation, regardless of printed size variation of the pillars. Undesired holes in the dense holes are plugged by the pillars. As a result of the double resist patterning, on-grid random hole pattern is successfully delineated. Due to the robustness of each patterning process, very high process latitude is achieved. Off course, this technique can be carried out under any wavelength on regard of imaging. In other aspect, this technique utilizes only positive-tone resist. Hence, this technique can be applied with leading-edge ArF immersion lithography. As a conclusion, this technique is a promising candidate of hole pattern formation in 32nm era and beyond.

Virtual OPC concept is suggested for soothing the problem that the roadmap of semiconductor devices proceeds the rate of development of exposure tools. Virtual OPC uses the simulated CD data for an OPC modeling instead of the measured CD data. For successful virtual OPC, the extreme accuracy of the simulation is required for obtaining the simulated CD data close to the actual CD values. In this paper, our efforts to enhance the simulation accuracy are presented and the accuracy of simulated sample data for OPC is verified. The applicability of virtual OPC to the production of devices was verified by performing the virtual OPC using the simulated sample data at 1.2 NA lithography and the result also is presented.

In this work, the reduction of the shot count of the mask data is studied. This shot count reduction is achieved by reducing of the number of jogs resulting from the Model-Based Optical Proximity Correction (MBOPC) stage. To reduce the number of OPC-jogs, we study the impact of aligning very small jogs on the shot count as well as their effect on the residual Edge Placement Error (EPE). The OPC-jog alignment phase is made during OPC and not after it, so that the post alignment OPC iterations are responsible for the correction of any residual average EPE resulting from the jogs alignment. The results of this approach show a reduction of the total shot count in the mask fabrication stage by 18%, while the EPE distribution is still almost the same compared to the standard OPC approach, promising for a nice enhancement in the OPC flow to be more fracture friendly expected to decrease the data size of the fracturing, the mask writing time as well as the mask costs.

With the increasing complexity of design and the shrinking of technology nodes, optical proximity correction has become an integral part of IC fabrication. Pattern fidelity is the baseline for any accurate OPC model. Calibrated process models are used to make iterative pattern adjustments over a fragmented design to align simulated images and the target layout. More and more advanced modeling techniques are deployed for accurate prediction of complicated 1D and 2D structures. As such, more aggressive layout situations must be taken into consideration for different process and OPC aspects such as optimization of process window, contrast, MEEF, OPC convergence, and many more. However along with different process optimizations, the mask complexity increases and the OPC run-time is also adversely affected. Often, it has been noticed that the OPC model accuracy is restricted by long OPC run-times. The variation in OPC runtime could be due to many factors, including number of finitely sized segments, multiple iterations of edge movements & simulations, convergence, multiple process conditions, step size, sitelength, model complexity, etc. Integration of fast and accurate analysis is needed to address the growing complexity of OPC solutions. We present here different approaches for OPC run-time improvement. A methodology is prepared to investigate accurate OPC models with fast runtimes. Additionally, proper selection of fragmentation, simulation sitelength, and number of iterations can be modified to achieve significant improvement in computation speed. The variation in run-time is assessed for different approaches listed above with an emphasis on OPC accuracy. Statistical analysis is used to measure image parameters and edge placement errors (EPE) for various experiments and the output is the measurement and plotting of accuracy versus run-time. This paper will present those results and suggest best practices for OPC run-time improvement that can be incorporated as a part of an OPC model building and OPC qualification flow.

The super-sensitivity of wafer critical dimensions (CDs) to mask CDs at low k₁, known as the Mask Error Enhancement Factor (MEEF) drives the need for increasingly tighter mask CD control. In addition, the accuracy of the model based optical proximity correction (OPC) used to compensate systematic lithographic errors is partially dependent on a stable mask CD error signature that expands mask CD control requirements over multiple feature types. This paper presents the need for improved quantification and monitoring of mask CD signatures that includes CD characteristics relevant to OPC model calibration. It also introduces and discusses a new method to characterize, quantify, and control mask signatures in a mask manufacturing environment to limit the impact of mask CD variations on the OPC model validity. Multiple approaches to implementing this "golden curve" method are discussed in terms of their advantages and disadvantages.

State of the art lithography is continually driven to resolve increasingly smaller features, forcing k₁ values for lithography processes ever lower. In order to image these difficult features with reliable fidelity, lithographers must increasingly use Resolution Enhancement Techniques (RETs). One such technique that is proposed in this paper uses small, sub-wavelength grooves placed in close proximity to an aperture. These sub-wavelength grooves create evanescent fields bound to the surface between the absorber and the mask substrate, decaying exponentially in lateral directions. In this work we demonstrate the ability to use such Evanescent Wave Assist Features (EWAFs) to enhance the propagating near and far field energy within openings such as slits and contacts. Using a Finite Difference Time Domain model, the effects of these evanescent wave assist features are explored in both the near and far field regions. Several cases of absorber material, feature type, spacing, and illumination will be presented.

As the minimum pitch size becomes smaller, the gate-poly critical dimension uniformity (CDU) is a critical parameter for the device performance and an important indicator of the OPC capability. From the photolithographic point of view, the root causes of increasing gate-poly CDU is due to corner rounding effects, ripples, misalignment between the gate-poly and active layers. The corner rounding effect of the gate-poly region on the active can be severe for the sub L50 device because the space between the active layer and the gate-poly layer becomes narrow. To correct these effects caused by litho-process the advanced OPC technique and the design rule limitation should be optimized. The OPC method which can be used to improve gate-poly CDU is defined as "Litho Process-aware OPC for the Gate-Poly CDU improvement" in this paper. The pixel based simulation algorithm which gives lots of information compared to the sparse simulation algorithm is used for the OPC and ORC. The design rule for the space limitation from RX to PC is evaluated with its own litho-process model and this evaluation result has to be reflected to the design rule and the OPC recipe to manipulate the polygons is also necessary. Additionally if misalignment exists in the minimum space between the active layer and gate-poly layer during the photo process, this corner rounding effect can be more serious, so this misalignment accounted to reduce the corner rounding effect on the gate-poly CDU. The redundant field poly polygon enclosing the contact can be cut by keeping the design rule for the overlap margin between the poly layer and the contact layer. The miss-alignment effect can be considered indirectly by sizing the active layer. The OPC convergence technique is also used to reduce the ripple phenomenon close to the concave corner and line end. As a result of retargeting to accommodate a corner rounding effects, ripple effects and misalignment correction led to an improved gate-poly CDU for a sub-50nm device.

We present description of the Compact Model 1 (CM1) resist model designed for use in OPC and OPC verification. We discuss model formulation and compare model predictions to the resist measurements. We propose to use CM1 model as a standard pattern transfer model during chip-scale process simulations.

Modular OPC modeling, describing mask, optics, resist and etch processes separately is an approach to keep efforts for OPC manageable. By exchanging single modules of a modular OPC model, a fast response to process changes during process development is possible. At the same time efforts can be reduced, since only single modular process steps have to be re-characterized as input for OPC modeling as the process is adjusted and optimized. Commercially available OPC tools for full chip processing typically make use of semi-empirical models. The goal of our work is to investigate to what extent these OPC tools can be applied for modeling of single process steps as separate modules. For an advanced gate level process we analyze the modeling accuracy over different process conditions (focus and dose) when combining models for each process step - optics, resist and etch - for differing single processes to a model describing the total process.

Yield is one of the most important factors for massive semiconductor circuits production. As process variation tolerances decrease and the number of contacts/vias increase in modern technologies, contact/via failure has increased substantially, which attracts many attentions from both manufacture and design domains. Among all the contact/via failure mechanisms, lithography related ones become more important, the majority of which are rooted in focus and dose variations. Since the lithography image robustness is pattern dependent, conventional design rules are becoming less efficient and effective to convey the information. Models should be established to facilitate the evaluation of the lithography pattern robustness. Meanwhile, the models need to be fast enough to be used in design tools. Since Optical Proximity Correction (OPC) is very expensive to apply, the metric should be computed without doing actual OPC. We develop two new pre-OPC metrics to predict the post-OPC contact/via CD error due to focus variation, which are validated by our simulations. However, the metric for the post-OPC contact/via CD error due to dose variation is found not correlated well to the actual simulation. Further investigation is needed to increase the metric accuracy.

The challenges of ever-smaller CD (Critical Dimension) budget for advanced memory product requires tight ACLV (Across-Chip Line-width Variation) control. In addition to the lithographic MOPC (Model-based Optical Proximity Correction) for DCD (photo CD) control, the process correction for etch proximity effect can no longer be ignored. To meet on our requirement on final CD accuracy for critical layer, a set of test pattern, that represents memory array in one of our critical layers, has been generated for both photo and etch process characterizations. Through the combination of different pattern-coverage areas in the test mask and wafer map design, various local (chip-level) pattern densities of 40%~70% and global (wafer-level) pattern densities of 35%~65% were achieved for optical and etch proximity study. The key contributors to the process proximity effect were identified and voluminous data has been extracted from the memory block like patterns for statistical analysis. The photo and etch proximity effects were hence modeled as function of memory block separation, local pattern density as well as global pattern density. Finally, the respective photo and etch proximity effects through model-based proximity correction and rule-based proximity correction were applied in a multi-step flow to products.

OPC has become an indispensable tool used in deep sub-wavelength lithograph process enabling highly accurate CD (Critical Dimension) control as design rule shrinks. Rule based OPC was widely acceptable in the past, however it has recently turned toward model OPC according to the decreasing pattern size. Model based correction was first applied to the optical proximity phenomenon because the image of sub-wavelength pattern is distorted severely during the optical image transformation. In addition, more tight CD control required to compensate the process induced error effects from etch or other process as well optical image can be achieved. In this paper, we propose advanced OPC method to obtain better accuracy on the final target for sub-90nm technology. This advanced method converts measured CD data into final CD target by using an equation. We compared the results from the data converting method, suggested in this paper, with those from post-litho(DI), post-etch (FI) OPC model step by step. Finally we confirmed that advanced new OPC method gives better accuracy than that from conventional OPC model

Recently, photolithography process is facing many difficulties in patterning the circuit adequately, mainly due to the rapid decrease of the k1 factor. The limitation of numerical aperture (NA) causes the distortion of printed patterns, such as corner rounding, line end shortening, and the different bias between isolated and dense figures. The optical proximity effect correction (OPC) is the most popular method to solve this problem. Especially, we should apply the model-based OPC to the critical layers as the circuit patterns get smaller and more complex. The success of model-based OPC largely depends on the quality of the model, which describes the physics in the resist under a specific optical condition. A "good" model should have both the low fitting error and the full chip coverage. Efforts to lower the fitting error can lead to the degradation of physical meaning, and this would result in insufficient coverage of the model. To settle this concern, we should extract test patterns for model calibration that cover all the aerial image properties of full chip geometry. The investigation for selecting the data set for optical model tuning is also necessary to prevent the final model to be over fitted. In this paper, we will present test pattern selection strategy for optical model, and resist model.

In modern photolithography, the dose latitude, Normalized Image Log Slope (NILS), and hence the image quality are closely related to the gradient of the aerial image intensity at the evaluation point. The placement of sub-resolution assist feature (SRAF) in isolated lines helps improve the aerial image quality by increasing the gradient. Traditionally, it is simple and straightforward to calculate the effect of the SRAF placement on the gradient at a certain evaluation point. The gradients before and after the SRAF placement are computed separately. The difference between these two gradients indicates the magnitude of the effect. However, this simple methodology is only convenient when the location of the SRAF placement is known. In addition, this methodology is not adaptable to searching for the optimum placement, as many potential placements need to be evaluated. In this report, an innovative and rapid solution for SRAF placement is presented. The methodology output indicates the optimal location for the SRAF placement to increase the gradient of the aerial image is about 210 nm from the drawn edge of the iso-line and is independent of the iso-line structure for an annular illumination system. The results are verified by measuring the gradient difference with an independent tool.

The correction accuracy of a model-based OPC (MB-OPC) depends critically on its edge offset calculation scheme. In a normal MB-OPC algorithm, only the impact of the current edge is considered in calculating each edge offset. As the k1 process factor decreases and design complexity increases, however, the interaction between the edge segments becomes much larger. As a result, the normal MB-OPC algorithm may not always converge or converge slowly. Controlling the EPE is thus become harder. To address this issue, a new kind of MB-OPC algorithm based on MEEF matrix was introduced which is also called matrix OPC. In this paper, a variant of such matrix OPC algorithm is proposed which is suitable for kernel-based lithography models. Comparing with that based on MEEF matrix, this algorithm requires less computation in matrix construction. Sparsity control scheme and RT reuse scheme are also used to make the correction speed be close to a normal one while keeping its advantages on EPE control.

Standard Model Based OPC is based on resist and after etch CD measurements. In the case of non-linear photo-etch bias due to the etch microloading effect two-dimensional configuration can be wrongly corrected by the OPC model and hence lead to possible Si bridging. This paper reports a geometrical model for the determination of potential bridging in silicon trench structures that depends on the proximity of neighboring features. The model shows a possibility to detect and correct the post OPC data base by taking into account the non-linear effect caused by the non linear etch microloading. This approach can at the end leave the OPC model with a more straightforward photo resist model (and prevent the need to recreate a new OPC model), awhile-adding additional step of correction just in the locations of killer effects like bridging may occur.

In the recent year tools for DFM (Design for Manufacturing) addressing the lithographic pattern transfer like LfD have evolved besides OPC (Optical Proximity Correction) to reduce the time required from design to manufacturing along the design to mask data preparation flow. The insertion of ORC (Optical Rule Check) after OPC in a separate mask data preparation step has been commonly adopted in order to successfully meet the ever increasing need of an advanced technology node like 130nm, 90nm, 65nm and below. Separate simulation runs are normally done for both OPC and ORC and it is not unusual that different platforms (software, hardware or algorithm) are used for OPC and ORC, especially for better ORC processing throughput. An investigation has been made to look into the possibility of a DFMlite approach by inserting ORC into the OPC run on the same Calibre platform. This is accomplished by adding additional intelligence necessary to provide a 'polishing' step for a hotspot identified, without increasing the combined cycle time but having the benefit of both full OPC and partial ORC in a single simulation run.

The upcoming 45nm device node is a point at which newer field-based (i.e., dense pixel-based) OPC simulation methods may begin to show advantages over sparse-sampling ("flash") simulation methods. Field-based simulation provides computational efficiencies in applications where a large number of model evaluation locations are needed, and where the simulated layout geometry is complex. Field-based simulation leverages computation in the frequency domain, whereas sparse-sampling methods operate in the space domain. Mathematically, both methods are equivalent but their respective numerical methods give rise to some implementation differences for OPC applications. These differences include different optimization strategies for hierarchical processing, and fine-grained feature symmetry control for critical matched-transistor circuits (such as SRAM, where noise margin is a fundamental device control issue). An optimum, field-based OPC solution will address these differences without compromising the performance benefits of field-based methods. In this paper we describe and compare the manufacturing implementation of flash-based and field-based OPC at the 45nm and 32nm device nodes

Since the beginning of the optical lithography simulation, the mask, though actually with limited thickness, is always considered as purely Two-Dimensional, or in other word, the mask thickness is infinitely small. This is always a good approximation for the real mask when the critical dimension is relative large and the Numerical Aperture of the optical imaging system is smaller than 0.7, for, the image distortion induced by the mask thickness and profile under such situation is negligible. Even adopting infinite thin mask approximation described by Kirchoff approach, accurate simulation results can be achieved. However, for higher NA microlithography process, the polarization of the illumination light and the profile of the mask become important factor that will be reflected in the final image formation. Thus, the infinite thin mask approximation will have larger deviation from real world process with the technology goes into 65nm node and beyond. To describe the 3D mask effect exactly, Maxwell electric-magnetic filed equations should be adopted. However, to solve the Maxwell equations mathematically is obviously a horrible work, since the pattern on the mask can be extremely complicated. Fortunately, there are still a lot of algorithms through which numerical results of the Maxwell equations can be achieved. We have developed a tool based on the Finite-difference time-domain method (FDTD), which is developed by K. S. Yee in 1966. Second-order approximation of Mur’s absorbing boundary condition is used to enhance the convergence of the calculation. We here will demonstrate some simulation results given by our tool, including how the profile (footing, undercutting and so on) of the mask affects the final image formed on wafer level and the comparison of the results given by Kirchoff approach and FDTD approach. Brief summary will also given for the 3D Mask Effect in the image formation.

As the industry transitions to the 45 nm node and beyond, requirements for critical dimension (CD) control are getting extremely aggressive. Current 45 nm node specifications call for 2 nm or better CD uniformity (CDU) on the gate level. For critical dimension control in this regime all measurable process effects must be closely monitored and controlled. This includes such effects as etch uniformity, scanner dose and focus consistency, post-exposure bake (PEB) plate uniformity, and incoming wafer variation such as wafer warpage. The problem is that as the number of significant contributors to CDU continues to increase; the number of parameters that can be used to control CDU has not. To better understand how to achieve these increasingly stringent CDU targets, the authors have explored how exposure and resist processing effects CD control. The goal of this work is to simulate how process parameters such as dose and PEB temperature can be used to effectively control CD, while minimizing unintended negative effects on thru pitch CD performance, MEEF, and other lithography process metrics. In addition to traditional lithography metrics, the effect these process changes have on CDU is simulated using a Monte Carlo technique.

In this paper we have analyzed the ACLV performance of a 45nm CMOS logic process as a function of gate layer exposure tool. Data from identical masks and with identical litho processes is compared side by side on immersion and dry lithography. Theoretically, the improved focus control of immersion scanners allows tighter CD control for pitches that have lower process windows. Thereby, the ACLV performance of immersion lithography is expected to be better than on a comparable dry tool, when keeping all other parameters the same. This is specifically important for foundry processes where pitches are not restricted. The wafer results give somewhat ambivalent answers. Overall, ACLV performance of the dry tool is very similar to the immersion tool. Taking out systematic contributions, it becomes evident that the ACLV is dominated by dose effects and less by the curvature of the Bossung plots. Even though the focus window is considerably smaller on the dry tool, the apparently better dose control leads to better ACLV performance after subtracting systematic effects.

As semiconductor process technology moves to 65nm and beyond, RET (resolution enhancement technology) becomes more and more important, especially in low k1 processes, where it is used frequently. Currently, in the 65nm generation, the k1 is ~0.4 on a 0.85 NA exposure tool. However, the NA improvement of the exposure tool cannot meet the schedule of generation movement very well. Low k1 technology must be applied on next generation processes. For the 45nm generation, a 0.93 NA exposure tool is available currently and is used to achieve the production criteria. Because the k1 value is quite low (~0.31), using traditional methods cannot satisfy process requirements. For metal layers of the 45nm generation, 55nm photo-resist CD (critical dimension) patterning of 130nm pitch is a difficult goal on a 0.93 NA exposure tool. Traditional OAI (off-axis-llumination) (annular mode) cannot provide enough image contrast for pattern printing. Customization of illumination mode is an approach on low k1 processes. Another one is utilizing light source polarization to achieve resolution improvement. In this paper, we introduce different approaches on 45nm metal patterning. The RET approach (C-quad. illumination mode with polarization) can provide enough image contrast in pattern printing to solve process issues.

Presented here is an analysis of photoresist profile and feature control performance for high-energy well implant lithography as it is implemented in microelectronic devices, specifically SRAMs, at the 45 and 65nm nodes. As device designs become increasingly smaller to the tune of Moore's Law, deep well implant lithography specifications become more and more stringent, and issues related to lateral implant scattering that were more trivial for more relaxed designs begin to make significant contributions to photoresist feature uniformity and implant profile control. Simplified process assumptions that overlook such non-ideal implant phenomena can result in an overestimation of process latitude. Undesirable variability derived from the implantation, lithography, and substrate associated with a deep well formation process can degrade implantation profiles and have adverse effects on device electrical performance. Mechanisms for these adverse effects such as implant scattering and implant straggle will be explored followed by their relationships to process tolerance and electrical performance. Emphasis will be placed on evaluating the optimum photoresist feature profile for a given process and determining its true process latitude as opposed to "centering" a feature in a device layout during design. Finally, challenges confronting process control methods for high-aspect ratio implant mask features will be discussed followed by some proposed process improvement suggestions.

In order to minimize manufacturing costs, lithographers have to extend the capabilities of KrF and i-line tools working with low k1 factor. In this paper we present results of a successful transfer of several lithographic processes from KrF to i-line. During the process transfer, the optimal conditions for 365-nm technology were first determined by simulation and then verified by exposure of real production layers on a 0.65 NA i-line tool. The goal of the process optimization was to find settings for 365-nm process, which can match the performance of the 248-nm process. Proximity matching, CD uniformity, tool throughput and process costs were chosen as the main criteria for successful transfer. Encountered challenges, the applied methodology and the experimental results have been discussed. Based on the results, we conclude that low k1 i-line lithography is feasible for mass production with CD as small as 210 nm. The process does not require additional preparation for 248-nm masks.

A new alignment mark implementation for color processing has been successfully tested in a joint activity between ASML and TOWER. Alignability and overlay performance have been proven by applying the combination of a pure high order mark design and a dual implementation using the ATHENA^TM alignment sensor and a PAS5500/400 machine. By their very nature, the resists used in color filter processes will absorb light at various wavelengths. While this makes them useful as color filters, it can noticeably reduce the signal strength of pattern images as seen by lithography alignment systems. The pure high order mark design enhances the signal strength. Exposing two of such mark pairs in a Metal Last layer with two different metal plateaus (in previous metal layers: "Metal Last - 1" and "Metal Last -2") leads to two different optical mark depths and therefore mimics a four wavelength alignment system with ATHENA. In principle, the evaluated technique might be extended to more (than four) "wavelengths" as well as other process layers. Moreover, the use of scribe-line marks enhances productivity since no extra lithography step is required to expose Zero Layers. The performance of this implementation has been evaluated for 180-nm CMOS Image Sensor technology. This paper discusses the overlay and alignment results of the evaluation. Alignment parameters such as absolute signal strength and signal strength variation were studied in detail. It is shown that such mark implementation shows good alignability and easily meets the product overlay requirements of Image Sensor devices.

A thin FinFET bulk Si-fin body structure has been successfully fabricated upon bulk-Si wafers through using 193nm scanner lithography and a composite hard mask etching technique. First, a 100Å-thick buffer SiO₂ layer was thermally grown upon the bulk silicon layer and subsequently a 1200Å-thick SiN_x layer and a 1000Å-thick TEOS SiO₂ hard mask layer was chemically vapor deposited to form a composite hard mask structure of buffer-SiO₂/SiN_x/TEOS. Second, both 1050Å-thick BARC and 2650Å-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the Si-fin body layout patterning under relatively high exposure energy. This achieves the ADI (after develop inspection) of 80nm from the original as-drawn Si-fin layout of 110nm. Then, a deep sub-micron plasma etcher was used for an aggressive P/R and BARC trimming down processing and both the capping TEOS and CVD-SiN_x with its underlying buffer oxide layers were subsequently etched in other etching plasma chambers, respectively. Resultantly, the AMI (after mask inspection) can reach 60nm. Subsequently, both the P/R and BARC were removed with a nominal plasma ashing as well as a RCA cleaning for the final sub-micron Si-fin plasma etching. Eventually, a 60nm-width and 400nm-height bulk Si-fin body structure can be successfully etched out after a fixed time-mode silicon plasma etching.

The merits of hyper NA imaging using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is clear. However, the challenge remains CD control at hyper NA and the development of ARC stacks to support not only lithographic response but also device integrations. Extreme off-axis illumination, polarization, and dense pitches of the C045 and C032 nodes show a significant degradation of reflection and CD control and a significant loss of resolution. Consequently, hyper NA patterning requires the development of a new ARC to improve the overall CD control. Thus, a single ARC layer could not ensure the reflectivity condition, and ARC stacks must now be decomposed into two or three components in order to suppress reflectivity through a wide range of incidence angle. In a previous work, we presented the advantage of using an antireflective based on CVD organic - inorganic stacks. This paper presents an upgrade of this type of stack, applied to 1.2NA imaging. We will show stack reflectivity simulations based on S-matrix approach. The capabilities of the CVD tools have been taken into account in the simulations in order to define a reflectivity process window. We will present 1.2NA lithography with different optimized ARC stacks, comparing potential capability and CD control in conjunction with the immersion lithography for 45 nm and 32 nm nodes.

A 100Å-thick SiGe (22.5%) channel MOSFET with gate length down to 40nm has been successfully integrated with 14Å nitrided gate oxide as well as a 1200Å high-compressive PECVD ILD-SiNx stressing layer as the contact etching stop layer (CESL) that enhances the PMOS electron mobility with +33% current gain. To achieve a poly-Si gate length target of 400Å (40nm), a 193nm scanner lithography and an aggressive oxide hard mask etching techniques were used. First, a 500Å-thick TEOS hard mask layer was deposited upon the 1500Å-thick poly-Si gate electrode. Second, both 1050Å-thick bottom anti-reflective coating (BARC) and 2650Å-thick photoresist (P/R) were coated and a 193nm scanner lithography tool was used for the gate layout patterning with nominal logic 90nm exposure energy. Then, a deep sub-micron plasma etcher was used for an aggressive P/R and BARC trimming down processing and the TEOS hard mask was subsequently plasma etched in another etching chamber without breaking the plasma etcher’s vacuum. Continuously, the P/R and BARC were removed with a plasma ashing and RCA cleaning. Moreover, the patterned Si-fin capping oxide can be further trimmed down with a diluted HF_(aq) solution (DHF) while rendering the RCA cleaning process and the remained TEOS hard mask is still thick enough for the subsequent poly-Si gate main etching. Finally, an ultra narrow poly-Si gate length of 40nm with promising PMOS drive current enhancement can be formed through a second poly-Si etching, which is above the underneath SiGe (22.5%) conduction channel as well as its upper 14Å-thick nitrided gate oxide.

As semiconductor technology moves toward and beyond the 65 nm lithography node, the importance of Optical Proximity Correction (OPC) models grows due to the lithographer's need to ensure high fidelity in the mask- to-silicon transfer. This, in turn, causes OPC model complexity to increase as NA increases and minimum feature size on the mask decreases. Subtle effects, that were considered insignificant, can no longer be ignored. Depending on the imaging system, three dimensional mask effects need to be included in OPC modeling. These effects can be used to improve model accuracy and to better predict the final process window. In this paper, the effects of 3D mask topology on process window are studied using several 45 nm node mask structure types. Simulations are conducted with and without a polarized illumination source. The benefits of using an advanced model algorithm, that comprehends 3D mask effects, will be discussed. To quantify the potential impact of this methodology, relative to current best known practices, all results are compared to those obtained from a model using a conventional thin film mask.

Strong resolution enhancement techniques (RETs) are highly demanded to overcome the resolution limit of sub-60nm lithography. ArF immersion lithography may be the best candidate for sub-60nm device patterning. However, the polarization effect becomes more prominent to degrade the image quality in high NA immersion lithography as the feature size shrinks. Therefore, it is important to understand the polarization effect in the mask. The induced polarization effect shows the different aspects between the binary and the attenuated phase shift mask (PSM). In this paper, we considered the effects of polarization state as a function of mask properties. We evaluated the performances of the binary mask and the attenuated PSM by using simulation, AIMS^TM (Aerial Image Measurement System) tool, and real wafer printing. We find out that there are no differences between the binary mask and the attenuated PSM in view of image contrast and mask error enhancement factor (MEEF).

In recent years, model-based OPC has been an essential technique to achieve better yield or even if resolution itself. Currently available OPC software employs optical simulation with thin-mask model or approximated model. However for 45nm-node and beyond, it is well-known that there is difference between 2D simulation by calculating thin-mask model and 3D rigorous simulation by calculating thick-mask model such as FDTD or RCWA. Especially, it is expected that larger incident angle of off-axis illumination and higher aspect ratio of mask topography lead larger differences between them. On the other hand, thick-mask model OPC consumes much computation time, so it will not be practical. The difference of these two simulation models is caused from the effect of mask topography and behavior of electromagnetic field on 3D rigorous simulation. The effect of mask topography also creates the difference of diffraction amplitude and phase at Fourier optics stage or imaging from diffraction. Then such diffraction orders with thin and thick-mask model was focused and evaluated at first approach. In this paper, the difference of diffraction orders' amplitude between two simulation models caused by illumination angle, mask materials is analyzed and then the difference of OPC bias for various pattern pitches is presented. Then from this result, the compensation methodology of the diffraction differences is discussed and simple compensation approach for OPC to improve the accuracy with thin-mask model's OPC is demonstrated. As a result, one new solution for OPC without additional computer time is proposed.

The progress of optical lithography has approached the sub-30 nm regime using 193nm excimer lasers as the exposure sources. To increase the numerical aperture (NA) further, many issues, especially those related to materials, need to be addressed. In this paper, we present the analytical and experimental results of oblique two-beam lithography with sapphire (Al₂O₃) as the optical material. At 193nm, the index of sapphire is 1.92 while the typical index of a photoresist is near 1.70. Classical theory predicts that, ignoring the absorbance in the photoresist, once the NA is greater than the photoresist refractive index, no energy will be transmitted across the sapphire/photoresist boundary due to total internal reflection. However, it can be shown that the absorbance in the resist prevents a "critical angle" and total internal reflection will not occur. Photoresist exposure can result even when NA is greater than the photoresist refractive index. The image profile is strongly affected by the real and imaginary parts of the photoresist refractive index. Optimization of photoresist optical properties is necessary for good image profile. Lutetium aluminum garnet (Lu₃Al₅O₁₂ or LuAG with an index 2.14 at 193 nm) is also investigated as an alternative lens material.

This paper reports the water-leakage mechanism of the immersion hood in an immersion scanner. The proposed static analysis reveals the immersion hood design performance in defect distribution. A dynamic water-leakage model traces the leaked water and identifies its position on the wafer, during exposure. Comparing simulation to experimental results on bare-silicon and resist-coated wafers, the defect type, source of residuals, and critical settings on the immersion system were clearly identified.

The rapid expansion in the number of semiconductor manufactures using immersion imaging systems confirms the acceptance of immersion lithography for critical layer imaging. One of the early concerns in the development of immersion lithography was defect levels. These defects levels have been dramatically reduced with each new system, and are now approaching defect levels similar to dry systems. Continued reduction of defects will be required as smaller critical dimensions are pursued on immersion systems with NAs well over one. In this work have studied new ways to further reduce the number of defects. For this investigation an ASML 1150i &agr;-immersion scanner was used for both ultra pure water soaking and for image exposure. Previous pre-exposure and post-exposure rinse/soak tests have been conducted on coater/developer tracks; however using the track causes a significant time delay from soak to exposure, and vice-versa. For this experimentation a dynamic soak of coated wafers immediately before exposure and immediately after exposure was performed on the immersion scanner with controlled soak times. The wafers were then processed as normal on a TEL-Lithius coater/developer track. Defect type and size were analyzed to determine the interactions which reduced defects. The findings showed that an immediate pre-exposure soak of 14 seconds reduced image expansion defects by 38%, compared to no pre-exposure soak. Test results also indicated that the most frequent defect, bridging, was not produced by water droplets.

The polarization characteristics of the state-of-art of optical lithography equipment are approximately ideal, i.e., in general only small polarization changes are induced by optical elements. Because of that, the polarization matrices of the optics are close to the unit element, which can be represented using the first canonical coordinate of a Lie group. The four-matrix basis of real general linear group of degree two is classified from a geometrical point of view. The complex versions of the four matrices are added to the four real matrices to obtain the basis of Lie ring of two-dimensional complex linear group, which is sufficient for physically possible polarization transformations. Each geometrical basis matrix generates non-Jones space of easy to understand individual optical phenomena. We propose a new physical polarization representation of projection optics for microlithography, which has eight real parameters, suitable for conventional pupil representation, with individual real optical characteristics applicable to optical elements. Pupil maps of a simulated projection lens whose polarization aberration and diattenuation induced by compensated intrinsic birefringence of CaF₂ lens elements, are shown using the representation.

In hyper NA system, specific illumination combined with polarization can be used as one of major RET techniques. Polarization at high NA dry system is also regarded as important technology to bring improvement of very low k1 process. The benefits of polarization on repeated structure are very well known. However we also need to understand the effect on random pattern in peripheral region to adopt polarization technology successfully into real devices. Memory device such as DRAM and NAND Flash has repeated cell structure and also loose pattern in peripheral region. In this study two kinds of polarization function will be applied to real memory devices and the polarization behavior on various patterns in peripheral circuit will be analyzed through actual printing process using 6% attenuated PSM at ArF high NA dry system. The printed result will be compared on random patterns through in-line metrology tool and process guideline including OPC treatment will be discussed based on this study, especially with regard to ID bias.