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Design-Process-Technology Co-optimization for Manufacturability XIII
Editor(s): Jason P. Cain
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Volume Details

Volume Number: 10962
Date Published: 17 June 2019

Table of Contents
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Front Matter: Volume 10962
Author(s): Proceedings of SPIE
Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet
Author(s): S. M. Yasser Sherazi; Miroslav Cupak; P. Weckx; O. Zografos; D. Jang; P. Debacker; D. Verkest; A. Mocuta; R. H. Kim; A. Spessot; J. Ryckaert
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Optimization of read and write performance of SRAMs for node 5nm and beyond
Author(s): Khaja Ahmad Shaik; Mohit Gupta; Pieter Weckx; Alessio Spessot
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A novel design-for-yield solution based on interconnect level layout improvements at 7nm technology node
Author(s): Jaehwan Kim; Sangah Lee; Byungchul Shin; J. Jeon; Jin Kim; B. M. Kim; Jae-Hyun Kang; Seungweon Paek; Piyush Pathak; Frank E. Gennari; Philippe Hurat; Ya-Chieh Lai
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Backside power delivery as a scaling knob for future systems
Author(s): Bharani Chava; Khaja Ahmad Shaik; Anne Jourdain; Sofiane Guissi; Pieter Weckx; Julien Ryckaert; Geert Van Der Plaas; Alessio Spessot; Eric Beyne; Anda Mocuta
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CFET standard-cell design down to 3Track height for node 3nm and below
Author(s): S. M. Y. Sherazi; J. K. Chae; P. Debacker; L. Matti; D. Verkest; A. Mocuta; R. H. Kim; A. Spessot; A. Dounde; J. Ryckaert
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Persistent homology analysis of complex high-dimensional layout configurations for IC physical designs
Author(s): Yacoub Kureh; Vito Dai; Luigi Capodieci
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Machine learning based wafer defect detection
Author(s): Yuansheng Ma; Feng Wang; Qian Xie; Le Hong; Joerg Mellmann; Yuyang Sun; Shao Wen Gao; Sonal Singh; Panneerselvam Venkatachalam; James Word
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Pattern-aware diagnostics: using high-performance pattern analysis to identify defect root cause (Conference Presentation)
Author(s): Jason P. Cain; Abdullah Yassine; Moutaz Fakhry; Piyush Pathak; Jeffrey E. Nelson; Frank Gennari; Ya-Chieh Lai
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Fast detection of largest repeating layout pattern
Author(s): Jingsong Chen; James Shiely; Evangeline F. Y. Young
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Process window-based feature and die failure rate prediction
Author(s): John Sturtevant; Lianghong Yin; Young Chang Kim; Shumay Shang; Andrew Burbine; Chris Clifford; Kostas Adam
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Applications of machine learning in EDA (Conference Presentation)
Author(s): Paul D. Franzon
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Optical proximity correction using bidirectional recurrent neural network (BRNN)
Author(s): Yonghwi Kwon; Youngsoo Song; Youngsoo Shin
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Investigation of machine learning for dual OPC and assist feature printing optimization
Author(s): Marco Guajardo; Yulu Chen; Peter Brooker; C.-E. Wu; Kevin Hooker; Folarin Latinwo; Kevin Lucas
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Using machine learning in the physical modeling of lithographic processes
Author(s): Kostas Adam; Shashidhara Ganjugunte; Clement Moyroud; Kostya Shchehlik; Michael Lam; Andrew Burbine; Germain Fenger; Yuri Granik
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Design for manufacturability for analog, radio frequency, and millimeter wave designs
Author(s): Lynn Wang; Gail Katzman; Yongfu Li; Vikas Mehrotra; Janam Bakshi; Ahmed Abdulghany; Michael Simcoe; Rais Huda; Zhao Chuan Lee; Don Blackwell; Thomas Hermann; Uwe Paul Schroeder; Thomas McKay; Sriram Madhavan
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3D resist reflow compact model for imagers microlens shape optimization
Author(s): Sébastien Bérard-Bergery; Jérôme Hazart; Jean-Baptiste Henry; Patrick Quéméré; Charlotte Beylier; Nacima Allouti; Maryline Cordeau; Raphaël Eleouet; Florian Tomaso; Alain Ostrovsky; Valérie Rousset
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Accuracy improvement of electrical characteristics estimation for sub-20nm FDSOI devices with non-rectangular gates
Author(s): Jia-Syun Cai; Sheng-Wei Chien; Xin-Yang Zheng; Chien-Lin Lee; Kuen-Yu Tsai
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Optimizing DFM scores by using a genetic evolution algorithm
Author(s): Uwe Paul Schroeder; Ahmed Shalabi; Janam Bakshi; Mohamed Ismail; Ahmed Mounir Elsemary
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Full-chip layout optimization for photo process window improvement of 3D NAND metal routing level
Author(s): Jennefir L. Digaum; Hung-Eil Kim; Eric Christensen; Hamilton Sanchez; Moydul Islam
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Critical defect detection, monitoring and fix through process integration engineering by using D2DB pattern monitor solution
Author(s): Ming Tian; Yu Zhang; Tiapeng Guan; Jianghua Leng; Baojun Zhao; Lei Yan; Wei Hua; Abhishek Vikram; Guojie Chen; Hui Wang; Gary Zhang; Wenkui Liao
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SAQP spacer merge and EUV self-aligned block decomposition at 28nm metal pitch on imec 7nm node
Author(s): Jae Uk Lee; Soo Han Choi; Yasser Sherazi; Ryan Ryoung Han Kim
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EUV computational lithography using accelerated topographic mask simulation
Author(s): Vitaly Domnenko; Bernd Küchler; Wolfgang Hoppe; Jürgen Preuninger; Ulrich Klostermann; Wolfgang Demmerle; Martin Bohn; Dietmar Krüger; Ryoung Ryoung Han Kim; Ling Ee Tan
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EUV mask synthesis with rigorous ILT for process window improvement
Author(s): Kyle Braam; Kosta Selinidis; Wolfgang Hoppe; Hongyuan Cai; Guangming Xiao
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Lithography hotspot candidate detection using coherence map
Author(s): Tetsuaki Matsunawa; Taiki Kimura; Shigeki Nojima
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CAPP: context analyzer and printability predictor
Author(s): Vikas Tripathi; Yongfu Li; I-Lun Tseng; Zhao Chuan Lee; Valerio Perez; Jonathan Ong; Shobhit Malik
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Hotspot detection using squish-net
Author(s): Haoyu Yang; Piyush Pathak; Frank Gennari; Ya-Chieh Lai; Bei Yu
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Multi-criteria hotspot detection using pattern classification
Author(s): Kazufumi Shiozawa; Taiki Kimura; Tetsuaki Matsunawa; Shigeki Nojima; Toshiya Kotani
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Multilayer CMP hotspot modeling through deep learning
Author(s): Luis Francisco; Rui Mao; Ushasree Katakamsetty; Piyush Verma; Robert Pack
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SALELE process from theory to fabrication
Author(s): Youssef Drissi; Werner Gillijns; Jae Uk Lee; Ryan Ryoung han Kim ; Ahmed Hamed-Fatehy; Rehab Kotb; Rajiv Naresh Sejpal; Germain Fenger; James Word
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Sample patterns extraction from layout automatically based on hierarchical cluster algorithm for lithography process optimization
Author(s): Tianyang Gai; Ying Chen; Pengzheng Gao; Xiaojing Su; Lisong Dong; Yajuan Su; Yayi Wei; Tianchun Ye
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Incorporating process variation contours in design rule calculation and SRAM design optimization
Author(s): Dongbing Shao; Jing Sha; Jinning Liu; Robert Wong
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Copper interconnect topography simulation in 3D NAND designs
Author(s): Yang Li; Rick Li; Peng Jiang; Luming Fan; Aman Zheng; Sicong Wang; Guangyi Wang; Zhengfang Liu; Chunshan Du; Ruben Ghulghazaryan; Qijian Wan; Xinyi Hu
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FEOL CMP modeling challenges and solution in 3D NAND
Author(s): Yang Li; Rick Li; Peng Jiang; Luming Fan; Aman Zheng; Sicong Wang; Guangyi Wang; Chunshan Du; Zhengfang Liu; Ruben Ghulghazaryan; Qijian Wan; Xinyi Hu
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Design rule exploration for width sensitive zone for metal layers in advanced nodes
Author(s): Xiaojing Su; Lisong Dong; Yayi Wei; Yajuan Su; Rui Chen; Chunshan Du
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Experimental study of the strong halation-effect of a fully PGMEA-based under-layer on a highly etched topography in the dual damascene via-first approach
Author(s): Valentina Dall'Asta; Emma Litterio; Nicoletta Corneo; Pietro Cantú
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An efficient way of automatic layout decomposition and pattern classification
Author(s): Zhenzhen Wan; Limei Liu; Huan Kan; Qijian Wan; Xinyi Hu; Zhengfang Liu; Chunshan Du
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A smart litho friendly design method to enable fast lithography hotspots detection in design flow
Author(s): Xiaolong Ma; Yanxiang Liu; Xinyi Hu; Qijian Wan; Zhengfang Liu; Chunshan Du; Liguo Zhang
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Machine learning to improve accuracy of fast lithographic hotspot detection
Author(s): NamJae Kim; Kiheung Park; Jiwon Oh; Sangwoo Jung; Sangah Lee; Jae-hyun Kang; Seung Weon Paek; Kareem Madkour; Wael ElManhawy; Aliaa Kabeel; Ahmed ElGhoroury; Marwa Shafee; Asmaa Rabie; Joe Kwan
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Novel pattern-centric solution for high performance 3D NAND VIA dishing metrology
Author(s): Sicong Wang; Jian Mi; Abhishek Vikram; Gao Xu; Guojie Cheng; Liming Zhang; Pan Liu
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