This PDF file contains the front matter associated with SPIE Proceedings Volume 10962 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

The targeted N3 technology node at IMEC is being redefined with respect to the poly pitch, as compared to the previous node definitions [1,2]. The overall industry trend of poly pitch scaling is slowing down, due to difficulties in keeping pace with device performance and yield issues. However, the metal pitch continues to scale down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore’s law. Here we present some of the options for the standard cell design that can enable an N3 technology node by using Design-Technology cooptimization (DTCO).

Scaled technology node, SRAMs suffer from increased Bit Line (BL) and Word Line (WL) resistance. To solve these issues, we present SRAM bit-level BL and WL metallization and options suitable for both SADP an EUV. We also present Buried power Rail (BPR) SRAM as enablers for high density SRAM cells (HD-111) in scaled technology nodes for 5nm and beyond and illustrate system level advantages of BPR SRAM with BPR based power delivery network of a hard macro like Arm 64-bit CPU.

Continuous scaling of CMOS process technology to 7nm (and below) has introduced new constraints and challenges in determining Design-for-Yield (DFY) solutions. In this work, traditional solutions such as improvements in redundancy and in compensating target designs for low process window margins are extended to meet the additional constraints of complex 7nm design rules. Experiments conducted on 7nm industrial designs demonstrate that the proposed solution achieves 9.1%-41% redundant-via-rate improvements while ensuring all 7nm design rule constraints are met.

Standard cell track height scaling provides us with sufficient area scaling at the standard cell library level. The efficiency of this technique and the complexities involved with this scaling method have been discussed in detail [1,2]. However, the area benefits of standard cell track height scaling diminish when we consider the complexities of incorporating on-chip power grid into the DTCO exploration loop. We have previously outlined several layout techniques to improve the utilization density of this scaling technology [2,4]. However, the proposed techniques only minimize the impact of the power grid on the design. In this work, we discuss the need to combine 3D – μTSV technology and logic technology to decouple the power grid from the design budget. The proposed technique delivers power from the backside of a thinned device wafer using the process steps depicted in Figure 4. Our analysis demonstrates significant area savings and IR-drop reduction. We use SPICE simulations to extract grid resistances as part of our technology targeting process, based upon a high-level on-chip PDN model. We also verify our findings using a commercially available EDA toolchain.

Advanced technology nodes are based on nFET and pFET fins, which are fabricated on the same Silicon level of the wafer. However, in a complimentary FET (CFET) technology the nFET and pFET devices are stacked on top of each other [1]. This provides a significant area reduction mainly driven by a simplified transistor terminal access and the removal of the lateral physical separation between the two transistors. The combination of the CFET with buried power rails can reduce the track height of the cells and the elusive 3 Track standard cell is seen to be a possibility.

Problems in simulation, in physical defects, or in electrical failures of the IC devices generally occur at the boundaries of dimensional tolerances, such as the minimum width and space. However, for layout configurations with four or more critical dimensions, simple minimums are insufficient to characterize dimensional coverage. Persistent homology is a multi-resolution analysis technique which robustly summarizes dimensional coverage. We apply this technique to compare dimensional coverage of IC design configurations, on the same layer, on different layers, and on different designs, yielding results both expected and unexpected based on manufacturing process and design rule knowledge.

Detecting and resolving the true on-wafer-hotspot (defect) is critical to improve wafers’ yield in high volume manufacturing semiconductor foundries. Traditionally, Optical Rule Check (ORC) with computation lithography has been one of the most important techniques to flag potential failure patterns (weak points) after Optical Proximity Correction (OPC), where ORC results are fed back to the OPC team to fix the OPC solution if needed, or fed forward to Contamination Free Manufacturing (CFM) team to improve the inspection accuracy. However, as the integrated circuits process becomes more and more complex with the technology scaling, ORC alone could no longer identify the outlier-alike defects, even though it has helped in resolving most of defects on wafer. Failing to detect yield-killer defects could be due to the lack of sufficient understanding and modeling in terms of etching, CMP, as well as other inter-layer process variations. It has been a struggle for Fab to identify reasonable amount of defects scattered on wafer in order to understand defect mechanisms quickly, thus find ways to fix them in a timely manner. In this paper, we present a fast and accurate Defect Detection and Repair Flow (DDRF) with machine learning (ML) methodology to address the above issues. There are four parts in the DDRF: the first part is on the feature generation and data collection, the second on the ML model building, the third on the full-chip prediction, and the fourth on the hot-spot repair. We use limited amount of known defects found on wafer as input to train the ML model, and then apply the ML model to the full chip for prediction. The wafer verification data showed that our flow achieved more than 80% of defect hit rate with engineered feature extractions and ML model for a 7nm mask. Finally, we analyze the failing mechanism with more available defects, and are able to provide guidance to the OPC development to fix the defects by using the ML model.

Layout-pattern-based approaches for physical design analysis and verification have become mainstream in recent years and are enabling many new applications. Prior work introduced the ability to collect all patterns from multiple layouts into a catalog as well as to use machine learning techniques to score and filter patterns to identify which ones are critical. In this paper, data mined from a library of scored patterns from established designs is applied to the analysis of diagnosis results from a new design to improve defect root cause analysis (RCA). The flow for this approach is as follows: patterns interacting with nets reported in diagnosis callouts are selected as patterns of interest (POIs) from the catalog of all patterns. Next, features of interest (FOIs) are extracted from all POIs to build a dataframe. Finally, volume diagnosis results identifying nets with likely open or short defects are added to the dataframe. RCA is performed using the dataframe to identify likely root cause(s) for failures and suggest refined failure locations for targeted inspection, physical failure analysis, or other electrical failure analysis. The approach described above is applied to products in high-volume manufacturing using a leading-edge technology node. Silicon validation results will be included for example applications.

Several tools in the mask data preparation flow utilize the repetitions of patterns within a layout to reduce processing time. Conventionally, this is achieved by an analysis of the design hierarchy. However, intermediate processing in the data preparation flow can distort the hierarchy. Also, some repetitions in small-grain structures may not be represented in the hierarchy. An alternative is to learn repeating patterns and their frequency by analyzing the layout as a flat data structure. This paper demonstrates a methodology for learning the largest repeating patterns in a layout without the use of hierarchy, purely by referencing the layout as a flat data structure. The experimental results show its efficacy for layouts containing hundreds of thousands of polygons, as well as its efficiency in terms of computing time and memory usage. The results indicate that it is practical to use a distributed process to directly learn the largest repeating patterns without resorting to design hierarchy, in a reasonable runtime and memory usage.

Critical edge placement margins continue to shrink in advanced designs, Over the years, various methods have been used to quantify the lithographic “process window”, often in terms of allowable CD variation. Ultimately however, what is of most interest is the margin for chip failure, either due to hard pinching, bridging, or pattern collapse of a single layer, or interlayer critical edge placement errors. The latter could include insufficient overlap between layers such as metal and via, or unwanted bridging of patterns between layers. We present here a framework for estimating the failure rate for any individual feature given an assumed manufacturing distribution of primary patterning variables such as dose, focus, mask dimension, and perhaps overlay. If the failure rate for all features within the die is known, then by extension the failure rate for the entire die can be known. Since estimating the process window exhaustively for all in-die locations is not possible, we first identify process window limiting features, then utilize this knowledge to estimate overall die failure rates. This method can account for both systematic failure of an individual feature instance as well as stochastic failure for repeating patterns.

Machine learning has significant potential to help the human designer produce better outcomes. It can also help manage some of the complexity with chip design in advanced nodes. Projects to be discussed include the following. o Using Bayesian optimization for circuit IP reuse. Analog and custom digital IP reuse is difficult and time-consuming. Professor Franzon's group has built a Bayesian optimization approach involving statistical surrogate models. They have demonstrated by porting a number of designs between nodes, including a BJT to SOI port. The machine learning based approach produced better results than a human designer. o Using Surrogate modeling for Physical design. Professor Franzon's group has used a machine learning approach to predict Global Router and detailed router results as a function of tool input settings. These models can be used to tune the tool setup for specific outcomes. o Using Surrogate Modeling and System Identification Modeling to model digital receiver chains. Digital receiver modeling is predict BER of a receiver in the presence of an input signal with a close eye. Professor Franzon's group has used a combination of Surrogate Modeling and System Identification to build such a modeling capability. o Using deep networks for design rule checking. The team has demonstrated that deep networks can be used instead of Boolen checkers. There is significant potential to close the DFM and custom design productivity gaps.

Machine learning (ML) techniques have been applied for quick optical proximity correction (OPC) processing. A key limitation of previous ML-OPC approaches lies in the fact that a layout segment is corrected while the correction result for other segments is not reflected yet. Bidirectional recurrent neural network (BRNN) model is adopted in this paper to alleviate this problem. BRNN consists of multiple neural network instances, which are serially linked through hidden layer connections in both forward- and backward-directions. Each instance corresponds to one layout segment, so BRNN processing corrects a group of nearby segments together. Two key problems are identified and addressed: mapping between layout segments and neural network instances, and network input features. In experiments, BRNN-OPC achieves 3.9nm average EPE for test M1 layout, which can be compared to 6.7nm average EPE from state-of-the-art ML-OPC method.

As feature resolution and process variations continue to shrink for new nodes of both DUV and EUV lithography, the density and number of devices on advanced semiconductor masks continue to increase rapidly. These advances cause significantly increased pressure on the accuracy and efficiency of OPC and assist feature (AF) optimization methods for each subsequent process technology. Several publications and industry presentations have discussed the use of neural networks or other machine learning (or even deep learning) to provide improvements in efficiency for OPC main feature optimization or AF placement. However, these two mask synthesis steps are not independent. OPC affects AF optimum position and size; and AF position and size both affect the final optimum OPC main feature correction. A challenging example of these interactions is the need for OPC and AF methods to be aware of potential AF wafer printing. AF printing on the wafer can lead to catastrophic device failure. If an AF is at risk of printing in photoresist, both the OPC and the size (and potentially the position) of the AF need to be modified accurately and efficiently. Recent advancements in lithography utilizing negative tone develop (NTD) photoresists (resists) with strong physical shrink effects also further increase the difficulty of accurately modeling AF printing. In this paper, we present results of our work to explore the requirements, the issues and the overall potential for developing robust, accurate and fast integrated machine learning methods to optimize OPC and AFs.

We show how combining machine learning with physical models can improve the overall accuracy of modeling the lithographic process for OPC applications by up to 40%. This level of model accuracy improvement is critical to meet the stringent requirements of the 5nm node and below. We demonstrate how the judicious design of the neural network can create a model capable of high accuracy and high contour quality, even when no contour data is available. This allows the neural network model to be introduced without disrupting the model calibration flow used in OPC.

A suite of DFM enablement is enhanced to address the unique needs of analog, RF, and mmWave designs in the custom design flow. The DFM rules and patterns are made stricter beyond baseline requirements, and new DFM rules and patterns are added to further reduce layout-dependent device variability. Auto-fixing in the custom design flow is enhanced to meet these new requirements. New DFM enablement is developed for device matching for differential circuits and sensitive devices. Lastly, novel DFM fill strategies are implemented to reduce the variability of passive devices operating at high frequencies. Using DFM-aware fill, a 2% quality-factor loss for a mmWave inductor operating at 30 GHz is shown to be sufficient for meeting manufacturing planarity requirements.

There has been a significant increase of optical applications in the last decade, either embedded into complex multifunction devices such as smartphones, or for imaging purpose as cameras. Core of such optical systems are microlens arrays, used for light gathering or light emitting. The most commonly used manufacturing method by the industry is the thermal reflow of photoresist polymer. The method consists in melting previously patterned photoresist dots in order to form the lenses. But the resist shaping into a microlens is not as straight forward, since the final microlens needs to match shaping criteria to maximize the device optical efficiency. The optimization of the microlens 3D shape is thus an empiric and iterative work, where several lithography and reflow process variations are explored. Photomask reorder might also be needed in order to finally reach the final targeted microlens. All of this results in a costly and time consuming process tuning work. A low cost alternative option to overcome this practical issue and make the overall microlens optimization process easier would be to have at disposal a resist reflow simulation tool, which could predict the photoresist shaping evolution through melt and cure steps. This would help designers and lithographer to evaluate beforehand the final shape of a certain design at the end of the process flow. It would then offer the possibility to identify from the start the correct design to embed onto the photomask guaranteeing the fabrication of the desired microlens. A 3D compatible and computation efficient reflow simulation software is proposed in this paper, in line with a Design Process Technology Co-optimization (DTCO) approach. It allows the fast 3D reflow simulations of hundreds of different resist patterns, taking as input a CAD design and returning the corresponding 3D microlens that will be formed. The purpose of this paper is to present the developed reflow modeling software solution and its calibration methodology. The use of the proposed alternative simulation flow for microlens optimization in a Resolution Enhancement Technics (RET) environment will also be described.

In subwavelength lithography, the printed patterns on the silicon wafer suffer from geometric distortions and different from the original design. These non-rectangular patterns can affect electrical characteristics and circuit performances seriously. In this work, we extend the verification of location-dependent weighting method and further propose three single conventional equivalent gate length (EGL) extraction methods for representing each non-rectangular gate transistor with a single EGL model. These methods are applied to sub-20nm FDSOI circuits to predict the postlithography performances. An in-house Extreme Ultraviolet Lithography (EUVL) simulation tool is utilized for nonrectangular pattern simulation. Shape information is imported to TCAD to construct 3D non-rectangular FDSOI transistor models. The accuracy of the location-dependent weighting method and EGL extraction methods are verified with TCAD circuit simulations. A 2D EGL circuit simulation method in TCAD is proposed instead of 3D EGL method to reduce the simulation time required. Preliminary simulation results indicate that weighting factors can improve the accuracy of electrical characteristics estimation, especially in leakage current analysis. On average, the off-state EGL (EGL_off) with weightings is good enough. These methods could be used to simulate the non-rectangular transistors applied to sub-20nm FDSOI circuits including 6T-SRAM caused by non-ideal optical effects in industrial processes.

This paper presents a methodology to optimize standard cells and other small IP for manufacturability. The optimization is based on an evolutionary machine learning algorithm. This algorithm creates variants of a starting cell by randomly selecting and moving edges, and selects the best variant based on a scoring methodology for the next set of iterations. The opportunity for such an algorithm arises from the complexity of advanced node design rules, where multiple rules compete and have to be optimized simultaneously across multiple mask layers. Doing this process manually is a lengthy and highly iterative process and most often leaves DFM opportunities on the table. The selector in the algorithm is a combination of MAS/DRC rule-based checks, and a holistic multi-layer lithographic process window metric. Specifically library standard cells can be optimized for DFM scores and printability within a very short time frame.

The continuous scaling of 3D NAND by vertically stacking more tiers in a single die presents some major challenges . One of these challenges is the effect of increasing surface topography on photolithography. Although photolithography is relaxed in 3D NAND process compared to 2D NAND, surface topography can lead to a reduced process window (PW) of critical immersion levels. For a metal routing level near the top of the die stack, up to ~240 nm of topography can be present at immersion photolithography levels. In tight pitch regions of the metal routing layout, topography variations can cause poor printing, particularly near locations where the metal routing bends due to various layout constraints. Edge progression and corner jog layout optimization provide a solution to this less-discussed challenge in the 3D NAND fabrication process. Simulation results show a 70% increase of the PW in the areas where edge progression was applied. In bending regions of the metal routing, jog optimization improves the PW by 40%. These two layout optimization techniques increased the overall metal routing PW by ~40%, and this increase was validated by wafer FEM data. Additionally, the same jog optimization and edge progression techniques can be used to fix hot spot areas due to process variations. This paper presents a solution to compensate for the decreased PW of the metal routing level near the top of a 64-tier 3D NAND die due to fab topography issues through corner jog and edge progression layout optimization.

Rigorous patterning control at critical wafer process steps of semiconductor fabrication is done to ensure integrity of the manufacturing process. At times, still with the entire existing process control infrastructure, we run into defect issues. Here we report an innovative methodology of Pattern Monitor that complements the existing approach and consistently detects critical defects on wafer that are hard to find using conventional wafer inspection tools. The unique integrated pattern centric approach puts this method apart from all the current inline tools. The Die-to-Database Pattern Monitor (D2DB-PM) solution has been applied to understand the evolution of pattern deformation through process integration engineering. A pattern centric engine is the key to this successful solution that is used to process large volumes of already existing Scanning Electron Microscope (SEM) images to perform Die-to-Database shape and critical dimension evaluation to detect deviations in the patterning behavior. This solution helped to resolve the limited Critical dimension (CD) measurement constraint that is otherwise associated with Critical Dimension Scanning Electron Microscope (CDSEM) measurement. In this paper we report the results from this innovative solution to detect process marginality and also verify the improved patterning behavior after the process fix is implemented.

Self-aligned quadruple patterning (SAQP) is not compatible with every design. It couldn’t pattern even number routing track, for examples 4 internal routing tracks with power rails side by side, due to the process footprint of conventional SAQP. On the other hand SAQP spacer merge technique is able to remove 1 internal metal line by merging 2 spacer into 1 spacer. It can offer additional track scaling and flexible design of track number, for example, 5.5 tracks together with 6.5 tracks to accomplish low and high performance device respectively. In this paper, SAQP spacer merge technique and self-aligned block (SAB) process are considered as one of potential patterning approaches for 1D style 28 nm metal pitch. SAQP spacer merge technique is indispensable for supporting 5.5T cell of 4 internal tracks with 28nm metal pitch. And 5.5T cell also requires the irregular metal color array for SAB and its biases which is litho-etch skew. SAB can be sized up double compared to conventional block process, it is biased over next metal line to takes advantage of material etch selectivity of SAQP structure inherently before metallization. To meets those requirement with automatic mask layout generation, we newly proposed forward decomposition algorithm and color-aware block resizing of SAB. The forward decomposition algorithm generates mandrel to spacer 1 to spacer 2 to mimics process order of SAQP spacer merge technique. And color-aware block resizing of SAB needs conditional bias depending on neighboring metal color. Additionally, edge placement error budget is analyzed with process variation band of source mask optimization (SMO) on top of overlay, line edge roughness (LER) and etch uniformity assumption. Simulation result seems to be fine to enable SAQP spacer merge and SAB integration. However, EUV stochastics reported that CD uniformity is not fit in Gaussian distribution. Considering beyond 3σ, restricted design rule may be needed. To see design availability, 3 representative standard library cells were verified in design rule restriction without area loss. This SAQP spacer merge decomposition algorithm is useful since it is possible to extend for Fin patterning application as well.

As EUV lithography is getting ready for deployment in high volume manufacturing, lithography engineering focus moves to efficient computational lithography tools (mask correction, verification, source-, mask- and processoptimization) providing optimal RET solutions for EUV early design exploration. Key to computational lithography success is the prediction ability of the underlying lithography process simulation model. Topographic mask effects prediction is one of the major challenges with significant impact on both simulation quality of results and turn around time. In this paper, we apply a fast modeling approach to EUV light diffraction on topographic masks, which is based on fully rigorous topographic mask simulations. It is demonstrating performance benefits of several orders of magnitude while maintaining the accuracy requirements for productive cases. We explore its applicability to medium sized computational lithography tasks. The accurate mask solver results will be complemented with imaging and 3D resist simulations using the rigorous lithography simulator S-Litho by Synopsys.

The difficulties involved in ramping EUV lithography to volume manufacturing have highlighted the critical task of understanding process, layout design and device interactions, and also of optimizing the overall product integration to reduce undesirable interactions. In this paper, we demonstrate mask synthesis methods that using rigorous EUV lithography models together with inverse lithography technology (ILT) for EUV process window and CD control improvement. To enable this new capability, we have linked the broad EUV physical effect modeling capability of our rigorous lithography simulator, Sentaurus Lithography (S-Litho), with our highly flexible production proven ILT mask synthesis solution (Proteus ILT). This new combined capability can take advantage of the wide range of EUV modeling capabilities including rigorous electromagnetic mask/substrate modeling. The advantages of using S-Litho rigorous simulation for ILT optimization is further benefited from significant speed enhancements using new high performance EUV mask 3D capabilities. ILT has been extensively used in a range of lithographic areas for DUV and EUV including logic hot-spot fixing, memory layout correction, dense memory cell optimization, assist feature (AF) optimization, source optimization, complex patterning design rules and design-technology co-optimization (DTCO). The combined optimization capability of these two technologies therefore will have a wide range of useful EUV applications. We will highlight the specific benefits of the rigorous DUV and EUV ILT functionality for several advanced applications including resist profile optimization for resist top- oss and resist descumming and process window improvement.

Lithography hotspot detection and correction in the layout design phase is important to suppress manufacturing yield loss. Although machine learning based hotspot detection methods are considered as effective solutions over conventional lithography simulation, it is still difficult to apply them to practical layout design tasks because of a trade-off between detection accuracy and false alarms. In this paper, we propose a fast, accurate and reliable method to detect lithography hotspot candidates based on coherence map. Experimental results show that our method outperforms typical machine learning based hotspot detection models on industrial benchmark.

Layout context plays a very significant role in printability of layout shapes, and hence it is extremely critical to include layout context information while performing printability checks. In this paper, we are proposing a unique approach of analyzing layout context geometries and use Machine Learning (ML) technique to predict lithography hotspots. Our method uses past lithography simulation results to evaluate geometry margins and profile them in simple geometry rules. The markers of these rules then analyzed by our unique context analyzer and generate data set for train Arterial Neural Network (ANN). Later this trained ANN model used for predictions on new input designs. In this paper, we will also present results to highlight how our approach is better in the accuracy of lithography hotspots detection in comparison to previous work related to pattern matching and machine-learning techniques.

Design-process weakpoints also known as hotspots cause systematic yield loss in semiconductor manufacturing. One of the main goals of DFM is to detect such hotspots. For the application of AI in hotspot detection, a variety of machine learning-based techniques have been proposed as an alternative to time expensive process simulations. Related research works range from finding efficient layout representations and features and developing reliable machine learning models. Main stream layout representations include density-based feature, pixel-based feature, frequency domain feature, concentric circle sampling (CCS) and squish pattern. However most of them are either suffering from information loss (e.g. density-based feature, and CCS), or not storage efficient (e.g. images). To address these problems, we propose a convolutional neural network called Squish-Net where the input pattern representation is in an adaptive squish form. Here, the squish pattern representation is modified to handle variations in the topological complexity across a pattern catalog, which still allows no information loss and high data compression. We show that different labeling strategies and pattern radius contribute to the trade-offs between prediction accuracy and model precision. Two imbalance-aware training strategies are also discussed with supporting experiments.

Lithography hotspot detection using lithography simulation (LCC) in a design stage is one of important techniques in order to avoid yield loss caused by the hotspots. Conventional LCC should detect all hotspots observed on wafer and reduce false errors which are not hotspots on wafer. However, the conventional LCC is not enough to meet the requirement. In this paper, we propose a multi-criteria hotspot detection method with a pattern classification technique. The proposed method uses a peak intensity value as the criterion and different criteria are used for different pattern categories. The categories are created based on K-means algorithm. Experimental results show our proposed method can reduce a number of false errors by 75% without any overlooking of hotspots.

Chemical mechanical polishing (CMP) is a critical process in Integrated Circuit (IC) manufacturing used to ensure planarity of the layers which comprise the IC. The IC design and CMP process must be optimally integrated otherwise dishing and erosion may occur on any of the various layers resulting in significant degradation impacting lithographic pattern fidelity and performance variability. Consequently, it is desirable to accurately predict if and where these hotspots (HS) will appear early in the design to ensure high manufacturing yield and predicted performance. In this work, we use a Deep Learning (DL) multilayer convolutional neural network (CNN) algorithm to model CMP hotspots for full-chip multilayer layouts. The DL model consists of convolutional layers for automatic feature extraction and fully-connected CNN layers for HS classification and detection. Our implementation can learn/capture effects that go beyond traditional methods in that these effects can be discovered from previous technologies with transfer learning and the model can be trained with either simulation or topography measurement data. Further, the model is trained from multiple layers and CMP results thereby enabling modeling and prediction of hotspots resulting from complex inter-layer interactions or effects which may escape traditional methods. With the proposed DL model, we achieved a hotspot prediction accuracy of up to 98% with up to 10 metal layers. After training the model, the inference time for a full chip can be up to 10x faster than existing CMP tools. This flow enables CMP/Fill-aware design validation that can help to create optimal high-yielding customer designs.

In this work we are introducing a manufacturing flow for the SALELE Process in details. Starting with layout decomposition, where the drawn layer is decomposed into 4 Masks: 2 Metal-like Masks, and 2 Block-like Masks. Then each of these masks is subjected to Optical Proximity Correction (OPC) process, and here we explain more about the OPC recipe development for each mask. Then we introduce a verification flow that performs two levels of verifications: (a) Litho verification, where the litho fidelity of each mask is quantified based on image quality measurements. (b) Final Manufactured shapes verification vs. expected output. This work has been carried out on an N3 candidate layout designed by IMEC.

The effective test pattern is a crucial component for lithography process optimization such as Source Mask Optimization (SMO) and Optical Proximity Correction (OPC). The conventional parameterized test patterns cannot represent various contexts of patterns, thus sample patterns extracted from layout become an alternative option. This paper introduces a sample patterns extraction method based on the hierarchical clustering algorithm, according to the geometric characteristics. Meanwhile, an improved HLAC-based method is applied to the layout patterns at the stage of feature extraction for accurate characterization. The method can reduce the number of test patterns while maintaining high coverage of layout’s geometric features. The lithography process window is analyzed to validate the effectiveness of the patterns clustering flow. Moreover, the comparison between the spectrums of sample patterns and original layout also indicates that the proposed sampling method preserve a sufficient coverage of layout’s optical characteristics. Pattern extraction method in this paper could provide a candidate solution for fast test pattern generation with high coverage for lithography process exploration.

At the early stage of a new technology development, Ground Rule (GR) calculations are performed assuming design targets are met, and all the process variations are within certain process assumptions. However, as technology matures, it is expensive, and time consuming to verify these assumptions for all the designs allowed by the rules. Thus, there’s a loop hole in the GRs if these assumptions are not met on the design. This issue becomes even worse for 2D dense design such as SRAM, where the design target and wafer image are so different due to all the corners, jogs, line ends etc, and the process variations are much larger for the 2D designs. As a result, SRAM designs almost never follow a standard GR approach but its own unique rules. In fact, for SRAM designs of slightly different style, the rules will be significantly different. On the other hand, Process Variation (PV) contours offer much more details of process variations even though their usage is very limited. One reason for that is that off-nominal conditions having larger risks from rule point of view but have lower probability at the same time, making it a dilemma for us. In this talk we propose a method to incorporate PV contours in GR calculation, and each PV contour are used in Monte-Carlo calculation in accordance with its own probability. We apply this method in SRAM layout optimization as an example. This work was performed at the IBM Semiconductor Research Center, Albany NY 12203

Vertical NAND (3D NAND) designs provide unprecedented improvements in input/output (I/O) performance and storage density, but require additional analysis to ensure manufacturing and market success. While 3D stacked architectures greatly reduce chip area at advanced technology nodes, greater topology uniformity is essential, not only for inter-layers stacking, but also for the chip bonding process. As the link between design and manufacturing, design for manufacturing (DFM) predicts potential manufacturing issues during the design stage, enabling design teams to modify the layout and mitigate the risk. The copper interconnect process can be modeled through multiple process steps, from film stacking, etch, and copper deposition to polishing. The simulated topology of a given design predicts potential risky areas that may be fixed by changing designs or inserting dummy fill prior to manufacturing. This simulation is a useful technique during yield ramp-up, and can shorten the cycle from design to manufacturing. This paper presents a solution for BEOL CMP modeling and analysis on BEOL copper interconnect of a 3D NAND flow.

Chemical-mechanical polishing (CMP) is a key process that reduces chip topography variation during manufacturing. Any variation outside of specifications can cause hotspots, which negatively impact yield. As technology moves forward, especially in memory processes like 3D NAND, high-quality surface planarity is required to overcome manufacturing challenges in each process step. Any topography variation in the front-end-of-line (FEOL) must be taken into consideration, as it may dramatically impact the surface planarity achieved by subsequent manufacturing steps. Rule-based checking of the design is not sufficient to discover all potential CMP hotspots. An accurate FEOL CMP model is necessary to predict design-induced CMP hotspots and optimize the use of dummy fill to alleviate manufacturing challenges. While back-end-of-line (BEOL) CMP modeling technology has matured in recent years, FEOL CMP modeling is still facing multiple challenges. This paper describes how an accurate FEOL CMP model may be built, and how interlayer dielectric (ILD) layer CMP simulations may be used for 3D NAND design improvement. In the example of ILD CMP model validation for a 3D NAND product, it is shown that the model predictions match well with the silicon data and that the model may successfully be used for hotspot prediction in production designs prior to manufacturing.

Use of lithography exposure and metrology tools in production typically results in worse performance than seen on test wafers. Physical design always starts with rough design rule for a new technology node. To evaluate the influence of the inevitable degraded performance on test wafers, our paper put forward a systematic approach to evaluate whether the ability of current process can support the design. The approach utilizes litho-friendly design (LFD) to find the yield killers and conducts pattern classification with pattern matching. Process window discovery (PWD) is used to collect the statistical data to confirm whether the yield killers in LFD simulation will meet the systematic fail on wafer. It is necessary to do mask optimization (MO), source mask optimization (SMO) and design rule optimization (DRO) for the real yield killers. Moreover, design of advanced node may include the patterns inside forbidden pitch range. We do the design rule exploration for metal 2 layer of 14nm technology node and discuss the corresponding solutions for width sensitive zone as well.

In the preparation of Integrated Circuits (ICs), employing the Dual Damascene (DD) via-first approach, the fulfilling of extremely deep via and, in general, of highly etched structures, still remains a challenging task. Especially, if this is combined with the need to obtain a planar surface with a thickness bias proximal to zero between flat zones and highly via-rich parts of the die or deep trenches. Herein, we report a full analysis of the impact of the nature of solvent and polymer composing the Hard-Mask (HM) precursor on the filling of via and long trenches. The analysis is carried out by means of optical microscopy (OPT) and scanning electron microscopy (SEM) on standard silicon wafers processed with the HM, changing different variables; from the use of materials comprising different solvents and polymers with various C-contents, up to the variation of the coating parameters such as: the spin speed, the bake temperature and the primer vaporization step before dropping the via-filler material. Interestingly, the solvent is demonstrated to play a crucial role in the formation of macro-defectiveness on long deep trenches surrounded by a flat area: PropyleneGlycolMonomethylEtherAcetate (PGMEA) uniquely-based materials can bring to a peculiar halation-effect, partially avoided with the introduction of several pre-bake steps of the under-layer on a HexaMethylDiSilazane (HMDS)-presprayed Silicon surface.

As technology advances, chip size becomes larger and larger, this brings challenges when engineers would like to do a quick investigation of the design in a short time, like hotspot detection and layout fixing. An idea to mitigate the challenges is to decompose a layout into patterns and classify these patterns to unique ones. Engineers then prioritize their work on these unique patterns. Patterns from different products can be accumulated and recorded, when a new design comes in, the known patterns will be filtered out from all unique patterns seen in this new design. When the pattern database is large enough and contains enough safe and weak patterns, machine learning can be used to train the algorithm to predict hotspots in the new design. The key point is how to efficiently decompose a layout and group those patterns. This paper presents how to decompose a layout by using Calibre Pattern Matching and DRC. The experiment data shows that this is a very efficient way to decompose a layout automatically.

When technology comes to 28nm and beyond, chip size and design complexity are increasing. Lithography simulation is computing intensive and it may takes days to see whether there is any hotspot hard to solve other than change the design. Pattern classification is quite a matured technique and it can be used to locate unique patterns on a chip, then it is possible to do lithography simulation on these unique pattern locations first. This is an efficient approach to quickly detect any unfriendly design style on the layout and give designers enough time to fix these unfriendly designs and do an incremental check to validate the fixing. Once the fixing approach is validated, a pattern matching based pattern substitution can be used to fix all the problematic areas on the layout.

As the typical litho hotspot detection runtime continue to increase with sub-10nm technology node due to increasing design and process complexity, many DFM techniques are exploring new methods that can expedite some of their advanced verification processes. The benefit of improved runtimes through simulation can be obtained by reducing the amount of data being sent to simulation. By inserting a pattern matching operation, a system can be designed such that it only simulates in the vicinity of topologies that somewhat resemble hotspots while ignoring all other data. Pattern Matching improved overall runtime significantly. However, pattern matching techniques require a library of accumulated known litho hotspots in allowed accuracy rate. In this paper, we present a fast and accurate litho hotspot detection methodology using specialized machine learning. We built a deep neural network with training from real hotspot candidates. Experimental results demonstrate Machine Learning’s ability to predict hotspots and achieve greater than 90% detection accuracy and coverage, with best achieved accuracy 99.9% while reducing overall runtime compared to full litho simulation.

The 3D NAND (three-dimensional NAND type) has rapidly become the standard technology for enterprise flash memories, and is also gaining widespread use in other applications. Continued manufacturing process improvements are essential in delivering memory devices with higher I/O performance, higher bit density, and lower cost. Current 3D NAND technology involves process steps that form array and peripheral CMOS (Complementary Metal-Oxide-Semiconductor) regions side-by-side, resulting in waste of silicon real estate and film stress compromises, and limits the paths of making advanced 3D NAND devices. An innovative architecture was invented to overcome these challenges by connecting two wafers electrically through millions of metal VIAs (Vertical Interconnect Access) simultaneously across the whole wafer in one process step [1]. A highly accurate and efficient metrology is required to monitor the VIA interface due to the increased process complexity and precision requirements. With the advanced processing of AFM (Atomic Force Microscopy) images, highly accurate and precise measurements have been achieved. An inline pattern-centric metrology solution that is designed for high volume mass production of high-performance 3D NAND is presented in this paper.