This PDF file contains the front matter associated with SPIE Proceedings Volume 10961 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

We explore role of software modeling in semiconductor manufacturing and contrast it with the roles that modeling plays in other fields of human activity. Major trends and challenges in physical and compact process modeling are discussed. We contemplate complexities arising from their multi-dimensional nature. The landscape of Optical Proximity Correction and satellite applications is surveyed. Instructive examples are collected that demonstrate shortcomings of our intuition while dealing with complex systems and parameter interactions. We ponder over the scientific and business opportunities of new promising techniques and prospective applications.

Deep learning has recently been successfully applied to lithography hotspot detection. However, automatic correction of the detected hotspots into non-hotspots has not been explored. This problem is challenging because the standard supervised learning requires a training dataset with pairs of hotspots and non-hotspots, which is impractical to collect because lithography hotspots involve diverse and complicated lithographic pattern properties. In this paper, we propose a new framework for lithography hotspot correction with a deep generative network combined with a learning strategy optimized for lithography patterns. Our key idea is to learn to translate hotspots to non-hotspots and vice versa, simultaneously. In this way, the training dataset does not have to be paired, and hotspot patterns in variety of background can be learned. Our method does not require the understanding of the cause of hotspots and can correct hotspots that are difficult to recognize by conventional approaches. For evaluation, we propose to synthesize a training dataset that reflects a variety of real-world lithography patterns. Experimental results show that our framework can correct hotspot images with comparable quality as a conventional complicated process, while significantly reducing the overall processing time.

Etch process is critical to CD control in patterning, but Etch-aware OPC is not as accurate as lithographyaware OPC. Etch process is not understood very well compared to lithography, so empirical etch model like Variable Etch Bias (VEB) has been used for OPC. Although VEB has been quite successful so far, accuracy of etch model needs be improved with below 10 nm node devices. Machine Learning (ML) is applied in this work for VEB model improvement. However, ML is also an extreme empirical model, in fact, so over-fitting is a big problem with machine learning. We demonstrate over-fitting as well as accuracy can be improved in this work as presenting specific methods of ML such as double-stage machine learning, etch-relevant inputs and ensuring sample-coverage.

Model-based optical proximity correction (MPOPC) has been well adopted in subwavelength lithography for integrated-circuit manufacturing. Typical MBOPC algorithms involve with iteratively moving the layout polygon edges to reduce the edge placement errors (EPEs) predicted by the lithography model. At each iteration, the amounts of movement are mainly determined by the values of the EPEs and the correction factors (CFs). Since full-chip lithography simulation is very computation intensive, it is highly desirable to minimize the number of iterations for acceptable run times, by selecting suitable CFs. In practical applications, the CFs are usually heuristically determined and applied globally throughout the correction regions. This approach efficiently reduces the EPEs at most of the target points but the entire convergence can be hampered at a relatively small number of hot-spot locations. This work investigates the effectiveness of improving the overall convergence by introducing both global and local CFs, and approaches to utilize machine-learning techniques to estimate the hot-spot locations and associated local CF values.

As technology continues to scale aggressively, Sub-Resolution Assist Features (SRAF) are becoming an increasingly key resolution enhancement technique (RET) to maximize the process window enhancement. For the past few technology generations, lithographers have chosen to use a rules-based (RB-SRAF) or a model-based (MB-SRAF) approach to place assist features on the design. The inverse lithography solution, which provides the maximum process window entitlement, has always been out of reach for full-chip applications due to its very high computational cost. ASML has developed and demonstrated a deep learning SRAF placement methodology, Newron™ SRAF, which can provide the performance benefit of an inverse lithography solution while meeting the cycle time requirements for full-chip applications [1]. One of the biggest challenges for a deep learning approach is pattern selection for neural network training. To ensure pattern coverage for maximum accuracy while maintaining turn-around time (TAT,) a deep-learning-based Auto Pattern Selection (APS) tool is evaluated. APS works in conjunction with Newron SRAF to provide the optimal lithography solution. In this paper, Newron SRAF is used on a DRAM layer. A Deep Convolutional Neural Network (DCNN) is trained using the target images and Continuous Transmission Mask (CTM) images. CTM images are gray tone images that are fully optimized by the Tachyon inverse mask optimization engine. Representative patterns selected by APS are used to train the neural network. The trained neural network generates SRAFs on the full-chip and then Tachyon OPC+ is performed to correct main and SRAF simultaneously. The neural network trained by APS patterns is compared with those trained by patterns from manual selection and multiple random selections to demonstrate its robustness on pattern coverage. Tachyon Hierarchical OPC+ (HScan+) is used to apply Newron SRAF at full-chip level in order to keep consistency and increase speed. Full-chip simulation results from Newron SRAF are compared with the baseline OPC flow using RBSRAF and MB-SRAF. The Newron SRAF flow shows significant improvements in NILS and PV band over the baseline flows. This whole flow including APS, Newron SRAF and full-chip HScan+ OPC enables the inverse mask optimization on full-chip level to achieve superior mask performance with production-affordable TAT.

For the past several years there has been a push in the industry to drive innovation by pairing different types of metrology to keep up with the challenging requirements of overlay, focus and CD in multi-patterning processes. Holistic metrology is an example of this where instead of using a single metrology method we pair various available metrology methods to enrich the overall information content. With advancements in deep learning algorithms we can better utilize existing infrastructure to extract information from metrology parings for a cost-effective solution that has traditionally gone unused. In computational alignment metrology we pair leveling data with alignment and wafer quality to generate a dense alignment vector map. In the first step wafer leveling metrology from the lithographic apparatus is deconvolved into individual contributors. Selecting the deconvolved signatures with greatest influence on alignment metrology we train our dense input metrology to our targeted alignment metrology using a deep feedforward network. With the trained weights and biases of the deep feedforward network and input from a new lot of wafers we can now compute a dense alignment vector map. With a 3rd order HOWA model fit to the original 32 marks and then again to the same 32 marks paired with leveling, the model fit to the dense estimation from the 32 marks paired with leveling out performs HOWA fit to the original 32 marks. Finally, by fitting an advanced alignment model which optimizes spatial frequency between our enhanced alignment and corresponding overlay metrology, we can realize additional performance improvements in wafer to wafer overlay.

To support the manufacturing of DRAM semiconductors for next and future nodes, there is a constant need to reduce the overlay fingerprints. In this paper we evaluate algorithms which are capable of decoupling wafer deformation from mark deformation and extrapolation effects. The algorithms enable lithography tools to use only the wafer deformation component in the alignment feedforward correction. Therefore improving the (wafer to wafer) overlay. First results will be shared showing improvement of wafer to wafer variation in high-volume manufacturing environment.

Layout features become highly susceptible to lithography process fluctuations due to the widening subwavelength lithography gap. Problematic layout patterns incur poor printability even if they pass design rule checking. These hotspots should be detected and removed at early design phases to improve manufacturability. While existing studies mainly focus on hotspot detection and pattern classification, hotspot pattern library generation is rarely addressed in literature but crucial to the effectiveness and efficiency of hotspot detection. For an advanced process, in addition to yield-limiting patterns inherent from old processes and computation intensive lithography simulation, defect silicon images (SEM images) inspected from test wafers provide more realistic process-dependent hotspots. For facilitating hotspot pattern library generation, we raise a pattern matching problem of searching design layout patterns that may induce problematic SEM images. The key challenge is the various shape distortions between an SEM image and corresponding design layouts. Directly matching either feature points or shapes of both is thus not applicable. We observe that even with shape distortions, matched design layouts and the SEM image have similar density distribution. Therefore, in this paper, we propose an efficient multilevel pixilation framework to seek layout clips with similar density distribution from coarse- to finegranularities to an SEM image. The proposed framework possesses high parallelism. Our results show that the proposed method can effectively and efficiently identify matched layout pattern candidates.

Modern photoresists shrink during exposure and post-exposure bake processes. The shrinkage is of an elastic nature, occurring below the glass transition temperatures when material does not flow. This elasticity problem is usually modeled numerically using finite element method. Here this problem is solved analytically for a one-, two-, and three- dimensional distribution of displacements. Exact analytical solutions in the form of Fourier series by the lateral film coordinates were found. The film shape and lateral displacements after shrinking are found to be convolutions on the distribution of voids that are formed after evaporation of volatile chemicals. Convolution is a fast numerical algorithm easily incorporated into compact process models for optical proximity correction and applied to the full chip processing. Photoresist shrinking effects are analyzed using this apparatus for modern bright and dark tone processes.

Chemically amplified resists undergo various chemical phenomena during the photolithography process such as exposure, post-exposure bake (PEB), and development. These chemical changes induce various stresses causing the deformation of exposed region of photoresist. It is imperative to include these deformations in the modeling of lithographic processes especially for negative tone development (NTD) process, where an exposed and deformed part of the resist stays on the substrate after development. We use rigorous physical model to express the stresses induced by voids created in resist by evaporation of the protecting species. Finite Element method (FEM) is then used to solve three-dimensional elastic deformation equations for resist during PEB and development. The deformation of resist is studied for both one-dimensional gratings and two-dimensional contact holes with varying pitch and optical doses, and we discuss how different modes of deformation are important to be considered in the lithography simulations in order to reduce the critical dimensions’ (CD) computation error. Finally, we briefly introduce a compact model where Fourier series are used to find the exact analytical solution of elastic deformation equations. The results of compact model are compared with the rigorous FEM solution. The compact model is suitable for full chip lithography simulations due to it being numerically fast operations and results comparable to full-physics rigorous simulations.

In recent years, compact modeling of negative tone development (NTD) resists has been extensively investigated. Specific terms have been developed to address typical NTD effects, such as aerial image intensity dependent resist shrinkage and development loading. The use of photo decomposable quencher (PDQ) in NTD resists, however, brings extra challenges arising from more complicated and mixed resist effect. Due to pronounced effect of photoacid and base diffusion, the NTD resist with PDQ may exhibit opposite iso-dense bias trend compared with normal NTD resist. In this paper, we present detailed analysis of physical effects in NTD resist with PDQ, and describe respective terms to address each effect. To decouple different effects and evaluate the impact of individual terms, we identify a certain group of patterns that are most sensitive to specific resist effect, and investigate the corresponding term response. The results indicate that all the major resist effect, including PDQ-enhanced acid/base diffusion, NTD resist shrinkage and NTD development loading can be well captured by relevant terms. Based on these results, a holistic approach for the compact model calibration of NTD resist with PDQ can be established.

Due to the semiconductor industry’s ever increasing need for finer resolution and improved critical dimension (CD) control, negative tone development (NTD) photoresists (resists) have been adopted for several advanced applications in lithographic patterning. NTD resists enable brightfield imaging by using an organic solvent developer to penetrate and remove the unexposed regions of the resist [1]. For certain critical patterning layers, such as metal trenches and vias, NTD resists are able to provide better resist imaging quality compared to the previous positive tone development (PTD) resist process. However, there are several additional engineering difficulties which must be addressed for an NTD resist process. Specifically, NTD resists have low contrast organic solvent development and in an NTD process the material remaining on the wafer substrate is exposed resist which has been substantially transformed both chemically and mechanically. Therefore, the remaining exposed resist shows significantly more complex physical behavior than the remaining PTD resist and these behaviors require substantial improvement in an OPC (compact) model’s physical modeling accuracy in order to match wafer data and trends [2,3]. Additionally, these more complex resist behaviors place further requirements on the physical validation of OPC modeling inference. In this paper, we present results of our work to understand and improve the optimization and physical validation of physics-based NTD compact modeling flows by utilizing new methods for analysis and automation. We utilize a complete compact model flow containing physics-based resist model forms for chemically amplified resist (CAR) exposure, CAR reaction-diffusion, resist top-loss due to exposure combined with post-exposure bake (PEB), low contrast organic solvent development of resist, and mechanical deformation effects in multiple process steps. We present solid evidence that this physically-based flow has been validated for accuracy and predictability by comparing it to several experimental NTD datasets and to results of rigorous 3D lithography simulation models which were trained to fit other experimental NTD data. We additionally compared key physics-based model forms from the compact model to the more complex full time-based moving surface NTD models of the rigorous 3D simulation. We next analyzed the key physics-based compact model forms for sensitivity to input testpattern type, layout and mask dimension (e.g., linearity and MEEF), traditional dose-focus variations, as well as systematic and random noise in CD metrology. We present the results of this study and make recommendations for minimum testpattern and overall process space data to include in NTD compact model datasets. We also present flow benefits obtained from automating different validation tests including the usefulness of employing rigorous lithography simulation NTD results early in the compact modeling flow to improve overall model quality. [1] S-H. Lee, et all. Understanding dissolution behavior of 193-nm photoresists in organic solvent developers.

A variable-angle spectroscopic ellipsometer (VASE) is an essential tool for measuring the thickness of a thin film, as well as its n and k optical parameters. However, for films thinner than 10 nm, precise measurement is very challenging. In this paper, the root causes of these measurement complexities are discussed, and a new approach is proposed to improve measurement accuracy and reliability as the VASE approaches its fundamental limits, that is, the limitations of the system’s mechanical accuracy and optical coherence. Specifically, twelve different polymer thin films were tested, each with 16 test points. The measured thicknesses (ranging from 3 nm to 19 nm) and n- and k-values strongly depended on test settings and on the data fitting algorithm, incident angle, and wavelength selection. Fitting using equal thickness and n-value of multiple test points was applied as additional criteria to evaluate the consistency of the test results. With this technique, reasonable n-values and thickness values were obtained from films that were as thin as 3 nm. To improve the efficiency of the model fitting, film thickness and n-value are associated to allow these two-dimensional parameters to be fitted into a quasi-one-dimensional model, which reduces central processing unit (CPU) utilization.

In this paper, Canon will report on our most advanced 300 mm i-line stepper, the FPA-5550iZ2. Steppers enjoy an inherent productivity advantage, and Canon has developed solutions that overcome stepper disadvantages to realize an exposure tool with high overlay accuracy and excellent productivity. We will review Canon’s 300 mm i-line steppers evolutions that started in 2001 when our first 300 mm i-line stepper provided only 84 wafer per hour (wph) throughput. In 2018, our latest FPA5550iZ2 has evolved to realize more than 250wph for productivity while maintaining the same base design and almost same footprint. This paper will report the technologies that improve productivity and introduce current and underdevelopment functions that can enhance customer processes.

All chipmakers understand that variability is the adversary of any process and reduction is essential to improving yield which translates to profit. Aggressive process window and yield specifications necessitate tight inline variation requirements on the DUV light source which impact scanner imaging performance. Improvements in reducing bandwidth variation have been realized with DynaPulse™ bandwidth control technology as significant reduction in bandwidth variation translates to a reduction in CD variation for critical device structures. Previous work on a NAND Via layer has demonstrated an improvement in process capability through improve source and mask optimization with greater ILS and reduced MEEF that improved CDU by 25%. Using this Via layer, we have developed a methodology to quantify the contribution in an overall CDU budget breakdown. Data from the light source is collected using SmartPulse™ allowing for the development of additional methodologies using predictive models to quantify CD variation from Cymer’s legacy, DynaPulse 1 and DynaPulse 2 bandwidth control technologies. CD non-uniformities due to laser bandwidth variation for lot to lot, wafer to wafer, field to field and within field is now available based on known sensitivities and modeled. This data can assist in understanding the contribution from laser bandwidth variation in global and local CDU budgets.

Multi-patterning lithography for future technology nodes in logic and memory are driving the allowed on-product overlay error in an DUV and EUV matched machine operation down to values of 2 nm and below. The ASML ORION alignment sensor provides an effective way to deal with process impact on alignment marks. In addition, optimized higher order wafer alignment models combined with overlay metrology based feedforward correction schemes are deployed to control the process induced overlay variability from wafer-to-wafer and lot-to-lot. In addition machine learning based algorithms based on hybrid metrology inputs, strengthen the control capabilities for high volume manufacturing. The increase of the number of process layers in semiconductor devices results in an increase of control complexity of the total overlay and alignment control strategy. This complexity requires a holistic solution approach, that addresses total overlay optimization from process design, to process setup, and process control in high volume manufacturing. We find the optimum combination between feedforward and feedback, by having feedback deal with constant and predictable parts of overlay and have scanner wafer alignment covering the wafer-to-wafer variable part of overlay. In this paper we present investigation results using more wavelengths for wafer alignment and show the benefits in wavelength selection and recipe optimization. We investigate the wafer-to-wafer variable content of two experiment cases and show that a sample scheme of about 60 marks is well capable estimating the model parameters describing the grid. Finally, we show initial results of using level sensor metrology data as hybrid input to the derivation of the exposure grid.

Latest ArF immersion lithography has been positioned as the promising technology to meet tighter process control requirements with providing highly efficient productivity, simultaneously. The most important features for the next generation lightsources are the improvement of chip yield and tool availability in manufacturing. One of the key requirements for lightsource is E95% bandwidth, which has become more critical parameter for enhancing process margin and improving optical characteristic. Lower E95% bandwidth enables to increase imaging contrast which demonstrates better OPE characteristic with better resolution as well as improved E95% bandwidth stability that providing CD uniformity on wafer. A newly designed line narrowing module (LNM) enables to lower E95% bandwidth from the standard 300fm to 200fm. The large shrinkage for E95% bandwidth is achieved by the sophisticated design in LNM which enables to lower thermal wave front aberration reducing heat effect at optical elements and mechanical components during lasing the lights. Lower E95% bandwidth reduces a focus blur in the formulated image that is generated from the chromatic aberration with projection lenses in ArF immersion lithography system. In the other hand, it is essential to improve the productivity by means of reducing downtime, the lifetime of consumable modules such as a chamber and a line narrowing module (LNM) is needed to be extended. New electrodes as called “RAIKIRI” electrode with chamber enable lifetime extension from 60 billion pulses (Bpls) to 80 Bpls. Furthermore, new optical design in LNM enables the lifetime to extend from 60 Bpls to 110 Bpls. Hence, the GT65A, maximizes device yield, process productivity therefore provides optimum in the operational costs for chipmakers. In the presentation, the latest development status and performances on GT65A will be discussed.

We have developed an automatic lens control and parameter settings scheme (on-product iLC) for thermal aberration predictive (feedforward) and calibration (feedback) control. Thermal aberration control is essential for critical layers, and lens control parameter setup time reduction is imperative in maximizing scanner uptime. In our experiment, during production lot exposure the new scheme automatically corrected lens control parameters to within sufficient imaging accuracy tolerances, and demonstrated a dramatic reduction in layer setup time compared with the conventional approach, and we will discuss an actual use-case in this paper.

The semiconductor manufacturing roadmap which generally follows Moore’s law requires smaller and smaller EPE (Edge Placement Error), and this places stricter requirements on OPC model accuracy, which is mainly limited by metrology errors, pattern coverage and model form. Current metrology errors are mainly related to SEM image noise and measurement difficulty in complex 2D patterns. And traditional model form improvement by adding empirical terms for PEB (Post Exposure Bake), NTD (Negative Tone Development) and PRS (Physical Resist Shrinkage) effects still cannot meet the accuracy spec because other physical and chemical effects are uncaptured. Fitting these effects also requires comprehensive pattern coverage during model calibration. Solely improving model form may overfit the metrology error, which is risky, while solely improving metrology ignores existing model errors: both factors are troublesome for OPC. In this paper, a new metrology (MXP, naming for Metrology of Extreme Performance) and deep learning (Newron, naming for a Deep Convolutional Neural Network model form) integrated solution is proposed, where MXP decreases the metrology errors and provides good pattern coverage with high-volume reliable CD and EP (Edge Placement) gauges, and Newron captures remaining complex physical and chemical effects embedded in high-volume gauges beyond the traditional model. This solution shows overall ~30% prediction accuracy improvement compared to baseline metrology and FEM+ (Focus Exposure Matrix) model flow in N14 NTD process, predicts SEM shape of critical weak points more accurately.

With semiconductor technology progressing beyond 5nm node, there is tremendous pressure on computational lithography to achieve both accuracy and speed. One very promising technique to accomplish this mission is to take full advantage of the maturing machine learning techniques based on neural network architecture. Some success has been achieved using convolution neural network (CNN) to obtain inverse lithography technology (ILT) solution with significantly less computational time. In general, CNN architecture consists of feature extraction layers and nonlinear mapping function construction layers. To train a CNN model requires a large amount of data and computational resource. To maintain certain intrinsic symmetries of imaging behavior, the feature extraction layers must be carefully engineered using weight sharing techniques or using well balanced training samples of different orientations, otherwise, feature extraction part will be skewed. It is therefore very desired to have a scheme that can obtain optimal feature vector for machine learning based computational lithography automatically without the need of feature extraction layers in CNN. In this paper, we will make an attempt to describe such a scheme and present our test results on machine learning based OPC and ILT solution. It should be understood that machine learning based computational lithography solutions do not possess the capability to replace conventional OPC or ILT completely due to its lack of required accuracy. However, it can provide an initial solution that is close enough to final OPC solution or ILT solution, therefore fast OPC and fast ILT can be realized.

The placement and size of SRAF (sub-resolution assisted feature) can greatly affect the overlapped process window. The time-consuming inverse lithography technology (ILT) can provide the co-optimization for both main pattern and SRAFs, which can guarantee the results with high precision. Rule-based SRAF (RBSRAF) offers the efficient application in large scale layout, which relies mostly on the design of test patterns and the corresponding empirical data on wafer. Our paper demonstrates a methodology of SRAF rule extraction and insertion based on ILT. The SRAF rules are extracted from the results of ILT and inserted by the RBSRAF, which ensures the reliability of the SRAF rules and shortens the development cycle. The hotspots areas with substandard process variation (PV) band are then repaired by ILT tools. Besides, the SRAF printing model can further refine the placement and dimension. The experiment results validate the feasibility of our methodology to be applied in large scale layout finally.

An efficient lithographic source and mask optimization approach is developed based on localized level set methods, which is reformulated as an inverse problem by tracking the evolution of level-set functions (LSFs) embedding the level-set representation of source and mask patterns. A distance regularized level-set (DRLS) term is incorporated into the level-set formulation enabling not only stable LSF evolution and accurate computation by maintaining a signed-distance property, but also a simple and efficient narrow-band implementation. Consequently, optimization dimensionality is significantly reduced by updating the pixels in the vicinity of zero level set (narrow band) instead of all the level sets, effectively reducing computation complexity, resulting in significantly improvements in pattern fidelity convergence in terms of runtime, computation load, Euler time step and caching memory requirement which are merited by numerical simulations.

For deep sub-wavelength lithography, loss of wafer fidelity, such as line end shortening and corner rounding, is a known patterning phenomenon due to the diffraction limitation of the optical systems and some other processing effects. Without properly correcting these effects, particularly for gate corner rounding at the active area, sometime device performance might be limited or wafer yield will be impacted. It is addressable to improve the feature fidelity by OPC (Optical proximity correction) methodology, which is intentionally to offset the light distortion while in mask synthesis process. However, it is most likely becoming better, but not be completely solved at all. In this paper, first, the acceptable gate corner rounding criteria is examined. From the design rule constraint for gate region and test key electrical performance result, primary geometrical specification is determined. At the same time, considering inline process variation, such as ADI CD/overlay variation and loading effect of etching process, then the OPC corner rounding target specification comes accordingly. Second, OPC countermeasure for gate corner rounding improvement is studied. Usually gate CD uniformity is increased near the corner region, that is, gate poly CD is larger than expectation at the beginning of the active area near the L-shape or U-shape poly pattern. Since the transistor performance will be degraded, the improvement for corner rounding is important for OPC development. Aggressive OPC recipe to manipulate the polygon is required. We make use of localized fragmentation rule as well as specific retargeting to eliminate the impact of corner rounding effect in optical system. This methodology for corner fidelity improvement was proved by the wafer result.

To achieve the smallest line width of IC requires the spherical and coma aberration free lithography optics. Once the aberration of lens is formed, it is hard to amend the mask to original requirement, unless the light pattern figure is adjustable. A programmable UVLED array with a collimated lens as Fourier transfer lens forms an adjustable pattern as the intensity profile to amend the aberration of mask to form aberration free mask intensity pattern into wafer. A 25 X 25 UVLED array with collimated lens is applied to correct the aberration contained mask, is to form a corrected pattern under the requirement for reducing aberration mask to form a smallest line width.

As critical dimension shrinks, the image quality of lithographic projection lens is improved gradually. In lithographic tool, vibration is an important factor affecting the image quality of projection lens. The internal vibration of projection lens will change the relative position between the lens elements, reduce the image contrast and process window. There are usually two methods to suppress the internal vibration of lithographic projection lens, isolating the external vibration source and improving the stiffness of the internal structure. Based on the above methods, this paper proposes a dynamic imaging model (DIM) that establishes a precise quantitative relationship between the internal vibration of projection lens and the imaging contrast. The DIM has been used in image performance analysis and the structure design for lithographic projection lens.

In recent years, applications of semiconductor demands have been steadily growing, including automobiles to finance, medicine, agriculture, etc., and the needs for productivity improvement amongst semiconductor manufacturers is higher than ever. To resolve this situation, in the last few years, Gigaphoton developed emerging technologies on light source, to extend the module replacement interval and reduce the maintenance time by state-of-the-art technology into cutting edge lithography operation. In order to access highly effective and utilize productivity, it is required quantitative and predictive approach before service event execution, Gigaphoton also developed a software function named as Availability MAXimization (here after “AMAX”). Currently in light sources, PM (Periodical Maintenance, here after “PM”) schedule bases per chipmaker input concerning wafer production, which is schedule bases PM execution. Gigaphoton allows providing the solutions with chipmakers best scenario in terms of both schedule bases and availability maximization. Simultaneously therefore, chipmaker should gain the efficiency of productivity enhancement through Gigaphoton AMAX solution, as well as module lifetime extension.

Multi-patterning techniques with ArF immersion lithography is expected to continue as main solution for manufacturing IC chips. The reduction of laser downtime has great impact on the productivity of chipmakers. The laser downtime is closely related to the lifetime of consumable parts of the laser. Gigaphoton has developed longer life excimer laser chamber which contains a new technology “New-type G-electrode”. This new type excimer laser chamber demonstrated 1.3 times longer lifetime than conventional excimer laser chamber. Gigaphoton has also introduced new design of LNM (Line Narrowing Module) last year. Through combines timing of maintenance of new type excimer laser chamber and new type LNM, it’s expected that the downtime of the laser is significantly reduced than ever. This leads to the improvement of the throughput on ArFi lithography.

In advanced DRAM fabrication, wafer alignment is a key enabler to meet on-product overlay performance requirement. Due to the extreme complexity of patterning and integration process involved, it’s becoming a challenge to design alignment marks that can be patterned robustly through process window, meet process integration constraints, withstand large process variation or changes, and provide accurate alignment measurement, during early development. The unique tilted pattern in DRAM fabrication technology poses special challenges during both design and process phase. In this paper, we present a holistic computational approach to design robust alignment marks with ASML’s integrated Design for Control (D4C) and OPC solutions. With this integrated solution, we design a complex set of alignment marks for the entire full flow process from FEOL through BEOL, tailored by each stack of different lithography layers. In mark design stage, marks’ signal and robustness are optimized by D4C simulation, taking into account the design rule and process constraints, while patterning fidelity and process window of these marks is ensured by OPC, subject to the design rule constraints. We demonstrate that the process window (PW) of the resulting alignment marks, especially for the challenging layers with extreme off-axis illuminations and tight design constraints, are significantly improved, while simultaneously accurate and robust alignment measurements are obtained on full loop wafers.

In recent years, DUV light source used in lithography process is enabling to shrink the feature size as a driver for Moore's law, in order to push the physical limits of semiconductor device. E95, also known as spectral bandwidth, is one of the most important parameters in the semiconductor lithography process. Light source is required to push E95 to be tighter in order to improve image contrast, and also required to improve E95 control technology to contribute to OPE (Optical Proximity Effect) error reduction. Therefore, measurement accuracy is crucial important to measure spectral bandwidth. Current measurement error is 5.6 fm (femtometers) when E95 is 300 fm, under a standard spectral metrology tool as ELIAS (Echelle Based Spectrometers produced by LASERTECHNIK BERLIN GmbH). Gigaphoton's recent technology successfully reduced the E95 target value from the existing 300 fm to 200 fm by decreasing the optical thermal load for the LNM (Line-Narrowing Module) [1]. Under current measurement method, the error will be increased, when E95 is set at 200 fm. In order to resolve this problem, Gigaphoton uses a grating base spectral measurement, to reduce the error, by optical engineering improvement and high-resolution spectrum measurement. This ultra-high-resolution measurement impact to OPE error reduction.