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Proceedings Paper

PMJ panel discussion overview: mask manufacturing with massive or multi-parallel method
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Paper Abstract

Computational lithography appeared with people's expectation expanding to reduce total lithography cost and to push the resolution limit for launching novel LSI fabrication processes and masks toward advanced LSI devices of 22 nm and beyond. Recently computational lithography grows up into an integration step to achieve the optimum solution between an illumination source and a mask for creating the resist image on a wafer. This integration scheme enables us not only to achieve ultimate single exposure but also to attain higher resolution beyond the physical limitation by means of double patterning technique. The advanced computational lithography requires massive data volume that urges us to construct further effective multi parallel methods. Photomask Japan highlighted the computational lithography in a panel discussion titled "Mask Manufacturing with Massive or Multi-parallel Method" and sub-titled "Massive or Multi-parallel" drives 22 nm (half pitch 32 nm) litho-mask solution?" We reached a conclusion of "Enhancing computation power and more sophisticated computation methods could solve the difficulties about further complicated computation".

Paper Details

Date Published: 23 September 2009
PDF: 12 pages
Proc. SPIE 7488, Photomask Technology 2009, 748805 (23 September 2009); doi: 10.1117/12.835786
Show Author Affiliations
Minoru Sugawara, Sony Semiconductor Kyusyu Corp. (Japan)
Kokoro Kato, SII NanoTechnology Inc. (Japan)

Published in SPIE Proceedings Vol. 7488:
Photomask Technology 2009
Larry S. Zurbrick; M. Warren Montgomery, Editor(s)

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