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Proceedings Paper

Noble approach for mask-wafer measurement by design-based metrology integration system
Author(s): Hiroaki Mito; Katsuya Hayano; Tatsuya Maeda; Hiroshi Mohri; Hidetoshi Sato; Ryoichi Matsuoka; Shigeki Sukegawa
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Paper Abstract

OPC technique is getting more complicated toward 32nm and below technology node, i.e. from moderate OPC to aggressive OPC. Also, various types of phase shift mask have been introduced, and then the manufacturing process of them is complicated now. In order to shorten TAT (Turn around time) time, mask technique need be considered in addition to lithography technique. Furthermore, the lens aberration of the exposure system is getting smaller, so the current performance of it is very close to the ideal. On the other hand, when down sizing goes down to 32nm technology node, it starts to be reported that there are cases that size cannot be matched between a mask pattern and the corresponding printed pattern. Therefore, it is very indispensable to understand the pattern sizes correlation between a mask and the corresponding printed wafer in order to improve the accuracy and the quality, in the situation that the device size is so small that low k1 lithography had been developed and widely used in a production. Then it is thought that it is one of the approaches to improve an estimated accuracy of lithography by using contour that was extracted from mask SEM image in addition to mask model. This paper describes a newly developed integration system in order to solve issues above, and the applications. This is a system which integrates CG4500; CD-SEM for mask and CG4000; CD SEM for wafer; using DesignGauge; OPC evaluation system by Hitachi High-Technologies. It was investigated that a measurement accuracy improvement by executing a mask-wafer same point measurement with same measurement algorithm utilizing the new system. At first, we measured patterns described on a mask and verified the validity based on a measurement value, picture, measurement parameter and the coordinate. Then create a job file for a wafer CD-SEM using the system so as to measure the same patterns that were exposed using the mask. In addition, average CD measurement was tried in order to improve the correlation. Also, in order to estimate very accurate pattern shape, a contour was calculated from a mask SEM image, the result and the design data was used in a litho simulation. This realizes verification including mask error. It is thought that it is beneficial for both mask maker and device maker to use this system.

Paper Details

Date Published: 29 September 2009
PDF: 9 pages
Proc. SPIE 7488, Photomask Technology 2009, 748832 (29 September 2009); doi: 10.1117/12.834229
Show Author Affiliations
Hiroaki Mito, Hitachi High-Technologies Corp. (Japan)
Katsuya Hayano, Dai Nippon Printing Co., Ltd. (Japan)
Tatsuya Maeda, Hitachi High-Technologies Corp. (Japan)
Hiroshi Mohri, Dai Nippon Printing Co., Ltd. (Japan)
Hidetoshi Sato, Hitachi High-Technologies Corp. (Japan)
Ryoichi Matsuoka, Hitachi High-Technologies Corp. (Japan)
Shigeki Sukegawa, Hitachi High-Technologies Corp. (Japan)

Published in SPIE Proceedings Vol. 7488:
Photomask Technology 2009
Larry S. Zurbrick; M. Warren Montgomery, Editor(s)

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