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Proceedings Paper

A combined space-time multiplex architecture for a stacked smart sensor chip
Author(s): A. Loos; M. Schmidt; A. Graupner; D. Fey; R. Schüffny
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Paper Abstract

We present a fine-grain parallel processor architecture which considers particularly the requirements defined by future 3-dimensional (3D) stacked optoelectronic devices. The architecture concept is well-suited for novel detector arrays which are exploited in data communication applications based on high-speed VCSEL photonic interconnects as well as for optical sensing applications in smart CMOS camera chips. We assume the presence of a two-dimensional optoelectronic interface mounted on top of the stacked device. Such a vertical communication scheme is perfect for the realization of very compact and fast working devices in embedded systems, e.g. in gripper arms of robots.

Paper Details

Date Published: 21 April 2006
PDF: 9 pages
Proc. SPIE 6185, Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration, 61850H (21 April 2006); doi: 10.1117/12.662287
Show Author Affiliations
A. Loos, Friedrich-Schiller-Univ. (Germany)
M. Schmidt, Friedrich-Schiller-Univ. (Germany)
A. Graupner, Dresden Univ. of Technology (Germany)
D. Fey, Friedrich-Schiller-Univ. (Germany)
R. Schüffny, Dresden Univ. of Technology (Germany)

Published in SPIE Proceedings Vol. 6185:
Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration
Hugo Thienpont; Mohammad R. Taghizadeh; Peter Van Daele; Jürgen Mohr, Editor(s)

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