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Proceedings Paper

Maximization of layout printability/manufacturability by extreme layout regularity
Author(s): Tejas Jhaveri; Larry Pileggi; Vyacheslav Rovner; Andrzej J. Strojwas
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Paper Abstract

In the past, complying with design rules was sufficient to ensure acceptable yields for a design. However, for sub 100nm designs, this approach tends to create patterns which cannot be reliably printed for a given optical setup, thus leading to hot-spots and systematic yield failures. The recent challenges faced by both the design and process communities call for a paradigm shift whereby circuits are constructed from a small set of lithography friendly patterns which have previously been extensively characterized and ensured to print reliably. In this paper, we describe the use of a regular design fabric for defining the underlying silicon geometries of the circuit. While the direct application of this methodology to the current ASIC design flow would result in unnecessary area and performance overhead, we overcome these penalties via a unique design flow that ensures shape-level regularity by reducing the number of required logic functions as much as possible as part of the top-down design flow. It will be shown that with a small set of Boolean functions and careful selection of lithography friendly patterns, we not only mitigate but essentially eliminate such penalties. Additionally, we discuss the benefits of using extremely regular designs constructed from a limited set of lithography friendly patterns not only to improve manufacturability but also to relax the pessimistic constraints defined by design rules. Specifically we introduce the basis for the use of "pushed-rules" for logic design as is commonly done for SRAM designs. This in turn facilitates a common OPC methodology for logic and SRAM. Moreover, by taking advantage of this newfound manufacturability and predictability of regular circuits, we will show that the performance of logic built upon regular fabrics can surpass that of seemingly more arbitrarily constructed logic.

Paper Details

Date Published: 24 March 2006
PDF: 15 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 615609 (24 March 2006); doi: 10.1117/12.659984
Show Author Affiliations
Tejas Jhaveri, Carnegie Mellon Univ. (United States)
Larry Pileggi, Carnegie Mellon Univ. (United States)
Vyacheslav Rovner, Carnegie Mellon Univ. (United States)
Andrzej J. Strojwas, Carnegie Mellon Univ. (United States)

Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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