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Proceedings Paper

DFM requirements and solution roadmaps: the multilayer approach
Author(s): Juan Antonio Carballo; Sani Nassif
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Paper Abstract

Design For Manufacturability (DFM) has emerged as a major driver as the semiconductor industry continues on its historic scaling trend. The International Technology Roadmap for Semiconductors (ITRS) Design Group has engaged in a major overhaul of the Design Technology Roadmap, including a completely new section focused on DFM. As part of that overhaul, it was observed that quantifying and road-mapping DFM requires effective yet simple models that can relate broad technology characteristics to specific circuit performances such as delay and power. In this article, we discuss the general topic of DFM roadmaps, and show a simple performance model built upon a canonical circuit and analytical solution that is parameterized such that it can address the DFM roadmap problem. We also show that for important model parameters such as threshold voltage, it may be necessary to apportion the various spaces of variability.

Paper Details

Date Published: 13 March 2006
PDF: 9 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560Y (13 March 2006); doi: 10.1117/12.659302
Show Author Affiliations
Juan Antonio Carballo, IBM Corp. (United States)
Sani Nassif, IBM Corp. (United States)

Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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