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Proceedings Paper

The use of optical proximity correction to compensate for reflectivity differences in N type and P type poly-silicon
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Paper Abstract

Semiconductor manufacturing technologies typically include a number of processes which involve complex physical and chemical interactions. Since it is almost impossible to fully control those interactions, different processes typically have variations that can cause significant deviation of the properties of printed integrated circuit. However, if a process variation is predictable and systematic, OPC techniques can successfully be applied to compensate for those process variations by modifying the layout. One such process variation relates to topographic variation on a wafer surface, which can cause defocusing during an optical lithography process. The nominal-focus aerial image of the layout should ideally be coincides with the wafer surface. In reality, topographic variation on the wafer surface can cause portions of the wafer's surface to be deviated from the nominal focal plane. This can result in defocused aerial image on the wafer causing line width variation of transistor gates during manufacturing process. This problem can be minimized by using anti-reflective coatings as well as differential biasing of the n-type, n-type, and field polysilicon. However, even after application of these two techniques, some residual error remains because the ARC layers are not fully absorbent. Moreover, the biasing techniques also induce process problems at the transition point between the biases and unbiased gate regions. In fact, required applied biases gradually become difficult to manage during technology node migrations. This paper presents a system that accurately determines critical dimension layout by compensating for the effects of topography variation on the performance of an optical lithography process. In this study, a model form and its empirical calibration process have been presented.

Paper Details

Date Published: 14 March 2006
PDF: 7 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61561F (14 March 2006); doi: 10.1117/12.656732
Show Author Affiliations
Lawrence S. Melvin III, Synopsys, Inc. (United States)
Jensheng Huang, Synopsys, Inc. (United States)

Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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