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Proceedings Paper

Annotated layout optimization
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Paper Abstract

The annotation of electrical information or constraints is a well established method to transfer information on design intent from the electrical to the physical designer. In this paper, we will discuss the possibility to extend the concept of annotation as vehicle to hand over critical information from the physical designer to the resolution enhancement technique (RET) engineer. Opportunities and implications to extend the existing optical proximity correction (OPC) methods from the current stage of "just print the layout on wafer" towards new approaches where the layout can be optimized during the RET/OPC step based on designers input are discussed. In addition, the benefit of using process variation information for this layout optimization will be compared to a conventional OPC approach that just tries to realize an overlapping process window at one point of the process window. The power of a combination of both approaches will be shown, based on a small test case. The target of this work is to motivate further research and development in this direction to enhance the current OPC/RET capabilities towards a more integrated solution enabling annotated layout optimization as link between design and manufacturing.

Paper Details

Date Published: 13 March 2006
PDF: 11 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 615605 (13 March 2006); doi: 10.1117/12.656428
Show Author Affiliations
Jörg Thiele, Infineon Technologies AG (Germany)
Roderick Köhle, Infineon Technologies AG (Germany)


Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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