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Proceedings Paper

Lithography window check before mask tape-out in sub-0.18um technology
Author(s): Mark Lu; Dion King; Flora Li; Zhibiao Mao; Curtis Liang; Lawrence S. Melvin III
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Paper Abstract

Lithography Rule Check (LRC) becomes a necessary procedure for post OPC in 0.15μm LV and below technology in order to guarantee mask layout correctness. LRC uses a process model to simulate the mask pattern and compare its performance to the desired layout. When the results are out of specified tolerances, LRC will generate error flags as weak points to trigger further checks. This paper introduces LRC to detect the weak points even in non-OPC employed circuit layout such as 0.18μm to 0.15μm process. LRC is more important for semiconductor foundry since there are diverse design layouts and shrinks in production. This diversity leads to the possibility of problematic structures reaching the reticle. In this work, LRC is added as a necessary step in tape-out procedure for the sub 0.18μm process nodes. LRC detected weak points such as low or excessive contrast sites, high MEEF areas and small process window features, then modified the layout according to check results. Our work showed some mask related potential problems can be avoided by LRC in even non model based OPC process and therefore guarantee improved product yield.

Paper Details

Date Published: 14 March 2006
PDF: 8 pages
Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 61560X (14 March 2006); doi: 10.1117/12.655851
Show Author Affiliations
Mark Lu, Shanghai Institute of Microsystem And Information Technology (China)
Grace Semiconductor Manufacturing Corp. (China)
Graduate School of the Chinese Academy of Sciences (China)
Dion King, Grace Semiconductor Manufacturing Corp. (China)
Flora Li, Grace Semiconductor Manufacturing Corp. (China)
Zhibiao Mao, Grace Semiconductor Manufacturing Corp. (China)
Curtis Liang, Grace Semiconductor Manufacturing Corp. (China)
Lawrence S. Melvin III, Synopsys, Inc. (United States)

Published in SPIE Proceedings Vol. 6156:
Design and Process Integration for Microelectronic Manufacturing IV
Alfred K. K. Wong; Vivek K. Singh, Editor(s)

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