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Proceedings Paper

Media digital signal processor core design for multimedia application
Author(s): Peng Liu; Guo-jun Yu; Wei-guang Cai; Qing-dong Yao
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Paper Abstract

An embedded single media processor named MediaDSP3200 core fabricated in a six-layer metal 0.18um CMOS process which implemented the RISC instruction set, DSP data processing instruction set and single-instruction-multiple-data (SIMD) multimedia-enhanced instruction set is described. MediaDSP3200 fuses RISC architecture and DSP computation capability thoroughly, which achieves RISC fundamental, DSP extended and single instruction multiple data (SIMD) instruction set with various addressing modes in a unified pipeline stage architecture. These characteristics enhance system digital signal processing performance greatly. The test processor can achieve 32x32-bit multiply-accumulate (MAC) of 320 MOPS, with 16x16-bit MAC of 1280MOPS. The test processor dissipates 600mW at 1.8v, 320MHz. Also, the implementation was primarily standard cell logic design style. MediaDSP3200 targets diverse embedded application systems, which need both powerful processing/control capability and low-cost budget, e.g. set-top-boxes, video conferencing, DTV, etc. MediaDSP3200 instruction set architecture, addressing mode, pipeline design, SIMD feature, split-ALU and MAC are described in this paper. Finally, the performance benchmark based on H.264 and MPEG decoder algorithm are given in this paper.

Paper Details

Date Published: 10 February 2006
PDF: 9 pages
Proc. SPIE 6074, Multimedia on Mobile Devices II, 607410 (10 February 2006); doi: 10.1117/12.647520
Show Author Affiliations
Peng Liu, Zhejiang Univ. (China)
Guo-jun Yu, Zhejiang Univ. (China)
Wei-guang Cai, Zhejiang Univ. (China)
Qing-dong Yao, Zhejiang Univ. (China)

Published in SPIE Proceedings Vol. 6074:
Multimedia on Mobile Devices II
Reiner Creutzburg; Jarmo H. Takala; Chang Wen Chen, Editor(s)

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