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Proceedings Paper

Fast prototyping of an FPGA-based high level image coprocessor using Handel-C
Author(s): K. Benkrid; S. Sukhsawas; S. Belkacemi
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Paper Abstract

FPGA technology enjoys both the high performance of a dedicated hardware solution and the flexibility of software that is offered by its inherent reprogrammability feature. Image Processing is one application area that can benefit greatly from FPGAs performance and flexibility. This paper presents the design and implementation of a high-level reconfigurable image coprocessor on FPGAs using the Handel-C hardware language. The latter allows non hardware specialists to program FPGAs at a high level using a C-like syntax, albeit with hardware architectures in mind. It hence allows for rapid development of FPGA applications. This is illustrated in this paper in the case of an image coprocessor whose instruction set is based on the operators of Image Algebra. Central to this instruction set are the five core neighbourhood operations of Image Algebra: Convolution, Additive Maximum, Additive Minimum, Multiplicative Maximum and Multiplicative Minimum. These are parameterised in terms of the neighbourhood operation’s window coefficients, window size and image size. Handel-C language was used to design the Image Coprocessor with a fully tested prototype on Celoxica Virtex-E based RC1000-PP PCI board. The paper presents an overview of the approach used to generate FPGA architectures dynamically for the Image Coprocessor using Handel-C, as well as a sample of implementation results.

Paper Details

Date Published: 1 June 2005
PDF: 9 pages
Proc. SPIE 5823, Opto-Ireland 2005: Imaging and Vision, (1 June 2005); doi: 10.1117/12.604961
Show Author Affiliations
K. Benkrid, The Queen's Univ. of Belfast (United Kingdom)
S. Sukhsawas, The Queen's Univ. of Belfast (United Kingdom)
S. Belkacemi, The Queen's Univ. of Belfast (United Kingdom)

Published in SPIE Proceedings Vol. 5823:
Opto-Ireland 2005: Imaging and Vision
Fionn D. Murtagh, Editor(s)

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