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Proceedings Paper

Fabrication challenges and opportunities for high-mobility materials: from CMOS applications to emerging derivative technologies
Author(s): N. Collaert; A. Alian; B. De Jaeger; U. Peralagu; A. Vais; A. Walke; L. Witters; H. Yu; E. Capogreco; K. Devriendt; T. Hopf; K. Kenis; G. Mannaert; A. Milenin; A. Peter; F. Sebaai; L. Teugels; D. van Dorp; K. Wostyn; N. Horiguchi; N. Waldron
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Paper Abstract

With increasing challenges in reducing power density while keeping and even increasing the device performance at every new technology node, innovations in both the device architecture and materials will be needed to ensure continuous improvements in power, performance, area and cost. For the last decade, replacing the Si channel by higher mobility materials like III-V and (Si)Ge has been considered as one of the most challenging innovations needed to further scale down the supply voltage and improve the overall energy efficiency of CMOS circuits. While these materials will not only contribute to enhancing the standard CMOS performance, the possibility of integrating these materials on a Si platform opens exciting new opportunities to build unique circuits, systems and applications. Especially in RF applications, co-integration of III-V/GaN and Si CMOS might be the key enabling technology to provide the speed and power efficiency required for next generation mobile communications. While the device architectures under consideration differ from nowadays ultra-scaled FinFET and nanowire/nanosheet technologies, and their scaling in general is more relaxed, there are significant challenges related to integrating these components on Si substrates. It will need innovations in patterning, deposition and cleaning, next to addressing the challenges of handling these novel materials in a standard CMOS environment. In this work, we will review the status and integration challenges of these materials for both advanced CMOS technologies and RF applications. Focus will be put on the required advancements in etch and deposition needed to enable the integration of these novel materials and devices on a Si platform.

Paper Details

Date Published: 20 March 2019
PDF: 9 pages
Proc. SPIE 10963, Advanced Etch Technology for Nanopatterning VIII, 1096305 (20 March 2019); doi: 10.1117/12.2511746
Show Author Affiliations
N. Collaert, IMEC (Belgium)
A. Alian, IMEC (Belgium)
B. De Jaeger, IMEC (Belgium)
U. Peralagu, IMEC (Belgium)
A. Vais, IMEC (Belgium)
A. Walke, IMEC (Belgium)
L. Witters, IMEC (Belgium)
H. Yu, IMEC (Belgium)
E. Capogreco, IMEC (Belgium)
K. Devriendt, IMEC (Belgium)
T. Hopf, IMEC (Belgium)
K. Kenis, IMEC (Belgium)
G. Mannaert, IMEC (Belgium)
A. Milenin, IMEC (Belgium)
A. Peter, IMEC (Belgium)
F. Sebaai, IMEC (Belgium)
L. Teugels, IMEC (Belgium)
D. van Dorp, IMEC (Belgium)
K. Wostyn, IMEC (Belgium)
N. Horiguchi, IMEC (Belgium)
N. Waldron, IMEC (Belgium)

Published in SPIE Proceedings Vol. 10963:
Advanced Etch Technology for Nanopatterning VIII
Richard S. Wise; Catherine B. Labelle, Editor(s)

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