Share Email Print
cover

Proceedings Paper

Methodology for determining CD-SEM measurement condition of sub-20nm resist patterns for 0.33NA EUV lithography
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

A novel methodology was established for determining critical dimension scanning electron microscope (CD-SEM) optimum measurement condition of sub-20 nm resist patterns for 0.33NA EUV lithography yielding both small shrinkage and high precision. To investigate dependency of resist shrinkage on pattern size and electron beam irradiation condition, shrinkage of 18, 32, and 45 nm EUV resist patterns was measured over a wide range of beam conditions. A shrinkage trend similar to that of ArF resist patterns was observed for 32 and 45 nm, but 18 nm pattern showed a different dependence on acceleration voltage. Conventional methodology developed for ArF resist pattern to predict shrinkage and precision using the Taguchi method was applied to EUV resist pattern to examine the extendibility of the method. Predicted shrinkage by Taguchi method for 32 and 45 nm patterns agreed with measurements. However, the prediction error increases considerably as the pattern size decreases from 32 to 18 nm because there is a significant interaction between acceleration voltage and irradiated electron dose in L18 array used in the Taguchi method. Thus, we proposed a new method that consists of separated prediction procedures of shrinkage and precision using both a shrinkage curve and the Taguchi method, respectively. The new method was applied to 18 nm EUV resist pattern, and the optimum measurement condition with shrinkage of 1.5 nm and precision of 0.12 nm was determined. Our new method is a versatile technique which is applicable not only to fine EUV resist pattern but also to ArF resist pattern.

Paper Details

Date Published: 19 March 2015
PDF: 13 pages
Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 94240H (19 March 2015); doi: 10.1117/12.2175841
Show Author Affiliations
Nobuhiro Okai, Hitachi, Ltd. (Japan)
Erin Lavigne, IBM Semiconductor Research and Development Ctr. (United States)
Keiichiro Hitomi, Hitachi, Ltd. (Japan)
Scott Halle, IBM Semiconductor Research and Development Ctr. (United States)
Shoji Hotta, Hitachi, Ltd. (Japan)
Shunsuke Koshihara, Hitachi High-Technologies Corp. (Japan)
Junichi Tanaka, Hitachi, Ltd. (Japan)
Todd Bailey, IBM Semiconductor Research and Development Ctr. (United States)


Published in SPIE Proceedings Vol. 9424:
Metrology, Inspection, and Process Control for Microlithography XXIX
Jason P. Cain; Martha I. Sanchez, Editor(s)

© SPIE. Terms of Use
Back to Top