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Proceedings Paper

A new paradigm for in-line detection and control of patterning defects
Author(s): Stefan Hunsche; Marinus Jochemsen; Vivek Jain; Xinjian Zhou; Frank Chen; Venu Vellanki; Chris Spence; Sandip Halder; Dieter van den Heuvel; Vincent Truffert
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Paper Abstract

With continuously shrinking design rules and corresponding low-k1 lithography, defectivity and yield are increasingly dominated by systematic patterning defects. The size of these yield-limiting defects is shrinking along with feature size, making their detection and verification more difficult. We discuss a novel, holistic approach to pattern defect detection and control, which integrates full chip layout analysis and hybrid wafer metrology data to predict wafer locations with highest probability for defect occurrence. We assess the various components of this flow by an experimental study on a 10 nm BEOL process at IMEC, using state-of-the-art negative tone development (NTD) and triple Litho-Etch patterning process.

Paper Details

Date Published: 19 March 2015
PDF: 12 pages
Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 94241B (19 March 2015); doi: 10.1117/12.2087178
Show Author Affiliations
Stefan Hunsche, ASML/Brion Technologies (United States)
Marinus Jochemsen, ASML/Brion Technologies (United States)
Vivek Jain, ASML/Brion Technologies (United States)
Xinjian Zhou, ASML/Brion Technologies (United States)
Frank Chen, ASML/Brion Technologies (United States)
ASML Brion (United States)
Venu Vellanki, ASML/Brion Technologies (United States)
Chris Spence, ASML/Brion Technologies (United States)
Sandip Halder, IMEC (Belgium)
Dieter van den Heuvel, IMEC (Belgium)
Vincent Truffert, IMEC (Belgium)

Published in SPIE Proceedings Vol. 9424:
Metrology, Inspection, and Process Control for Microlithography XXIX
Jason P. Cain; Martha I. Sanchez, Editor(s)

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