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Proceedings Paper

Virtual overlay metrology for fault detection supported with integrated metrology and machine learning
Author(s): Hong-Goo Lee; Emil Schmitt-Weaver; Min-Suk Kim; Sang-Jun Han; Myoung-Soo Kim; Won-Taik Kwon; Sung-Ki Park; Kevin Ryan; Thomas Theeuwes; Kyu-Tae Sun; Young-Wan Lim; Daan Slotboom; Michael Kubis; Jens Staecker
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Paper Abstract

While semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory, an increased emphasis has been placed on reducing the influence known contributors have toward the on product overlay budget. With a machine learning technique known as function approximation, we use a neural network to gain insight to how known contributors, such as those collected with scanner metrology, influence the on product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system. As a real world application, inline metrology can be used to measure overlay for a few wafers while using the trained function to approximate overlay vector maps for the entire lot of wafers. With the approximated overlay vector maps for all wafers coming off the track, a process engineer can redirect wafers or lots with overlay signatures outside the standard population to offline metrology for excursion validation. With this added flexibility, engineers will be given more opportunities to catch wafers that need to be reworked, resulting in improved yield. The quality of the derived corrections from measured overlay metrology feedback can be improved using the approximated overlay to trigger, which wafers should or shouldn’t be, measured inline. As a development or integration engineer the approximated overlay can be used to gain insight into lots and wafers used for design of experiments (DOE) troubleshooting. In this paper we will present the results of a case study that follows the machine learning function approximation approach to data analysis, with production overlay measured on an inline metrology system at SK hynix.

Paper Details

Date Published: 19 March 2015
PDF: 6 pages
Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 94241T (19 March 2015); doi: 10.1117/12.2085475
Show Author Affiliations
Hong-Goo Lee, SK Hynix, Inc. (Korea, Republic of)
Emil Schmitt-Weaver, ASML Netherlands B.V. (Netherlands)
Min-Suk Kim, SK Hynix, Inc. (Korea, Republic of)
Sang-Jun Han, SK Hynix, Inc. (Korea, Republic of)
Myoung-Soo Kim, SK Hynix, Inc. (Korea, Republic of)
Won-Taik Kwon, SK Hynix, Inc. (Korea, Republic of)
Sung-Ki Park, SK Hynix, Inc. (Korea, Republic of)
Kevin Ryan, ASML Netherlands B.V. (Netherlands)
Thomas Theeuwes, ASML Netherlands B.V. (Netherlands)
Kyu-Tae Sun, ASML Netherlands B.V. (Netherlands)
Young-Wan Lim, ASML Netherlands B.V. (Netherlands)
Daan Slotboom, ASML Netherlands B.V. (Netherlands)
Michael Kubis, ASML Netherlands B.V. (Netherlands)
Jens Staecker, ASML Netherlands B.V. (Netherlands)

Published in SPIE Proceedings Vol. 9424:
Metrology, Inspection, and Process Control for Microlithography XXIX
Jason P. Cain; Martha I. Sanchez, Editor(s)

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