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Proceedings Paper

Study on immersion lithography defectivity improvement in memory device manufacturing
Author(s): Weiming He; Huayong Hu; Qiang Wu
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Paper Abstract

As integrated circuit (IC) industry steps into immersion lithography’s era, defectivity in photolithography becomes more complex which requires more efforts in the analysis and solution finding when compared to traditional dry lithographic process. In this paper, we focus on one type of immersion defect from memory or flash memory devices with typical mask layouts. Since the use of self-aligned double patterning (SADP) or other double patterning techniques, the original single pattern layer has to be split into 2 mask layers: logic area vs cell area. One characteristic of such split process is that the total mask transmission rate (TR) is above 70%, with extended open area and a pattern area with a transmission rate close to 50%. This indicates that it may have special defect mechanism and type compared to logic devices. We have found one type of residue defect with center ring-like map. We have studied this defect with different development recipes and analyzed their underlying mechanisms. We have also studied the effect of different immersion photoresists including types with top-coating and without top-coating, as well as the effect of bottom anti-reflection coating (BARC) substrate (organic-BARC/Si-BARC). The results of our study will be presented and discussed.

Paper Details

Date Published: 10 April 2015
PDF: 8 pages
Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 94242M (10 April 2015); doi: 10.1117/12.2085457
Show Author Affiliations
Weiming He, Semiconductor Manufacturing International Corp. (China)
Huayong Hu, Semiconductor Manufacturing International Corp. (China)
Qiang Wu, Semiconductor Manufacturing International Corp. (China)


Published in SPIE Proceedings Vol. 9424:
Metrology, Inspection, and Process Control for Microlithography XXIX
Jason P. Cain; Martha I. Sanchez, Editor(s)

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