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Proceedings Paper

14-bit pipeline-SAR ADC for image sensor readout circuits
Author(s): Gengyun Wang; Can Peng; Tianzhao Liu; Cheng Ma; Ning Ding; Yuchun Chang
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Paper Abstract

A two stage 14bit pipeline-SAR analog-to-digital converter includes a 5.5bit zero-crossing MDAC and a 9bit asynchronous SAR ADC for image sensor readout circuits built in 0.18um CMOS process is described with low power dissipation as well as small chip area. In this design, we employ comparators instead of high gain and high bandwidth amplifier, which consumes as low as 20mW of power to achieve the sampling rate of 40MSps and 14bit resolution.

Paper Details

Date Published: 13 March 2015
PDF: 7 pages
Proc. SPIE 9403, Image Sensors and Imaging Systems 2015, 94030L (13 March 2015); doi: 10.1117/12.2083307
Show Author Affiliations
Gengyun Wang, Jilin Univ. (China)
Can Peng, Jilin Univ. (China)
Tianzhao Liu, Jilin Univ. (China)
Cheng Ma, Jilin Univ. (China)
Ning Ding, Jilin Univ. (China)
Yuchun Chang, Jilin Univ. (China)

Published in SPIE Proceedings Vol. 9403:
Image Sensors and Imaging Systems 2015
Ralf Widenhorn; Antoine Dupret, Editor(s)

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