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Proceedings Paper

Synthesis of regular very large scale integration (VLSI) architectures for the 1D discrete wavelet transform
Author(s): Jose Fridman; Elias S. Manolakos
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Paper Abstract

A methodology for synthesizing parallel computational structures has been applied to the Discrete Wavelet Transform algorithm. It is based on linear space-time mapping with constraint driven localization. The data dependence analysis, localization of global variables, and space-time mapping is presented, as well as one realization of a 3-octave systolic array. The DWT algorithm may not be described by a set of Uniform or Affine Recurrence Equations (UREs, AREs), thus it may not be efficiently mapped onto a regular array. However it is still possible to map the DWT algorithm to a systolic array with local communication links by using first a non-linear index space transformation. The array derived here has latency of 3M/2, where M is the input sequence length, and similar area requirements as solutions proposed elsewhere. In the general case of an arbitrary number of octaves, linear space-time mapping leads to inefficient arrays of long latency due to problems associated with multiprojection.

Paper Details

Date Published: 11 October 1994
PDF: 12 pages
Proc. SPIE 2303, Wavelet Applications in Signal and Image Processing II, (11 October 1994); doi: 10.1117/12.188779
Show Author Affiliations
Jose Fridman, Northeastern Univ. (United States)
Elias S. Manolakos, Northeastern Univ. (United States)

Published in SPIE Proceedings Vol. 2303:
Wavelet Applications in Signal and Image Processing II
Andrew F. Laine; Michael A. Unser, Editor(s)

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