Interests: Metrology technologies, modeling, algorithm and applications for advanced lithography and manufacturing.
Inventor of in-chip overlay metrology, which has been adopted worldwide and are regarded as essential for the most advanced semiconductor processes. Evaluated optimal printing parameters and established appropriate methodologies, demonstrated the effectiveness on 45/55/65 nm node production wafer at TSMC.
Lead metrology-process integration in ITRI-TSMC-Nanometrics joint develop project of in-chip overlay metrology. Developed 2D/3D image formation model to optimize the overlay target design for specific process layers. Developed image asymmetric algorithm to determine overlay with nanometer sensitivity.
Developed optical metrology for advanced manufacturing industry at ITRI. Collaborated on overlay metrology with TSMC/IBM/AMD/Nanometrics, established effective performance metrics.
Managed broadband spectral reflectometry research and applications for determining high aspect ratio TSV (Through Silicon Vias) depth and bottom shape. Enabled 3D interconnect metrology market penetration and new system sales.