Ushasree Katakamsetty

Broad experience in various aspects of physical place & route, low power, design rule development, physical verification, DFM, test chip design and semiconductor process development

Specialties:
. Physical Place & Route with low power features, RTL-GDS flow
. Hands on experience on all major EDA tools used for VLSI chip design
. PEX, Static timing analysis and Physical verification DRC & LVS
. DFM Rule based and Model based up to the advanced process nodes of 14nm
. Testchip design, layout, testing methodology, metrology data collection and analysis
. CMP modeling, Fill synthesis, Manufacturability weak points analysis and fixing