Nanotube-based Electronics Enable Smaller Circuits

Nanotube-based electronics use multiple carbon nanotubes fixed to substrates that are subjected to complex deformations during manufacturing. Conventional manufacturing methods use chemical vapor deposition for growing nanotubes in a pattern on a silicon chip, however, this process does not control the direction of nanotube growth, makes it difficult to separate metallic from semiconducting nanotubes, and produces nanotubes with larger diameters than required for electronic switches.

Physicists at the University of Pennsylvania (Phila-delphia, PA) circumvented these issues by growing large quantities of 200- to 300-nm-long single-walled carbon nanotubes (SWNTs) with average diameters near 1 nm. The physicists used a high-pressure carbon monoxide (HiPCO) method.

The group's approach to making useful electronic devices from SWNTs is to start with bulk material and process it so that individual SWNTs are suspended in a solution of water and surfactant. Positions on the substrate where SWNTs are supposed to go are then covered with a self-assembled molecular monolayer that acts as "glue" for the surfactant-coated SWNTs. When the substrate is dipped into a SWNT suspension, SWNTs stick in the desired locations. The surfactant is then removed, and metal electrodes are fabricated using ordinary lithographic techniques to complete the electrical circuit.

"The properties of carbon nanotubes are so remarkable, it seems as if nature has created them for application in electronic devices," says A. T. Charlie Johnson, Jr., of the research group. The team purified the HiPCO material to remove the amorphous carbon and other impurities, recovering approximately 95% of the original SWNT content. "The circuits made from purified material had resis-tances 200-2000 times lower [better] than similar circuits made from unpurified SWNTs [5 Mohm to 500 Kohm]," Johnson says.

The current target application focuses on SWNT mole-cular sensor arrays. In the long term, it may be possible to design microprocessors to have integrated SWNT inter-connects and/or transistor channels.