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SPIE Photonics Europe 2018 | Call for Papers

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Nanotechnology

Plasma etch challenges for next-generation semiconductor manufacturing

Alternative fabrication schemes based on concurrent engineering of plasma etching can overcome the limitations inherent in optical lithography and thus help to achieve ever smaller device dimensions.
18 August 2017, SPIE Newsroom. DOI: 10.1117/2.1201706.006842

In the photolithography process, a requisite mask layout is printed into a polymer layer. This layer, in turn, is transferred onto underlying inorganic/organic material layers for the fabrication of 3D semiconductors, and for high-volume integrated-chip manufacturing. Moore's law describes a trend, first observed in 1965, in which the dimension of patterns in these layouts shrinks every two years, doubling the number of transistors on the microchip.

Optical lithography has long since reached its physical limit (i.e., printing feature sizes below 40nm), and a number of alternative printing/material deposition schemes have been evaluated for use below this limit (see Figure 1) to maintain the economy of scaling. Among these schemes, plasma etching (which transfers the printed mask layout onto underlying layers by initiating chemical reactions) is employed industry-wide. Plasma is partially ionized gas (i.e., which contains gas atoms/molecules, activated radicals, and ions). The dry plasma etching process involves interactions—between radicals and the exposed surface—which lead to the removal/volatilization of the activated/modified layer via energetic ion bombardment. To optimize the etch process, the pressure, gas flow/flow ratios, radio frequency power, and substrate temperature can be modified by adjusting the appropriate tuning knobs. When one of these tuning knobs is adjusted, change is triggered in more than one of the plasma parameters (i.e., the radical flux, ion flux, ion energy, and ion energy distribution). In a continuous plasma-etch process, surface modification (activation) and energetic material removal (desorption) occur concurrently. Concurrence is problematic, however, because changing plasma parameters to improve one aspect of the printed mask transfer may degrade another. Balancing the plasma parameters and radical/ion flux ratio with the ion energy is therefore essential to achieve an optimized result.


Figure 1. Alternative patterning schemes able to achieve feature sizes of less than 40nm: 193nm immersion lithography combined with self-aligned multiple patterning; extreme UV (EUV) lithography; and directed self-assembly (DSA). Each color represents a different material layer. SADP: Self-aligned double patterning. SAQP: Self-aligned quadruple patterning. SAOP: Self-aligned octuple patterning.1

In our work,2 we used extreme UV (EUV)-lithography-based patterning to investigate the impact of key plasma parameters on the transfer fidelity of sub-40nm patterns. EUV resist masks are very thin and thus require high etch-rate selectivity to bring about transfer onto the layer beneath. Improving on the initial pattern roughness, which occurs due to the high incoming line-edge roughness (LER) of the as-developed image, is equally important. Typical challenges associated with plasma-etch pattern transfer include maintaining a number of key features: high selectivity to mask material; a highly anisotropic/vertical sidewall profile; no aspect-ratio dependent etching (ARDE); uniform etch rates across the whole wafer; the dimensions defined in the mask (referred to as the critical dimension, CD); and minimum roughness of the patterns (measured as LER and line width roughness, LWR).

Directed self-assembly (DSA) patterning presents an additional challenge in the form of polymer-to-polymer selectivity (i.e., one polymer domain needs to be removed while the other is kept intact). As device dimensions shrink, the aforementioned requirements become increasingly challenging due to the trade-offs encountered when multiple process knobs and plasma parameters are managed. The ‘trade-off triangle’ (i.e., the process knob/plasma parameter structure metric) is illustrated in Figure 2. All metrics must be met everywhere on the processed wafer, including at the challenging extreme edge.


Figure 2. Schematic representation of the ‘trade-off triangle,’ illustrating the typical trade-offs encountered during the plasma etching of materials for semiconductor fabrication.2CD: Critical dimension. LER: Line-edge roughness. ARDE: Aspect-ratio dependent etching.

Using a capacitively coupled plasma source, we were able to navigate the trade-off triangle to find optimal conditions for the radical/ion ratio, ion energy, and fluorocarbon plasma-based polymer passivation. We were thus able to achieve good pattern transfer into a metal-based hard mask layer (see Figure 3). Our results indicate that to achieve the best results (in terms of selectivity and improvement to the roughness in the fabricated resist), a balance is needed between passivation gas flow and the modulation of ion energy. In particular, our study on the plasma-etch development of DSA underscores the importance of ion energy and achieving an optimal radical/ion ratio for better selectivity and LER. Harnessing the ion energy regime between the sputter threshold for two polymer domains is the key to obtaining high selectivity, and synergy between radical flux and ion flux in this ion energy regime aids in roughness correction.


Figure 3. Example of an optimized plasma-etch pattern transfer, obtained via EUV and DSA lithography.

As semiconductor technology nodes3 advance toward 7nm and smaller, the trade-off triangle shrinks even further. Particularly critical is the need to control surface damage that occurs due to energetic ion bombardment. As a result, it will become increasingly difficult to navigate and locate the optimal process condition within that space (i.e., the range of available functional equipment parameters). The use of continuous plasma does not allow precise individual control over the plasma parameters. Given the inescapable cross-hardware variabilities in the infrastructure of fabrication facilities, the process space may be even smaller than industry-wide accepted tolerances. The need therefore arises to overcome (or escape) such trade-offs in continuous plasma etching.

We have demonstrated the importance of decoupling the activation process from the desorption of the modified layer in time space to achieve precise control over the etching process and minimize/escape trade-offs via atomic layer etching (ALE) of silicon (see Figure 4).4 In the case of silicon etching, one cannot always operate in a self-limiting regime due to productivity constraints. Careful management of ion energy and the radical-to-ion flux ratio is critical under such circumstances.


Figure 4. Schematic representation showing the difference between continuous plasma etch (reactive-ion etch) and precision plasma etch (atomic-layer etch, ALE).

Our results confirm that the gas chemistry, mask material, etching film, and etch-stop layer form a unique combination for each unit-process application in the fabrication scheme of whole-semiconductor integrated chips.5 Each combination requires separate study of the chemical and physical mechanisms of surface modification and process space. We have outlined the broad categories of surface-modification methods and mechanisms for common dielectric and conductor films.5 For example, in the case of dielectric material etching (where self-limiting chemistries are not available), we find that control over film growth is essential for obtaining precision etch solutions. A similar framework can be defined and implemented for other material-film combinations. However, much more research is required regarding the many combinations of activation precursors/material-film surfaces and their interactions to enable the optimization of the activation step. In one recent study, Sherpa and co-workers have developed a novel all-dry process solution for the precision etching of silicon nitride.6

The new frontier of semiconductor device fabrication will rely on collaboration between the computational and experimental communities to facilitate our understanding of the fundamental material properties and interactions at the atomic/near-atomic scale. This approach will enable the formation of ever-decreasing device dimensions with high fidelity and electrical reliability. We are now actively pursuing vehicles for control over surface modification through the use of advanced quantum chemistry simulation tools, in tandem with conventional experimental approaches. Our endgame is to link this approach to a broader framework—including plasma equipment simulation, plasma chemistry simulation, and device simulation—with fast feedback from real-time process development.

The authors would like to thank Alexander Oscilowski and Peter Biolsi at Tokyo Electron (TEL) Technology Center, America, LLC for their encouragement and enthusiastic support during our investigative studies.


Vinayak Rastogi
Etch Systems
TEL Technology Center, America, LLC
Albany, NY

Vinayak Rastogi obtained his PhD in chemical and biomolecular engineering from North Carolina State University. He is currently a senior member of the fundamental research and development team at TEL Technology Center, America, LLC. He is involved with the development of precision-etch processes for front- and back-end-of-the-line applications for technology nodes of 10nm and beyond.

Peter L. G. Ventzek
Tokyo Electron America, Inc.
Austin, TX

Peter L. G. Ventzek received his PhD in nuclear engineering from the University of Michigan. He is a fellow of the American Vacuum Society, manager of the Austin Plasma Laboratory, and a senior member of technical staff at Tokyo Electron America Inc.

Alok Ranjan
Tokyo Electron Miyagi Limited
Miyagi, Japan

Alok Ranjan received his PhD in chemical engineering from the University of Houston, Texas. He is the director and a senior member of technical staff in the etch division of Tokyo Electron Limited, where he currently leads advanced plasma-etch process development and diagnostics.


References:
1. H. Yaegashi, K. Oyama, A. Hara, S. Natori, S. Yamauchi, M. Yamato, Sustainable scaling technique on double-patterning process, SPIE Proc. 8682, p. 868204, 2013. doi:10.1117/12.2011359
2. V. Rastogi, G. Beique, L. Sun, H. Cottle, Y. Feurprier, A. Metz, K. Kumar, C. Labelle, J. Arnold, et al., Plasma etch patterning of EUV lithography: balancing roughness and selectivity trade off, SPIE Proc. 9782, p. 97820B, 2016. doi:10.1117/12.2216840
3. http://www.itrs2.net/2013-itrs.html International Technology Roadmap for Semiconductors, 2013. Accessed 27 May 2017.
4. A. Ranjan, M. Wang, S. D. Sherpa, V. Rastogi, P. L. G. Ventzek, A. Koshiishi, Implementation of atomic layer etching of silicon: scaling parameters, feasibility, and profile control, J. Vac. Sci. Technol. A 34, p. 31304, 2016.
5. P. L. G. Ventzek, S. D. Sherpa, M. Wang, V. Rastogi, A. Ranjan, Control of atomic layer reactions in plasma processing, ECS Trans. 75(6), p. 25-32, 2016.
6. S. D. Sherpa, A. Ranjan, Quasi-atomic layer etching of silicon nitride, J. Vac. Sci. Technol. A 35(1), p. 01A102, 2017.