Modern trends in processing, metrology, and control for integrated circuits

In his speech at the SPIE Advanced Lithography Conference 2012, senior vice president and general manager of operations at Qualcomm CDMA Technologies, Jim Clifford, called for aggressive scaling of the semiconductor (SC) industry. The mobile market is growing fast, he said, and requires more computing power and memory, lower energy consumption, and reduced-cost silicon. Further challenges include the need for optical patterning using 193nm photolithography, with critical dimension (CD) of near 10nm, and sophisticated deep-UV (DUV) 3D circuitry integration at the atomic scale. Manufacturers require subnanometer accuracy in CD metrology (monitoring and process control of the smallest dimensions of technology nodes), and an unprecedented level of control to maintain high yield and profitability.

DUV immersion photolithography—where light is used to transfer shapes from a mask to a photoresist—is currently the key patterning technique. To reduce CDs, one approach is directed self-assembly,¹ which uses photolithography to produce a guiding structure that is deposited with self-assembling molecules, creating a final pattern with a smaller CD. Today, developers are experimenting with this method to reduce CDs of holes and trenches² and to aid various 3D integration schemes. Directed self-assembly is a response not only to the challenges of optical patterning with CDs of less than 10nm, but also to the growing difficulties of metrology.

Optical CD (OCD) metrology, a well-established in-line technique based on scatterometry, suffers from continued reduction in feature dimensions (signal weakening) and complicated 3D integration, which has resulted in steady growth of the number of parameters for OCD model fitting.³ Various approaches have sought to reduce the measurement uncertainty (MU) of scatterometry,^{4, 5} including one that combines the data of several CD metrologies (OCD, CD-scanning electron microscopy, CD-atomic force microscopy, and high-resolution transmission electron microscopy) to deliver subnanometer MU. However, this approach comes at a high cost.⁵ Directed self-assembly would remove the need for CD metrology altogether because of the intrinsic stability of the process and its ‘ self-control.’

Real-world solutions for accurate metrology and process control generally have limited accuracy.^{6, 7} Manufacturing today often achieves product yield by narrowing the process window and using semi-empirical controls and tuning. Increasingly, yield engineers find weak correlation between in-line metrology data and the resulting electrical characteristics of fabricated transistors and circuits. In this situation, direct measurement of the electrical characteristics would be the most accurate—and arguably the most cost-effective—approach to process control.

To supplement in-line metrology and inspection tools at the early development stage, leading integrated circuit (IC) manufacturers use nanometer-sized probes to connect to terminals in the IC for electrical characterization of transistors and circuit debugging (see Figure 1). This approach, for testing and engineering within the circuitry, provides more realistic, relevant results than classic wafer acceptance testing and transistor parametric testing performed on special test structures in scribe lines.

Figure 1. Eight nanoprobes are landed at Metal 1. Pulses with rise and fall times as short as 10ns characterize an in-die static random-access memory (SRAM) device (top). Butterfly probing an SRAM bit cell with six to eight nanoprobes at Metal 1 yields voltage transfer curves and static noise margins at multiple VDD (power supply voltage) values (bottom). CH: Cell high (voltage). CL: Cell low (voltage).

Recent progress in nanoprobing technology—namely, improvement in throughput, stability, reliability, accuracy, and ease of use—has made electrical probing increasingly attractive not only for conventional IC failure analysis and debugging, but also for transistor design, circuit, and process development, and even for yield engineering.

While leading IC manufacturers have shown the greatest adoption of nanoprobing techniques, advanced companies that outsource manufacture (‘fabless’) have also shown significant interest in the technology. Nanoprobing allows fabless companies to perform early characterization and verification of device and circuit performance, enabling them to partner more effectively with foundries. Importantly, fabless companies can undertake such verification securely, using their proprietary circuit layout information. This enables them to adopt a new technology quickly, and to reduce the cost of development and time to market for their most advanced and profitable products.

In summary, nanoprobing is a growing transistor and circuit test technique expanding into technology development, yield, and product engineering from traditional circuit debugging. Nanoprobing benefits virtually any advanced SC technology, and is rapidly spreading to advanced logic, memory, and analog SC development and manufacturing. A possible next step is nanoprobing for in-line process development and control, which would be advantageous for technology development and manufacturing. However, for that to happen, there must be significant improvements in nanoprobing, such as automation of probing process flow and data processing.