Spie Press Book • on sale3D IC Devices, Technologies, and Manufacturing
|Format||Member Price||Non-Member Price|
The process of scaling integrated circuit (IC) chips has become more challenging as the feature size has been pushed into nanometer-technology nodes. In order to extend the scaling, engineers and scientists have attempted to not only shrink the feature size in x and y directions but also push IC devices into the third dimension.
This book discusses the advantages of 3D devices and their applications in dynamic random access memory (DRAM), 3D-NAND flash, and advanced-technology-node CMOS ICs. Topics include the development of DRAM cell transistors and storage node capacitors; the manufacturing process of advanced buried-word-line DRAM; 3D FinFET CMOS IC devices; scaling trends of CMOS logic; devices that may be used in the "post-CMOS" era; and 3D technologies, such as the 3D-wafer process integration of silicon-on-ILD and TSV-based 3D packaging.
Table of Contents
- 1 Manufacturing Processes of 3D IC Devices
- 1.1 Introduction
- 1.2 3D Devices in the DRAM and BWL DRAM process
- 1.2.1 DRAM introduction
- 1.2.2 3D devices in DRAM
- 1.2.3 BWL DRAM manufacturing processes
- 1.3 Brief summary of DRAM
- 1.4 Review questions
- 2 3D-NAND Flash and Its Manufacturing Process
- 2.1 Introduction
- 2.2 3D-NAND Flash Memory Manufacturing Processes
- 2.2.1 Peripheral module
- 2.2.2 Multi-layer deposition and staircase formation
- 2.2.3 Channel module
- 2.2.4 Isolation module
- 2.2.5 Contact and interconnection modules
- 2.3 3D-NAND Summary and Discussion
- 2.4 Review Questions
- 3 High-k, Metal-Gate FinFET CMOS Manufacturing Process
- 3.1 Introduction
- 3.2 FinFET Basics
- 3.3 FinFET Process
- 3.4 Advanced FinFET CMOS Process
- 3.5 Advanced FinFET SRAM
- 3.6 FinFET CMOS Scaling
- 3.7 Review Questions
- 4 Summary and Future Trends of the 3D IC Process
- 4.1 Scaling MOSFET after 14 nm
- 4.2 Scaling and Development of Memory Devices
- 4.3 3D Packaging
- 4.4 Other 3D Devices and 3D IC Processing Techniques
- 4.5 The End of Moore's Law?
My first exposure to semiconductor industry was in 1975 at the Microwave Diode Department of Chengdu Guoguang Electric Co. with my middle-school classmates during a month-long "learn from workers" program [very common for Chinese children during the chaotic period of the "Cultural Revolution" (1966 to 1976)]. The silicon wafer size was 1 inch, and we were making crystal diodes used in radar as a microwave detector. The factory had several process bays, such as diffusion, wet clean, wafer dicing, assembly, and final test. I watched workers push the wafers into the pyrogenic oxidation furnace and was amazed by the barely visible bluish hydrogen flame in it. I still remember the story of a hydrogen-leakage-induced explosion told during safety training. I worked in final test, using a special instrument to test the diode and determine whether it passed or needed to be thrown into the trash bin underneath the tester.
Twenty years later, I started my career in the semiconductor industry. The wafer size at that time was 200 mm, and the technology node was 350 nm. When the first edition of my textbook Introduction to Semiconductor Manufacturing Technology was published by Prentice Hall in 2000, the technology had scaled down to 180 nm, and copper metallization was the state-of-the-art technology.
Ten years after publication of the first edition, the wafer size increased to 300 mm, and the technology node migrated to 32 nm. New technologies that were not mentioned in the first edition, such as immersion lithography, double patterning, selective epitaxial growth (SEG), and atomic layer deposition (ALD), were widely used to manufacturing IC chips with high-k, metal-gate front-end and copper, ultra-low-k back-end. It became the main driving force for me to write the second edition of the book.
There are many new developments since I have summited the final manuscript of the second edition in the spring of 2012. Because simply scaling down the feature size of the planar MOSFET can no longer improve the device performance while reducing its power consumption, scientists and engineers have worked on scaling nanometer-scale electronic devices in the third dimension. FinFET is one such proposed device architecture that has been used to replace planar MOSFET. At the same feature size, FinFET can improve the drive current by increasing the effective gate width at on-state while reducing standby leakage by operating with a fully depleted regime at off-state. Theoretically, FinFET can migrate to the next-generation-technology node by just increasing fin height without shrinking the feature size. Because it is easier to control the fin height of the FinFET with the silicon thickness of the silicon-on-insulator (SOI) substrate, it was thought that FinFET needed a SOI wafer. Due to the high-cost of SOI wafers and the difficulties of fin height control with low-cost bulk-silicon wafers, many people regarded FinFET as a high-risk approach for the 22-nm or 20-nm technology node, even as late as 2009. In the summer of 2012, Intel announced its 22-nm FinFET at the Symposium on VLSI Technology. Although FinFET was mentioned in the second edition published by SPIE Press at the end of 2012, it was not elaborated upon due to the lack of credible information about its manufacturing processes.
In recent years, the manufacturing technology of non-volatile memory (NVM), especially NAND flash memory, has developed rapidly, driven by the demands of data storage for mobile electronics devices, such as smartphones, tablet PCs, digital cameras/camcorders, etc. Multiple patterning is required to manufacture the planar NAND flash-memory chips due to the limitation of 193-nm immersion lithography. The cost of triple patterning or quadruple patterning required by the low-teen-nm planar NAND flash will become too high, and scientists and engineers have proposed and developed an alternative vertical NAND or 3D-NAND technology that utilizes the gate-all-around vertical transistors to stack multiple memory cells in the vertical direction. In 2014, Samsung released a solid state drive (SSD) based on 3D-NAND with 32 stacks of NVM - only seven years after Toshiba published the concept. A SSD with 48-stack 3D-NAND is also available on the market. With 3D-NAND architecture, one can scale to a next-generation-technology node by increasing the number of stacks without shrinking the feature size. The second edition of Introduction to Semiconductor Manufacturing Technology mentions 3D-NAND in the last chapter, which discusses future trends. The future becomes reality in a very short time.
Another technology mentioned in the second edition but not described in detail is 3D packaging with through silicon via (TSV). By stacking multiple chips with TSV, one can increase the device density without shrinking the feature size, which has been limited by the capability of 193-nm immersion lithography technology and the delayed implementation of extreme ultraviolet (EUV) lithography. TSV has long been applied in CMOS image sensor packaging, which forms the tiny camera assembly used in mobile phones, tablets, and laptop. TSV wafer stacking requires very high yield for every wafer that is to be stacked; otherwise, the combined final yield will suffer. Although foundries are still proposing 2.5D packaging with an interposer due to the high cost of TSV 3D packaging, Samsung released the first 3D TSV technology based on DDR4 modules for enterprise servers in 2014.
Many people helped me acquire the information and knowledge needed to write this book; many of them helped me by answering my questions, and some of them helped by asking me questions to which I had no clear answer at that moment, which motivated me to further study and research: Dick James, Oliver Paterson, Hanming Wu, Jong (John) Chen, Chih-Ming Ke, David Fried, Sandy Wen, Xiaodong Wang, Victor Lim, Byoung-Ho Lee, Ming Lei, Qiang Zhao, Kevin Huang, Jeff Zhang, Wee Teck Chia, Takuji Tada, Jeff Barnum, Christina Wang, Paul MacDonald, Chris Mahr, Brian Duffy, Harsh Shiha, Rohan Gosain, Arun Lobo, Neeraj Khanna, Amir Azordegen, and Cecelia Campochiaro, just to name a few.
Figure 2.48 is provided by Coventor. Figures 3.9 to 3.17, used to describe the HKMG FinFET processes, were previously published in TechDesign Forums. These images were generated using Coventor�s SEMulator3D virtual-fabrication software platform.
Colin Xiao, Jarry Xiao, Sameet Shriyan, and Shishir Ramprasad helped me proofread the draft and corrected many English errors. Without the support of my wife, Liu (Lucy) Huang, and sons, Jarry and Colin, it would have been impossible to write and finish this book on time.
My generation grew up in China without television. Thanks to the "Cultural Revolution," there were very few movies for kids in China at that time. So, hungry for movies, I watched anything that projected on the screen. One such film I watched many times was "Mechanical Drawing," an educational film for college students at the Chengdu Institute of Radio Engineering (currently the University of Electronics Science and Technology of China), where my parents worked as professors. Even today, I can still vividly remember this film taught me how a 3D object can be presented by a top view, side view, and face view. The 3D concept and its presentation with a 2D drawing helped me tremendously when I took an IC design class in graduate school. [IC layout is essentially the top view of mechanical drawing with a microscopic scale (maybe it should be called nanoscopic scale now)]. This knowledge was really useful for me to reconstruct the 3D structures of IC devices and figure out the manufacturing processes by correlating the top-view images and cross-section images. I really appreciate the person who showed the film and allowed me, an elementary schooler, to watch it with college students.